2012-01-05 02:29:29 +01:00
|
|
|
/**
|
|
|
|
******************************************************************************
|
|
|
|
* @addtogroup PIOS PIOS Core hardware abstraction layer
|
|
|
|
* @{
|
|
|
|
* @addtogroup PIOS_TIM Timer Functions
|
|
|
|
* @brief PIOS Timer control code
|
|
|
|
* @{
|
|
|
|
*
|
2013-05-19 16:37:30 +02:00
|
|
|
* @file pios_tim.c
|
2012-01-05 02:29:29 +01:00
|
|
|
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
|
|
|
|
* @brief Sets up timers and ways to register callbacks on them
|
|
|
|
* @see The GNU Public License (GPL) Version 3
|
|
|
|
*
|
|
|
|
*****************************************************************************/
|
2013-05-19 16:37:30 +02:00
|
|
|
/*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 3 of the License, or
|
2012-01-05 02:29:29 +01:00
|
|
|
* (at your option) any later version.
|
2013-05-19 16:37:30 +02:00
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful, but
|
|
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
|
|
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
2012-01-05 02:29:29 +01:00
|
|
|
* for more details.
|
2013-05-19 16:37:30 +02:00
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License along
|
|
|
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
2012-01-05 02:29:29 +01:00
|
|
|
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
2011-11-02 08:51:20 +01:00
|
|
|
#include "pios.h"
|
|
|
|
|
2013-03-15 19:42:54 +01:00
|
|
|
#ifdef PIOS_INCLUDE_TIM
|
|
|
|
|
2011-11-02 08:51:20 +01:00
|
|
|
#include "pios_tim_priv.h"
|
|
|
|
|
|
|
|
enum pios_tim_dev_magic {
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_DEV_MAGIC = 0x87654098,
|
2011-11-02 08:51:20 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct pios_tim_dev {
|
2013-05-19 16:37:30 +02:00
|
|
|
enum pios_tim_dev_magic magic;
|
2011-11-02 08:51:20 +01:00
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
const struct pios_tim_channel *channels;
|
|
|
|
uint8_t num_channels;
|
2011-11-02 08:51:20 +01:00
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
const struct pios_tim_callbacks *callbacks;
|
|
|
|
uint32_t context;
|
2011-11-02 08:51:20 +01:00
|
|
|
};
|
2013-01-05 18:05:59 +01:00
|
|
|
#define PIOS_TIM_ALL_FLAGS TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4 | TIM_IT_Trigger | TIM_IT_Update
|
2011-11-02 08:51:20 +01:00
|
|
|
|
|
|
|
static struct pios_tim_dev pios_tim_devs[PIOS_TIM_MAX_DEVS];
|
|
|
|
static uint8_t pios_tim_num_devs;
|
2013-05-19 16:37:30 +02:00
|
|
|
static struct pios_tim_dev *PIOS_TIM_alloc(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
struct pios_tim_dev *tim_dev;
|
2011-11-02 08:51:20 +01:00
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
if (pios_tim_num_devs >= PIOS_TIM_MAX_DEVS) {
|
|
|
|
return NULL;
|
|
|
|
}
|
2011-11-02 08:51:20 +01:00
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
tim_dev = &pios_tim_devs[pios_tim_num_devs++];
|
|
|
|
tim_dev->magic = PIOS_TIM_DEV_MAGIC;
|
2011-11-02 08:51:20 +01:00
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
return tim_dev;
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
int32_t PIOS_TIM_InitClock(const struct pios_tim_clock_cfg *cfg)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_DEBUG_Assert(cfg);
|
|
|
|
|
|
|
|
/* Enable appropriate clock to timer module */
|
|
|
|
switch ((uint32_t)cfg->timer) {
|
|
|
|
case (uint32_t)TIM1:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM2:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM3:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM4:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM5:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM6:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM7:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM8:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM9:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM10:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM11:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM11, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM12:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM12, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM13:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t)TIM14:
|
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM14, ENABLE);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Configure the dividers for this timer */
|
|
|
|
TIM_TimeBaseInit(cfg->timer, cfg->time_base_init);
|
|
|
|
|
|
|
|
/* Configure internal timer clocks */
|
|
|
|
TIM_InternalClockConfig(cfg->timer);
|
|
|
|
|
|
|
|
/* Enable timers */
|
|
|
|
TIM_Cmd(cfg->timer, ENABLE);
|
|
|
|
|
|
|
|
/* Enable Interrupts */
|
|
|
|
NVIC_Init(&cfg->irq.init);
|
|
|
|
|
2016-05-24 02:05:26 +02:00
|
|
|
|
|
|
|
// Advanced timers TIM1 & TIM8 need special handling:
|
|
|
|
// There are up to 4 separate interrupts handlers for each advanced timer, but
|
|
|
|
// pios_tim_clock_cfg has provision for only one irq init, so we take care here
|
|
|
|
// to enable additional irq channels that we intend to use.
|
|
|
|
|
|
|
|
|
|
|
|
if (cfg->timer == TIM1) {
|
|
|
|
NVIC_InitTypeDef init = cfg->irq.init;
|
|
|
|
init.NVIC_IRQChannel = TIM1_UP_TIM10_IRQn;
|
|
|
|
NVIC_Init(&init);
|
2016-05-24 11:25:17 +02:00
|
|
|
#if !defined (STM32F401xx) && !defined (STM32F411xE)
|
2016-05-24 02:05:26 +02:00
|
|
|
} else if (cfg->timer == TIM8) {
|
|
|
|
NVIC_InitTypeDef init = cfg->irq.init;
|
|
|
|
init.NVIC_IRQChannel = TIM8_UP_TIM13_IRQn;
|
|
|
|
NVIC_Init(&init);
|
2016-05-24 11:25:17 +02:00
|
|
|
#endif
|
2016-05-24 02:05:26 +02:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
return 0;
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
int32_t PIOS_TIM_InitChannels(uint32_t *tim_id, const struct pios_tim_channel *channels, uint8_t num_channels, const struct pios_tim_callbacks *callbacks, uint32_t context)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_Assert(channels);
|
|
|
|
PIOS_Assert(num_channels);
|
|
|
|
|
|
|
|
struct pios_tim_dev *tim_dev;
|
|
|
|
tim_dev = (struct pios_tim_dev *)PIOS_TIM_alloc();
|
|
|
|
if (!tim_dev) {
|
|
|
|
goto out_fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Bind the configuration to the device instance */
|
|
|
|
tim_dev->channels = channels;
|
|
|
|
tim_dev->num_channels = num_channels;
|
|
|
|
tim_dev->callbacks = callbacks;
|
|
|
|
tim_dev->context = context;
|
|
|
|
|
|
|
|
/* Configure the pins */
|
|
|
|
for (uint8_t i = 0; i < num_channels; i++) {
|
|
|
|
const struct pios_tim_channel *chan = &(channels[i]);
|
|
|
|
|
|
|
|
/* Enable the peripheral clock for the GPIO */
|
2011-11-02 08:51:20 +01:00
|
|
|
/* switch ((uint32_t)chan->pin.gpio) {
|
2013-05-19 16:37:30 +02:00
|
|
|
case (uint32_t) GPIOA:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t) GPIOB:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
|
|
|
break;
|
|
|
|
case (uint32_t) GPIOC:
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
PIOS_Assert(0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
*/ // commented out for now as f4 starts all clocks
|
|
|
|
GPIO_Init(chan->pin.gpio, &chan->pin.init);
|
|
|
|
|
2014-08-16 08:40:37 +02:00
|
|
|
PIOS_DEBUG_Assert(chan->remap);
|
2013-05-19 16:37:30 +02:00
|
|
|
|
|
|
|
// Second parameter should technically be PinSource but they are numerically the same
|
|
|
|
GPIO_PinAFConfig(chan->pin.gpio, chan->pin.pin_source, chan->remap);
|
|
|
|
}
|
|
|
|
|
|
|
|
*tim_id = (uint32_t)tim_dev;
|
|
|
|
|
|
|
|
return 0;
|
2011-11-02 08:51:20 +01:00
|
|
|
|
|
|
|
out_fail:
|
2013-05-19 16:37:30 +02:00
|
|
|
return -1;
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
static void PIOS_TIM_generic_irq_handler(TIM_TypeDef *timer)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
/* Iterate over all registered clients of the TIM layer to find channels on this timer */
|
|
|
|
for (uint8_t i = 0; i < pios_tim_num_devs; i++) {
|
|
|
|
const struct pios_tim_dev *tim_dev = &pios_tim_devs[i];
|
|
|
|
|
|
|
|
if (!tim_dev->channels || tim_dev->num_channels == 0) {
|
|
|
|
/* No channels to process on this client */
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check for an overflow event on this timer */
|
|
|
|
bool overflow_event;
|
|
|
|
uint16_t overflow_count;
|
|
|
|
if (TIM_GetITStatus(timer, TIM_IT_Update) == SET) {
|
|
|
|
TIM_ClearITPendingBit(timer, TIM_IT_Update);
|
|
|
|
overflow_count = timer->ARR;
|
|
|
|
overflow_event = true;
|
|
|
|
} else {
|
|
|
|
overflow_count = 0;
|
|
|
|
overflow_event = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (uint8_t j = 0; j < tim_dev->num_channels; j++) {
|
|
|
|
const struct pios_tim_channel *chan = &tim_dev->channels[j];
|
|
|
|
|
|
|
|
if (chan->timer != timer) {
|
|
|
|
/* channel is not on this timer */
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Figure out which interrupt bit we should be looking at */
|
|
|
|
uint16_t timer_it;
|
|
|
|
switch (chan->timer_chan) {
|
|
|
|
case TIM_Channel_1:
|
|
|
|
timer_it = TIM_IT_CC1;
|
|
|
|
break;
|
|
|
|
case TIM_Channel_2:
|
|
|
|
timer_it = TIM_IT_CC2;
|
|
|
|
break;
|
|
|
|
case TIM_Channel_3:
|
|
|
|
timer_it = TIM_IT_CC3;
|
|
|
|
break;
|
|
|
|
case TIM_Channel_4:
|
|
|
|
timer_it = TIM_IT_CC4;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
PIOS_Assert(0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool edge_event;
|
|
|
|
uint16_t edge_count;
|
|
|
|
if (TIM_GetITStatus(chan->timer, timer_it) == SET) {
|
|
|
|
TIM_ClearITPendingBit(chan->timer, timer_it);
|
|
|
|
|
|
|
|
/* Read the current counter */
|
|
|
|
switch (chan->timer_chan) {
|
|
|
|
case TIM_Channel_1:
|
|
|
|
edge_count = TIM_GetCapture1(chan->timer);
|
|
|
|
break;
|
|
|
|
case TIM_Channel_2:
|
|
|
|
edge_count = TIM_GetCapture2(chan->timer);
|
|
|
|
break;
|
|
|
|
case TIM_Channel_3:
|
|
|
|
edge_count = TIM_GetCapture3(chan->timer);
|
|
|
|
break;
|
|
|
|
case TIM_Channel_4:
|
|
|
|
edge_count = TIM_GetCapture4(chan->timer);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
PIOS_Assert(0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
edge_event = true;
|
|
|
|
} else {
|
|
|
|
edge_event = false;
|
|
|
|
edge_count = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!tim_dev->callbacks) {
|
|
|
|
/* No callbacks registered, we're done with this channel */
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Generate the appropriate callbacks */
|
|
|
|
if (overflow_event & edge_event) {
|
|
|
|
/*
|
|
|
|
* When both edge and overflow happen in the same interrupt, we
|
|
|
|
* need a heuristic to determine the order of the edge and overflow
|
|
|
|
* events so that the callbacks happen in the right order. If we
|
|
|
|
* get the order wrong, our pulse width calculations could be off by up
|
|
|
|
* to ARR ticks. That could be bad.
|
|
|
|
*
|
|
|
|
* Heuristic: If the edge_count is < 16 ticks above zero then we assume the
|
|
|
|
* edge happened just after the overflow.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (edge_count < 16) {
|
|
|
|
/* Call the overflow callback first */
|
|
|
|
if (tim_dev->callbacks->overflow) {
|
|
|
|
(*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
|
|
|
|
tim_dev->context,
|
|
|
|
j,
|
|
|
|
overflow_count);
|
|
|
|
}
|
|
|
|
/* Call the edge callback second */
|
|
|
|
if (tim_dev->callbacks->edge) {
|
|
|
|
(*tim_dev->callbacks->edge)((uint32_t)tim_dev,
|
|
|
|
tim_dev->context,
|
|
|
|
j,
|
|
|
|
edge_count);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Call the edge callback first */
|
|
|
|
if (tim_dev->callbacks->edge) {
|
|
|
|
(*tim_dev->callbacks->edge)((uint32_t)tim_dev,
|
|
|
|
tim_dev->context,
|
|
|
|
j,
|
|
|
|
edge_count);
|
|
|
|
}
|
|
|
|
/* Call the overflow callback second */
|
|
|
|
if (tim_dev->callbacks->overflow) {
|
|
|
|
(*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
|
|
|
|
tim_dev->context,
|
|
|
|
j,
|
|
|
|
overflow_count);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (overflow_event && tim_dev->callbacks->overflow) {
|
|
|
|
(*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
|
|
|
|
tim_dev->context,
|
|
|
|
j,
|
|
|
|
overflow_count);
|
|
|
|
} else if (edge_event && tim_dev->callbacks->edge) {
|
|
|
|
(*tim_dev->callbacks->edge)((uint32_t)tim_dev,
|
|
|
|
tim_dev->context,
|
|
|
|
j,
|
|
|
|
edge_count);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Bind Interrupt Handlers
|
|
|
|
*
|
|
|
|
* Map all valid TIM IRQs to the common interrupt handler
|
|
|
|
* and give it enough context to properly demux the various timers
|
|
|
|
*/
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM1_CC_IRQHandler(void) __attribute__((alias("PIOS_TIM_1_CC_irq_handler")));
|
|
|
|
static void PIOS_TIM_1_CC_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM1);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM2_IRQHandler(void) __attribute__((alias("PIOS_TIM_2_irq_handler")));
|
|
|
|
static void PIOS_TIM_2_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM2);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM3_IRQHandler(void) __attribute__((alias("PIOS_TIM_3_irq_handler")));
|
|
|
|
static void PIOS_TIM_3_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM3);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM4_IRQHandler(void) __attribute__((alias("PIOS_TIM_4_irq_handler")));
|
|
|
|
static void PIOS_TIM_4_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM4);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM5_IRQHandler(void) __attribute__((alias("PIOS_TIM_5_irq_handler")));
|
|
|
|
static void PIOS_TIM_5_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM5);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM6_IRQHandler(void) __attribute__((alias("PIOS_TIM_6_irq_handler")));
|
|
|
|
static void PIOS_TIM_6_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM6);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM7_IRQHandler(void) __attribute__((alias("PIOS_TIM_7_irq_handler")));
|
|
|
|
static void PIOS_TIM_7_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM7);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM8_CC_IRQHandler(void) __attribute__((alias("PIOS_TIM_8_CC_irq_handler")));
|
|
|
|
static void PIOS_TIM_8_CC_irq_handler(void)
|
2011-11-02 08:51:20 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
PIOS_TIM_generic_irq_handler(TIM8);
|
2011-11-02 08:51:20 +01:00
|
|
|
}
|
2012-01-05 02:29:29 +01:00
|
|
|
|
2012-12-29 18:28:04 +01:00
|
|
|
// The rest of TIM1 interrupts are overlapped
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM1_BRK_TIM9_IRQHandler(void) __attribute__((alias("PIOS_TIM_9_CC_irq_handler")));
|
|
|
|
static void PIOS_TIM_9_CC_irq_handler(void)
|
2012-12-29 18:28:04 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
if (TIM_GetITStatus(TIM1, TIM_IT_Break)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM1);
|
|
|
|
} else if (TIM_GetITStatus(TIM9, PIOS_TIM_ALL_FLAGS)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM9);
|
|
|
|
}
|
2012-12-29 18:28:04 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM1_UP_TIM10_IRQHandler(void) __attribute__((alias("PIOS_TIM_10_CC_irq_handler")));
|
|
|
|
static void PIOS_TIM_10_CC_irq_handler(void)
|
2012-12-29 18:28:04 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
if (TIM_GetITStatus(TIM1, TIM_IT_Update)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM1);
|
|
|
|
} else if (TIM_GetITStatus(TIM10, PIOS_TIM_ALL_FLAGS)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM10);
|
|
|
|
}
|
2012-12-29 18:28:04 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM1_TRG_COM_TIM11_IRQHandler(void) __attribute__((alias("PIOS_TIM_11_CC_irq_handler")));
|
|
|
|
static void PIOS_TIM_11_CC_irq_handler(void)
|
2012-12-29 18:28:04 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
if (TIM_GetITStatus(TIM1, TIM_IT_COM | TIM_IT_Trigger)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM1);
|
|
|
|
} else if (TIM_GetITStatus(TIM11, PIOS_TIM_ALL_FLAGS)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM11);
|
|
|
|
}
|
2012-12-29 18:28:04 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM8_BRK_TIM12_IRQHandler(void) __attribute__((alias("PIOS_TIM_12_irq_handler")));
|
|
|
|
static void PIOS_TIM_12_irq_handler(void)
|
2012-09-30 20:32:03 +02:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
if (TIM_GetITStatus(TIM8, TIM_IT_Break)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM8);
|
|
|
|
} else if (TIM_GetITStatus(TIM12, PIOS_TIM_ALL_FLAGS)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM12);
|
|
|
|
}
|
2012-09-30 20:32:03 +02:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM8_UP_TIM13_IRQHandler(void) __attribute__((alias("PIOS_TIM8_UP_TIM13_IRQHandler")));
|
|
|
|
static void PIOS_TIM8_UP_TIM13_IRQHandler(void)
|
2012-12-29 18:28:04 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
if (TIM_GetITStatus(TIM8, TIM_IT_Update)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM8);
|
|
|
|
} else if (TIM_GetITStatus(TIM13, PIOS_TIM_ALL_FLAGS)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM13);
|
|
|
|
}
|
2012-12-29 18:28:04 +01:00
|
|
|
}
|
|
|
|
|
2013-05-19 16:37:30 +02:00
|
|
|
void TIM8_TRG_COM_TIM14_IRQHandler(void) __attribute__((alias("PIOS_TIM8_TRG_COM_TIM14_IRQHandler")));
|
|
|
|
static void PIOS_TIM8_TRG_COM_TIM14_IRQHandler(void)
|
2012-12-29 18:28:04 +01:00
|
|
|
{
|
2013-05-19 16:37:30 +02:00
|
|
|
if (TIM_GetITStatus(TIM8, TIM_IT_COM | TIM_IT_Trigger)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM8);
|
|
|
|
} else if (TIM_GetITStatus(TIM14, PIOS_TIM_ALL_FLAGS)) {
|
|
|
|
PIOS_TIM_generic_irq_handler(TIM14);
|
|
|
|
}
|
2012-12-29 18:28:04 +01:00
|
|
|
}
|
2012-09-30 20:32:03 +02:00
|
|
|
|
2013-03-15 19:42:54 +01:00
|
|
|
#endif /* PIOS_INCLUDE_TIM */
|
|
|
|
|
2012-01-05 02:29:29 +01:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
* @}
|
|
|
|
*/
|