1
0
mirror of https://bitbucket.org/librepilot/librepilot.git synced 2025-02-20 10:54:14 +01:00

Sending all FF finally again

This commit is contained in:
James Cotton 2012-02-02 10:36:09 -06:00
parent 80b839d145
commit 0a71a48c57
3 changed files with 16 additions and 6 deletions

View File

@ -154,8 +154,9 @@ int32_t transactionsStarted = 0;
*/
static int32_t transmitData(uint8_t * data, int32_t length)
{
memcpy(tx_buffer,data,length);
memset(tx_buffer + length, 0, sizeof(tx_buffer) - length);
// memcpy(tx_buffer,data,length);
memset(tx_buffer, 6, length);
memset(tx_buffer + length, 3, sizeof(tx_buffer) - length);
int32_t retval = 0;

View File

@ -153,14 +153,17 @@ int32_t PIOS_SPI_Init(uint32_t * spi_id, const struct pios_spi_cfg * cfg)
}
/* Configure DMA for SPI Rx */
DMA_DeInit(spi_dev->cfg->dma.rx.channel);
DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
DMA_Init(spi_dev->cfg->dma.rx.channel, (DMA_InitTypeDef*)&(spi_dev->cfg->dma.rx.init));
/* Configure DMA for SPI Tx */
DMA_DeInit(spi_dev->cfg->dma.tx.channel);
DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
DMA_Init(spi_dev->cfg->dma.tx.channel, (DMA_InitTypeDef*)&(spi_dev->cfg->dma.tx.init));
/* Initialize the SPI block */
SPI_DeInit(spi_dev->cfg->regs);
SPI_Init(spi_dev->cfg->regs, (SPI_InitTypeDef*)&(spi_dev->cfg->init));
/* Configure CRC calculation */
@ -181,7 +184,7 @@ int32_t PIOS_SPI_Init(uint32_t * spi_id, const struct pios_spi_cfg * cfg)
/* Configure DMA interrupt */
NVIC_Init((NVIC_InitTypeDef*)&(spi_dev->cfg->dma.irq.init));
DMA_ITConfig(spi_dev->cfg->dma.tx.channel, spi_dev->cfg->dma.irq.flags, ENABLE); /* XXX is this correct? */
// DMA_ITConfig(spi_dev->cfg->dma.tx.channel, spi_dev->cfg->dma.irq.flags, ENABLE); /* XXX is this correct? */
return(0);
@ -627,6 +630,12 @@ void PIOS_SPI_IRQ_Handler(uint32_t spi_id)
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
} else {
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
}

View File

@ -447,7 +447,7 @@ void PIOS_SPI_flash_irq_handler(void)
*/
void PIOS_SPI_overo_irq_handler(void);
void DMA1_Stream0_IRQHandler(void) __attribute__((alias("PIOS_SPI_overo_irq_handler")));
void DMA1_Stream5_IRQHandler(void) __attribute__((alias("PIOS_SPI_overo_irq_handler")));
void DMA1_Stream7_IRQHandler(void) __attribute__((alias("PIOS_SPI_overo_irq_handler")));
static const struct pios_spi_cfg pios_spi_overo_cfg = {
.regs = SPI3,
.remap = GPIO_AF_SPI3,
@ -495,9 +495,9 @@ static const struct pios_spi_cfg pios_spi_overo_cfg = {
},
},
.tx = {
.channel = DMA1_Stream5,
.channel = DMA1_Stream7,
.init = {
.DMA_Channel = DMA_Channel_5,
.DMA_Channel = DMA_Channel_0,
.DMA_PeripheralBaseAddr = (uint32_t) & (SPI3->DR),
.DMA_DIR = DMA_DIR_MemoryToPeripheral,
.DMA_PeripheralInc = DMA_PeripheralInc_Disable,