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Code Issues Releases Activity

REVONANO - Change Power Regulatro Scale mode to Scale1.

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Looks like stm32f4xx_Clock_Configuration_V1.1.0 seems like doesn't play well with 411. Reg Scale mode was wrong
This commit is contained in:
Alessio Morale 2015-04-20 21:41:23 +02:00
parent c0618258ad
commit 0d714fb861
1 changed files with 2 additions and 2 deletions
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4
flight/pios/stm32f4xx/libraries/CMSIS/Device/ST/STM32F4xx/Source/revonano/system_stm32f4xx.c
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@ -74,7 +74,7 @@
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* VDD(V) | 3.3 * VDD(V) | 3.3
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* Main regulator output voltage | Scale2 mode * Main regulator output voltage | Scale1 mode
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* Flash Latency(WS) | 3 * Flash Latency(WS) | 3
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
@ -375,7 +375,7 @@ static void SetSysClock(void)
/* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */ /* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN; RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR &= (uint32_t)~(PWR_CR_VOS); PWR->CR &= (uint32_t)~(PWR_CR_VOS);
PWR->CR |= PWR_CR_VOS_0 | PWR_CR_VOS_1;
/* HCLK = SYSCLK / 1*/ /* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; RCC->CFGR |= RCC_CFGR_HPRE_DIV1;