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Flight: Updated to the latest StdPeriph libraries

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git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2230 ebee16cc-31ac-478f-84a7-5cbb03baadba
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peabody124 2010-12-13 07:03:24 +00:00 committed by peabody124
parent 9250470c98
commit 18858571ce
54 changed files with 6158 additions and 2625 deletions
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557
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/core_cm3.c Normal file → Executable file
View File

@ -1,16 +1,18 @@
/******************************************************************************
* @file: core_cm3.c
* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version: V1.20
* @date: 22. May 2009
*----------------------------------------------------------------------------
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
@ -19,39 +21,37 @@
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for armcc */
#define __INLINE __inline /*!< inline keyword for armcc */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for iarcc */
#define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for gcc */
#define __INLINE inline /*!< inline keyword for gcc */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
@ -64,8 +64,7 @@ __ASM uint32_t __get_PSP(void)
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
@ -79,8 +78,7 @@ __ASM void __set_PSP(uint32_t topOfProcStack)
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
@ -94,8 +92,7 @@ __ASM uint32_t __get_MSP(void)
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
@ -109,8 +106,8 @@ __ASM void __set_MSP(uint32_t mainStackPointer)
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
@ -123,8 +120,8 @@ __ASM uint32_t __REV16(uint16_t value)
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int16_t value to reverse
* @return int32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
@ -140,9 +137,6 @@ __ASM int32_t __REVSH(int16_t value)
/**
* @brief Remove the exclusive lock created by ldrex
*
* @param none
* @return none
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
@ -153,8 +147,7 @@ __ASM void __CLREX(void)
/**
* @brief Return the Base Priority value
*
* @param none
* @return uint32_t BasePriority
* @return BasePriority
*
* Return the content of the base priority register
*/
@ -167,8 +160,7 @@ __ASM uint32_t __get_BASEPRI(void)
/**
* @brief Set the Base Priority value
*
* @param uint32_t BasePriority
* @return none
* @param basePri BasePriority
*
* Set the base priority register
*/
@ -181,11 +173,9 @@ __ASM void __set_BASEPRI(uint32_t basePri)
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
* @return PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
@ -196,8 +186,7 @@ __ASM uint32_t __get_PRIMASK(void)
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
@ -210,8 +199,7 @@ __ASM void __set_PRIMASK(uint32_t priMask)
/**
* @brief Return the Fault Mask value
*
* @param none
* @return uint32_t FaultMask
* @return FaultMask
*
* Return the content of the fault mask register
*/
@ -224,8 +212,7 @@ __ASM uint32_t __get_FAULTMASK(void)
/**
* @brief Set the Fault Mask value
*
* @param uint32_t faultMask value
* @return none
* @param faultMask faultMask value
*
* Set the fault mask register
*/
@ -238,12 +225,11 @@ __ASM void __set_FAULTMASK(uint32_t faultMask)
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
@ -252,8 +238,7 @@ __ASM uint32_t __get_CONTROL(void)
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
* @param control Control value
*
* Set the control register
*/
@ -266,14 +251,15 @@ __ASM void __set_CONTROL(uint32_t control)
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
@ -286,8 +272,7 @@ uint32_t __get_PSP(void)
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
@ -301,8 +286,7 @@ void __set_PSP(uint32_t topOfProcStack)
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
@ -316,8 +300,7 @@ uint32_t __get_MSP(void)
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
@ -331,8 +314,8 @@ void __set_MSP(uint32_t topOfMainStack)
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
@ -345,8 +328,8 @@ uint32_t __REV16(uint16_t value)
/**
* @brief Reverse bit order of value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
@ -357,12 +340,12 @@ uint32_t __RBIT(uint32_t value)
}
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (8 bit)
*
* @param uint8_t* address
* @return uint8_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
@ -371,12 +354,12 @@ uint8_t __LDREXB(uint8_t *addr)
}
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (16 bit)
*
* @param uint16_t* address
* @return uint16_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
@ -385,12 +368,12 @@ uint16_t __LDREXH(uint16_t *addr)
}
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (32 bit)
*
* @param uint32_t* address
* @return uint32_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
@ -399,13 +382,13 @@ uint32_t __LDREXW(uint32_t *addr)
}
/**
* @brief STR Exclusive
* @brief STR Exclusive (8 bit)
*
* @param uint8_t *address
* @param uint8_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
@ -414,13 +397,13 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr)
}
/**
* @brief STR Exclusive
* @brief STR Exclusive (16 bit)
*
* @param uint16_t *address
* @param uint16_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
@ -429,13 +412,13 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr)
}
/**
* @brief STR Exclusive
* @brief STR Exclusive (32 bit)
*
* @param uint32_t *address
* @param uint32_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
@ -447,12 +430,12 @@ uint32_t __STREXW(uint32_t value, uint32_t *addr)
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
@ -467,12 +450,10 @@ uint32_t __get_PSP(void)
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
@ -487,8 +468,7 @@ void __set_PSP(uint32_t topOfProcStack)
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
@ -507,8 +487,7 @@ uint32_t __get_MSP(void)
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
@ -523,8 +502,7 @@ void __set_MSP(uint32_t topOfMainStack)
/**
* @brief Return the Base Priority value
*
* @param none
* @return uint32_t BasePriority
* @return BasePriority
*
* Return the content of the base priority register
*/
@ -539,8 +517,7 @@ uint32_t __get_BASEPRI(void)
/**
* @brief Set the Base Priority value
*
* @param uint32_t BasePriority
* @return none
* @param basePri BasePriority
*
* Set the base priority register
*/
@ -552,11 +529,9 @@ void __set_BASEPRI(uint32_t value)
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
* @return PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
@ -569,8 +544,7 @@ uint32_t __get_PRIMASK(void)
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
@ -582,8 +556,7 @@ void __set_PRIMASK(uint32_t priMask)
/**
* @brief Return the Fault Mask value
*
* @param none
* @return uint32_t FaultMask
* @return FaultMask
*
* Return the content of the fault mask register
*/
@ -598,8 +571,7 @@ uint32_t __get_FAULTMASK(void)
/**
* @brief Set the Fault Mask value
*
* @param uint32_t faultMask value
* @return none
* @param faultMask faultMask value
*
* Set the fault mask register
*/
@ -608,174 +580,10 @@ void __set_FAULTMASK(uint32_t faultMask)
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Reverse byte order in integer value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int32_t value to reverse
* @return int32_t reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive
*
* @param uint8_t* address
* @return uint8_t value of (*address)
*
* Exclusive LDR command
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive
*
* @param uint16_t* address
* @return uint16_t value of (*address)
*
* Exclusive LDR command
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive
*
* @param uint32_t* address
* @return uint32_t value of (*address)
*
* Exclusive LDR command
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive
*
* @param uint8_t *address
* @param uint8_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive
*
* @param uint16_t *address
* @param uint16_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive
*
* @param uint32_t *address
* @param uint32_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* @return Control value
*
* Return the content of the control register
*/
@ -790,8 +598,7 @@ uint32_t __get_CONTROL(void)
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
* @param control Control value
*
* Set the control register
*/
@ -800,6 +607,171 @@ void __set_CONTROL(uint32_t control)
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
@ -810,20 +782,3 @@ void __set_CONTROL(uint32_t control)
*/
#endif

1277
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/core_cm3.h Normal file → Executable file
View File

@ -1,16 +1,18 @@
/******************************************************************************
* @file: core_cm3.h
* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version: V1.20
* @date: 22. May 2009
*----------------------------------------------------------------------------
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
@ -22,53 +24,38 @@
#ifndef __CM3_CORE_H__
#define __CM3_CORE_H__
#ifdef __cplusplus
extern "C" {
#endif
#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x03) /*!< Cortex core */
/**
* Lint configuration \n
* ----------------------- \n
/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
*
* The following Lint messages will be suppressed and not shown: \n
* \n
* --- Error 10: --- \n
* register uint32_t __regBasePri __asm("basepri"); \n
* Error 10: Expecting ';' \n
* \n
* --- Error 530: --- \n
* return(__regBasePri); \n
* Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
* \n
* --- Error 550: --- \n
* __regBasePri = (basePri & 0x1ff); \n
* } \n
* Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
* \n
* --- Error 754: --- \n
* uint32_t RESERVED0[24]; \n
* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
* \n
* --- Error 750: --- \n
* #define __CM3_CORE_H__ \n
* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
* \n
* --- Error 528: --- \n
* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
* \n
* --- Error 751: --- \n
* } InterruptType_Type; \n
* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
* \n
* \n
* Note: To re-enable a Message, insert a space before 'lint' * \n
* List of Lint messages which will be suppressed and not shown:
* - Error 10: \n
* register uint32_t __regBasePri __asm("basepri"); \n
* Error 10: Expecting ';'
* .
* - Error 530: \n
* return(__regBasePri); \n
* Warning 530: Symbol '__regBasePri' (line 264) not initialized
* .
* - Error 550: \n
* __regBasePri = (basePri & 0x1ff); \n
* Warning 550: Symbol '__regBasePri' (line 271) not accessed
* .
* - Error 754: \n
* uint32_t RESERVED0[24]; \n
* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
* .
* - Error 750: \n
* #define __CM3_CORE_H__ \n
* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
* .
* - Error 528: \n
* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
* .
* - Error 751: \n
* } InterruptType_Type; \n
* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
* .
* Note: To re-enable a Message, insert a space before 'lint' *
*
*/
@ -82,6 +69,24 @@
/*lint -e751 */
/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- Cortex-M core registers and bitfields
- Cortex-M core peripheral base address
@{
*/
#ifdef __cplusplus
extern "C" {
#endif
#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x03) /*!< Cortex core */
#include <stdint.h> /* Include standard types */
#if defined (__ICCARM__)
@ -103,9 +108,9 @@
*/
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
@ -115,188 +120,630 @@
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
@{
*/
/* System Reset */
#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
/* Core Debug */
#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
#define ITM_TCR_ITMENA 1 /*!< ITM enable */
/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
@{
*/
typedef struct
{
__IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
uint32_t RESERVED0[24];
__IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
uint32_t RSERVED1[24];
__IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
uint32_t RESERVED2[24];
__IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
uint32_t RESERVED3[24];
__IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
uint32_t RESERVED4[56];
__IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
uint32_t RESERVED5[644];
__O uint32_t STIR; /*!< Software Trigger Interrupt Register */
} NVIC_Type;
__IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
uint32_t RESERVED0[24];
__IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
uint32_t RSERVED1[24];
__IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
uint32_t RESERVED2[24];
__IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
uint32_t RESERVED3[24];
__IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
uint32_t RESERVED4[56];
__IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644];
__O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
} NVIC_Type;
/*@}*/ /* end of group CMSIS_CM3_NVIC */
/* memory mapping struct for System Control Block */
/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
memory mapped structure for System Control Block (SCB)
@{
*/
typedef struct
{
__I uint32_t CPUID; /*!< CPU ID Base Register */
__IO uint32_t ICSR; /*!< Interrupt Control State Register */
__IO uint32_t VTOR; /*!< Vector Table Offset Register */
__IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
__IO uint32_t SCR; /*!< System Control Register */
__IO uint32_t CCR; /*!< Configuration Control Register */
__IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IO uint32_t SHCSR; /*!< System Handler Control and State Register */
__IO uint32_t CFSR; /*!< Configurable Fault Status Register */
__IO uint32_t HFSR; /*!< Hard Fault Status Register */
__IO uint32_t DFSR; /*!< Debug Fault Status Register */
__IO uint32_t MMFAR; /*!< Mem Manage Address Register */
__IO uint32_t BFAR; /*!< Bus Fault Address Register */
__IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
__I uint32_t PFR[2]; /*!< Processor Feature Register */
__I uint32_t DFR; /*!< Debug Feature Register */
__I uint32_t ADR; /*!< Auxiliary Feature Register */
__I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
__I uint32_t ISAR[5]; /*!< ISA Feature Register */
} SCB_Type;
__I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
__IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
__IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
__IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
__IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
__IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
__IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
__IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
__IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
__IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
__I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
__I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
__I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
__I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
__I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
/*@}*/ /* end of group CMSIS_CM3_SCB */
/* memory mapping struct for SysTick */
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
memory mapped structure for SysTick
@{
*/
typedef struct
{
__IO uint32_t CTRL; /*!< SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< SysTick Reload Value Register */
__IO uint32_t VAL; /*!< SysTick Current Value Register */
__I uint32_t CALIB; /*!< SysTick Calibration Register */
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
/* memory mapping structur for ITM */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */
/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
memory mapped structure for Instrumentation Trace Macrocell (ITM)
@{
*/
typedef struct
{
__O union
{
__O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
__O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
__O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
} PORT [32]; /*!< ITM Stimulus Port Registers */
uint32_t RESERVED0[864];
__IO uint32_t TER; /*!< ITM Trace Enable Register */
uint32_t RESERVED1[15];
__IO uint32_t TPR; /*!< ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< ITM Trace Control Register */
uint32_t RESERVED3[29];
__IO uint32_t IWR; /*!< ITM Integration Write Register */
__IO uint32_t IRR; /*!< ITM Integration Read Register */
__IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
__IO uint32_t LAR; /*!< ITM Lock Access Register */
__IO uint32_t LSR; /*!< ITM Lock Status Register */
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< ITM Product ID Registers */
__I uint32_t PID5;
__I uint32_t PID6;
__I uint32_t PID7;
__I uint32_t PID0;
__I uint32_t PID1;
__I uint32_t PID2;
__I uint32_t PID3;
__I uint32_t CID0;
__I uint32_t CID1;
__I uint32_t CID2;
__I uint32_t CID3;
} ITM_Type;
__O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
__O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
__O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
} PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
uint32_t RESERVED0[864];
__IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
uint32_t RESERVED1[15];
__IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
uint32_t RESERVED3[29];
__IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
__IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
__IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
__IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
__I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
__I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
__I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
__I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
__I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
__I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
__I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
__I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
__I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_CM3_ITM */
/* memory mapped struct for Interrupt Type */
/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
memory mapped structure for Interrupt Type
@{
*/
typedef struct
{
uint32_t RESERVED0;
__I uint32_t ICTR; /*!< Interrupt Control Type Register */
__I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
__IO uint32_t ACTLR; /*!< Auxiliary Control Register */
__IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
#else
uint32_t RESERVED1;
#endif
} InterruptType_Type;
/* Interrupt Controller Type Register Definitions */
#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
/*@}*/ /* end of group CMSIS_CM3_InterruptType */
/* Memory Protection Unit */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
memory mapped structure for Memory Protection Unit (MPU)
@{
*/
typedef struct
{
__I uint32_t TYPE; /*!< MPU Type Register */
__IO uint32_t CTRL; /*!< MPU Control Register */
__IO uint32_t RNR; /*!< MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< MPU Region Base Address Register */
__IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
__IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
__IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
__IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
__IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
__IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
__IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
__I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
__IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
__IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
__IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
__IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
__IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
__IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@}*/ /* end of group CMSIS_CM3_MPU */
#endif
/* Core Debug Register */
/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
memory mapped structure for Core Debug Register
@{
*/
typedef struct
{
__IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
__O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
__IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
__IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
__IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
__O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
__IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
__IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
#define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
#define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
#define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
#endif
/*@}*/ /* end of group CMSIS_CM3_core_register */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
@ -304,8 +751,8 @@ typedef struct
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
@ -344,8 +791,7 @@ typedef struct
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
@ -354,8 +800,7 @@ extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
@ -365,8 +810,7 @@ extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
@ -376,8 +820,7 @@ extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
@ -387,18 +830,18 @@ extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/*
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int16_t value to reverse
* @return int32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
@ -410,9 +853,6 @@ extern int32_t __REVSH(int16_t value);
/**
* @brief Remove the exclusive lock created by ldrex
*
* @param none
* @return none
*
* Removes the exclusive lock which is created by ldrex.
*/
extern void __CLREX(void);
@ -420,8 +860,7 @@ extern void __CLREX(void);
/**
* @brief Return the Base Priority value
*
* @param none
* @return uint32_t BasePriority
* @return BasePriority
*
* Return the content of the base priority register
*/
@ -430,8 +869,7 @@ extern uint32_t __get_BASEPRI(void);
/**
* @brief Set the Base Priority value
*
* @param uint32_t BasePriority
* @return none
* @param basePri BasePriority
*
* Set the base priority register
*/
@ -440,19 +878,16 @@ extern void __set_BASEPRI(uint32_t basePri);
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
* @return PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
* Return state of the priority mask bit from the priority mask register
*/
extern uint32_t __get_PRIMASK(void);
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
@ -461,8 +896,7 @@ extern void __set_PRIMASK(uint32_t priMask);
/**
* @brief Return the Fault Mask value
*
* @param none
* @return uint32_t FaultMask
* @return FaultMask
*
* Return the content of the fault mask register
*/
@ -471,8 +905,7 @@ extern uint32_t __get_FAULTMASK(void);
/**
* @brief Set the Fault Mask value
*
* @param uint32_t faultMask value
* @return none
* @param faultMask faultMask value
*
* Set the fault mask register
*/
@ -481,8 +914,7 @@ extern void __set_FAULTMASK(uint32_t faultMask);
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
* @return Control value
*
* Return the content of the control register
*/
@ -491,8 +923,7 @@ extern uint32_t __get_CONTROL(void);
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
* @param control Control value
*
* Set the control register
*/
@ -500,13 +931,9 @@ extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
/**
* @brief Remove the exclusive lock created by ldrex
*
* @param none
* @return none
*
* Removes the exclusive lock which is created by ldrex.
*/
#define __CLREX __clrex
@ -514,8 +941,7 @@ extern void __set_CONTROL(uint32_t control);
/**
* @brief Return the Base Priority value
*
* @param none
* @return uint32_t BasePriority
* @return BasePriority
*
* Return the content of the base priority register
*/
@ -528,25 +954,22 @@ static __INLINE uint32_t __get_BASEPRI(void)
/**
* @brief Set the Base Priority value
*
* @param uint32_t BasePriority
* @return none
* @param basePri BasePriority
*
* Set the base priority register
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0x1ff);
__regBasePri = (basePri & 0xff);
}
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
* @return PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
* Return state of the priority mask bit from the priority mask register
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
@ -557,8 +980,7 @@ static __INLINE uint32_t __get_PRIMASK(void)
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
@ -571,8 +993,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask)
/**
* @brief Return the Fault Mask value
*
* @param none
* @return uint32_t FaultMask
* @return FaultMask
*
* Return the content of the fault mask register
*/
@ -585,8 +1006,7 @@ static __INLINE uint32_t __get_FAULTMASK(void)
/**
* @brief Set the Fault Mask value
*
* @param uint32_t faultMask value
* @return none
* @param faultMask faultMask value
*
* Set the fault mask register
*/
@ -599,8 +1019,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask)
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
* @return Control value
*
* Return the content of the control register
*/
@ -613,8 +1032,7 @@ static __INLINE uint32_t __get_CONTROL(void)
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
* @param control Control value
*
* Set the control register
*/
@ -637,7 +1055,7 @@ static __INLINE void __set_CONTROL(uint32_t control)
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
static __INLINE void __WFI() { __ASM ("wfi"); }
static __INLINE void __WFE() { __ASM ("wfe"); }
static __INLINE void __SEV() { __ASM ("sev"); }
@ -659,8 +1077,7 @@ static __INLINE void __CLREX() { __ASM ("clrex"); }
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
@ -669,8 +1086,7 @@ extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
@ -680,8 +1096,7 @@ extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
@ -691,8 +1106,7 @@ extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
@ -702,8 +1116,8 @@ extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
@ -712,73 +1126,73 @@ extern uint32_t __REV16(uint16_t value);
/**
* @brief Reverse bit order of value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
extern uint32_t __RBIT(uint32_t value);
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (8 bit)
*
* @param uint8_t* address
* @return uint8_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 8 bit values)
*/
extern uint8_t __LDREXB(uint8_t *addr);
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (16 bit)
*
* @param uint16_t* address
* @return uint16_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 16 bit values
*/
extern uint16_t __LDREXH(uint16_t *addr);
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (32 bit)
*
* @param uint32_t* address
* @return uint32_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 32 bit values
*/
extern uint32_t __LDREXW(uint32_t *addr);
/**
* @brief STR Exclusive
* @brief STR Exclusive (8 bit)
*
* @param uint8_t *address
* @param uint8_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 8 bit values
*/
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
/**
* @brief STR Exclusive
* @brief STR Exclusive (16 bit)
*
* @param uint16_t *address
* @param uint16_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 16 bit values
*/
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
/**
* @brief STR Exclusive
* @brief STR Exclusive (32 bit)
*
* @param uint32_t *address
* @param uint32_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 32 bit values
*/
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
@ -806,8 +1220,7 @@ static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
@ -816,8 +1229,7 @@ extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
@ -827,8 +1239,7 @@ extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
@ -838,8 +1249,7 @@ extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
@ -849,8 +1259,7 @@ extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Return the Base Priority value
*
* @param none
* @return uint32_t BasePriority
* @return BasePriority
*
* Return the content of the base priority register
*/
@ -859,8 +1268,7 @@ extern uint32_t __get_BASEPRI(void);
/**
* @brief Set the Base Priority value
*
* @param uint32_t BasePriority
* @return none
* @param basePri BasePriority
*
* Set the base priority register
*/
@ -869,19 +1277,16 @@ extern void __set_BASEPRI(uint32_t basePri);
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
* @return PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
* Return state of the priority mask bit from the priority mask register
*/
extern uint32_t __get_PRIMASK(void);
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
@ -890,8 +1295,7 @@ extern void __set_PRIMASK(uint32_t priMask);
/**
* @brief Return the Fault Mask value
*
* @param none
* @return uint32_t FaultMask
* @return FaultMask
*
* Return the content of the fault mask register
*/
@ -900,8 +1304,7 @@ extern uint32_t __get_FAULTMASK(void);
/**
* @brief Set the Fault Mask value
*
* @param uint32_t faultMask value
* @return none
* @param faultMask faultMask value
*
* Set the fault mask register
*/
@ -910,8 +1313,7 @@ extern void __set_FAULTMASK(uint32_t faultMask);
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
* @return Control value
*
* Return the content of the control register
*/
@ -920,8 +1322,7 @@ extern uint32_t __get_CONTROL(void);
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
* @param control Control value
*
* Set the control register
*/
@ -930,8 +1331,8 @@ extern void __set_CONTROL(uint32_t control);
/**
* @brief Reverse byte order in integer value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
@ -940,93 +1341,93 @@ extern uint32_t __REV(uint32_t value);
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/*
* Reverse byte order in signed short value with sign extension to integer
*
* @param int16_t value to reverse
* @return int32_t reversed value
*
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
extern int32_t __REVSH(int16_t value);
/**
* @brief Reverse bit order of value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
extern uint32_t __RBIT(uint32_t value);
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (8 bit)
*
* @param uint8_t* address
* @return uint8_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 8 bit value
*/
extern uint8_t __LDREXB(uint8_t *addr);
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (16 bit)
*
* @param uint16_t* address
* @return uint16_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 16 bit values
*/
extern uint16_t __LDREXH(uint16_t *addr);
/**
* @brief LDR Exclusive
* @brief LDR Exclusive (32 bit)
*
* @param uint32_t* address
* @return uint32_t value of (*address)
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command
* Exclusive LDR command for 32 bit values
*/
extern uint32_t __LDREXW(uint32_t *addr);
/**
* @brief STR Exclusive
* @brief STR Exclusive (8 bit)
*
* @param uint8_t *address
* @param uint8_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 8 bit values
*/
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
/**
* @brief STR Exclusive
* @brief STR Exclusive (16 bit)
*
* @param uint16_t *address
* @param uint16_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 16 bit values
*/
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
/**
* @brief STR Exclusive
* @brief STR Exclusive (32 bit)
*
* @param uint32_t *address
* @param uint32_t value to store
* @return uint32_t successful / failed
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command
* Exclusive STR command for 32 bit values
*/
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
@ -1043,15 +1444,20 @@ extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
#endif
/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
Core Function Interface containing:
- Core NVIC Functions
- Core SysTick Functions
- Core Reset Functions
*/
/*@{*/
/* ########################## NVIC functions #################################### */
/**
* @brief Set the Priority Grouping in NVIC Interrupt Controller
*
* @param uint32_t priority_grouping is priority grouping field
* @return none
* @param PriorityGroup is priority grouping field
*
* Set the priority grouping field using the required unlock sequence.
* The parameter priority_grouping is assigned to the field
@ -1064,31 +1470,31 @@ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
reg_value = (reg_value |
(0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
/**
* @brief Get the Priority Grouping from NVIC Interrupt Controller
*
* @param none
* @return uint32_t priority grouping field
* @return priority grouping field
*
* Get the priority grouping from NVIC Interrupt Controller.
* priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
*/
static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
/**
* @brief Enable Interrupt in NVIC Interrupt Controller
*
* @param IRQn_Type IRQn specifies the interrupt number
* @return none
* @param IRQn The positive number of the external interrupt to enable
*
* Enable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
@ -1101,8 +1507,7 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
/**
* @brief Disable the interrupt line for external interrupt specified
*
* @param IRQn_Type IRQn is the positive number of the external interrupt
* @return none
* @param IRQn The positive number of the external interrupt to disable
*
* Disable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
@ -1115,8 +1520,8 @@ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
/**
* @brief Read the interrupt pending bit for a device specific interrupt source
*
* @param IRQn_Type IRQn is the number of the device specifc interrupt
* @return uint32_t 1 if pending interrupt else 0
* @param IRQn The number of the device specifc interrupt
* @return 1 = interrupt pending, 0 = interrupt not pending
*
* Read the pending register in NVIC and return 1 if its status is pending,
* otherwise it returns 0
@ -1129,8 +1534,7 @@ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
/**
* @brief Set the pending bit for an external interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @return none
* @param IRQn The number of the interrupt for set pending
*
* Set the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
@ -1143,8 +1547,7 @@ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
/**
* @brief Clear the pending bit for an external interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @return none
* @param IRQn The number of the interrupt for clear pending
*
* Clear the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
@ -1157,8 +1560,8 @@ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
/**
* @brief Read the active bit for an external interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @return uint32_t 1 if active else 0
* @param IRQn The number of the interrupt for read active bit
* @return 1 = interrupt active, 0 = interrupt not active
*
* Read the active register in NVIC and returns 1 if its status is active,
* otherwise it returns 0.
@ -1171,13 +1574,12 @@ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
/**
* @brief Set the priority for an interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @param priority is the priority for the interrupt
* @return none
* @param IRQn The number of the interrupt for set priority
* @param priority The priority to set
*
* Set the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
* interrupt, or negative to specify an internal (core) interrupt. \n
* interrupt, or negative to specify an internal (core) interrupt.
*
* Note: The priority cannot be set for every core interrupt.
*/
@ -1186,14 +1588,14 @@ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
if(IRQn < 0) {
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
else {
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
/**
* @brief Read the priority for an interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @return uint32_t priority is the priority for the interrupt
* @param IRQn The number of the interrupt for get priority
* @return The priority for the interrupt
*
* Read the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
@ -1217,10 +1619,10 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
/**
* @brief Encode the priority for an interrupt
*
* @param uint32_t PriorityGroup is the used priority group
* @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)
* @param uint32_t SubPriority is the sub priority value (starting from 0)
* @return uint32_t the priority for the interrupt
* @param PriorityGroup The used priority group
* @param PreemptPriority The preemptive priority value (starting from 0)
* @param SubPriority The sub priority value (starting from 0)
* @return The encoded priority for the interrupt
*
* Encode the priority for an interrupt with the given priority group,
* preemptive priority value and sub priority value.
@ -1231,7 +1633,7 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
*/
static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@ -1248,11 +1650,10 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
/**
* @brief Decode the priority of an interrupt
*
* @param uint32_t Priority the priority for the interrupt
* @param uint32_t PrioGroup is the used priority group
* @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
* @param uint32_t* pSubPrio is the sub priority value (starting from 0)
* @return none
* @param Priority The priority for the interrupt
* @param PriorityGroup The used priority group
* @param pPreemptPriority The preemptive priority value (starting from 0)
* @param pSubPriority The sub priority value (starting from 0)
*
* Decode an interrupt priority value with the given priority group to
* preemptive priority value and sub priority value.
@ -1263,7 +1664,7 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
*/
static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@ -1280,17 +1681,11 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
/* SysTick constants */
#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
/**
* @brief Initialize and start the SysTick counter and its interrupt.
*
* @param uint32_t ticks is the number of ticks between two interrupts
* @return none
* @param ticks number of ticks between two interrupts
* @return 1 = failed, 0 = successful
*
* Initialise the system tick timer and its interrupt and start the
* system tick timer / counter in free running mode to generate
@ -1298,13 +1693,15 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
@ -1312,33 +1709,45 @@ static __INLINE uint32_t SysTick_Config(uint32_t ticks)
/* ################################## Reset function ############################################ */
/**
* @brief Initiate a system reset request.
*
* @param none
* @return none
*
* Initialize a system reset request to reset the MCU
* Initiate a system reset request to reset the MCU
*/
static __INLINE void NVIC_SystemReset(void)
{
SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
/* ################################## Debug Output function ############################################ */
/* ##################################### Debug In/Output function ########################################### */
/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
Core Debug Interface containing:
- Core Debug Receive / Transmit Functions
- Core Debug Defines
- Core Debug Variables
*/
/*@{*/
extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
/**
* @brief Outputs a character via the ITM channel 0
*
* @param uint32_t character to output
* @return uint32_t input character
* @param ch character to output
* @return character to output
*
* The function outputs a character via the ITM channel 0.
* The function returns when no debugger is connected that has booked the output.
@ -1346,11 +1755,9 @@ static __INLINE void NVIC_SystemReset(void)
*/
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (ch == '\n') ITM_SendChar('\r');
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
(ITM->TCR & ITM_TCR_ITMENA) &&
(ITM->TER & (1UL << 0)) )
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
(ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
@ -1358,10 +1765,54 @@ static __INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch);
}
/**
* @brief Inputs a character via variable ITM_RxBuffer
*
* @return received character, -1 = no character received
*
* The function inputs a character via variable ITM_RxBuffer.
* The function returns when no debugger is connected that has booked the output.
* It is blocking when a debugger is connected, but the previous character send is not transmitted.
*/
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
* @brief Check if a character via variable ITM_RxBuffer is available
*
* @return 1 = character available, 0 = no character available
*
* The function checks variable ITM_RxBuffer whether a character is available or not.
* The function returns '1' if a character is available and '0' if no character is available.
*/
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}
/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
#ifdef __cplusplus
}
#endif
/*@}*/ /* end of group CMSIS_CM3_core_definitions */
#endif /* __CM3_CORE_H__ */
/*lint -restore */

215
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_cl.s Normal file → Executable file
View File

@ -1,20 +1,21 @@
/**
******************************************************************************
* @file startup_stm32f10x_cl.s
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR
* address.
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
******************************************************************************
* @file startup_stm32f10x_cl.s
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
* @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR
* address.
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -24,8 +25,8 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
.syntax unified
.cpu cortex-m3
@ -60,48 +61,49 @@ defined in linker script */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
@ -111,12 +113,12 @@ Infinite_Loop:
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
@ -157,9 +159,9 @@ g_pfnVectors:
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
@ -180,7 +182,7 @@ g_pfnVectors:
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word OTG_FS_WKUP_IRQHandler
.word OTG_FS_WKUP_IRQHandler
.word 0
.word 0
.word 0
@ -188,63 +190,63 @@ g_pfnVectors:
.word 0
.word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ETH_IRQHandler
.word ETH_WKUP_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word OTG_FS_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ETH_IRQHandler
.word ETH_WKUP_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word OTG_FS_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x Connectivity line Devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
@ -462,3 +464,4 @@ g_pfnVectors:
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler ,Default_Handler
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

97
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_hd.s Normal file → Executable file
View File

@ -1,40 +1,40 @@
/**
******************************************************************************
* @file startup_stm32f10x_hd.s
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure external SRAM mounted on STM3210E-EVAL board
* to be used as data memory (optional, to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
******************************************************************************
* @file startup_stm32f10x_hd.s
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3210E-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
.syntax unified
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global SystemInit_ExtMemCtl_Dummy
.global Default_Handler
/* start address for the initialization values of the .data section.
@ -50,7 +50,6 @@ defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.equ Initial_spTop, 0x20000400
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
@ -66,12 +65,6 @@ defined in linker script */
.type Reset_Handler, %function
Reset_Handler:
/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */
bl SystemInit_ExtMemCtl
/* restore original stack pointer */
LDR r0, =_estack
MSR msp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
@ -99,28 +92,19 @@ LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief Dummy SystemInit_ExtMemCtl function
* @param None
* @retval : None
*/
.section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits
SystemInit_ExtMemCtl_Dummy:
bx lr
.size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
@ -129,18 +113,18 @@ Infinite_Loop:
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word Initial_spTop
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
@ -262,13 +246,12 @@ g_pfnVectors:
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x High Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*
*******************************************************************************/
.weak NMI_Handler
@ -478,6 +461,4 @@ g_pfnVectors:
.weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
.weak SystemInit_ExtMemCtl
.thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

469
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_ld.s Normal file → Executable file
View File

@ -1,50 +1,51 @@
/**
******************************************************************************
* @file startup_stm32f10x_ld.s
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address.
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
******************************************************************************
* @file startup_stm32f10x_ld.s
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
* @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.word _ebss
.equ BootRAM, 0xF108F85F
/**
@ -56,56 +57,57 @@ defined in linker script */
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
@ -113,79 +115,79 @@ Infinite_Loop:
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
0
0
.word SPI1_IRQHandler
0
.word USART1_IRQHandler
.word USART2_IRQHandler
0
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Low Density devices.*/
/*******************************************************************************
@ -196,144 +198,145 @@ g_pfnVectors:
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

492
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_md.s Normal file → Executable file
View File

@ -1,50 +1,51 @@
/**
******************************************************************************
* @file startup_stm32f10x_md.s
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
******************************************************************************
* @file startup_stm32f10x_md.s
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
* @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.word _ebss
.equ BootRAM, 0xF108F85F
/**
@ -56,56 +57,57 @@ defined in linker script */
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
@ -113,79 +115,79 @@ Infinite_Loop:
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
@ -196,160 +198,160 @@ g_pfnVectors:
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

638
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/stm32f10x.h Normal file → Executable file
View File

@ -2,12 +2,14 @@
******************************************************************************
* @file stm32f10x.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F10x Connectivity line, High
* density, Medium density and Low density devices.
* definitions and memory mapping for STM32F10x Connectivity line,
* High density, High density value line, Medium density,
* Medium density Value line, Low density, Low density Value line
* and XL-density devices.
******************************************************************************
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -17,7 +19,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
******************************************************************************
*/
@ -44,24 +46,40 @@
application
*/
#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)
/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
/* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
#define STM32F10X_HD /*!< STM32F10X_HD: STM32 High density devices */
/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
/* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
/* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
/* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
/* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
- Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
- Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
where the Flash memory density ranges between 16 and 32 Kbytes.
- Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
- Low-density value line devices are STM32F100xx microcontrollers where the Flash
memory density ranges between 16 and 32 Kbytes.
- Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
where the Flash memory density ranges between 64 and 128 Kbytes.
- High density devices are STM32F101xx and STM32F103xx microcontrollers where
- Medium-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 64 and 128 Kbytes.
- High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
- High-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
- XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 512 and 1024 Kbytes.
- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
*/
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
#endif
#if !defined USE_STDPERIPH_DRIVER
/**
* @brief Comment the line below if you will not use the peripherals drivers.
@ -78,29 +96,29 @@
Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
*/
#if !defined HSE_Value
#if !defined HSE_VALUE
#ifdef STM32F10X_CL
#define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#else
#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* STM32F10X_CL */
#endif /* HSE_Value */
#endif /* HSE_VALUE */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value
*/
#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
/**
* @brief STM32F10x Standard Peripheral Library version number
*/
#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
| __STM32F10X_STDPERIPH_VERSION_SUB2)
@ -116,7 +134,11 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */
#ifdef STM32F10X_XL
#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
#else
#define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
#endif /* STM32F10X_XL */
#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
@ -155,9 +177,9 @@ typedef enum IRQn
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
#ifdef STM32F10X_LD
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
@ -176,10 +198,32 @@ typedef enum IRQn
USART2_IRQn = 38, /*!< USART2 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
#endif /* STM32F10X_LD */
#ifdef STM32F10X_LD_VL
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
TIM7_IRQn = 55 /*!< TIM7 Interrupt */
#endif /* STM32F10X_LD_VL */
#ifdef STM32F10X_MD
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
@ -203,10 +247,37 @@ typedef enum IRQn
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
#endif /* STM32F10X_MD */
#ifdef STM32F10X_MD_VL
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
TIM7_IRQn = 55 /*!< TIM7 Interrupt */
#endif /* STM32F10X_MD_VL */
#ifdef STM32F10X_HD
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
@ -250,7 +321,94 @@ typedef enum IRQn
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
#endif /* STM32F10X_HD */
#ifdef STM32F10X_HD_VL
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
FSMC_IRQn = 48, /*!< FSMC global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
TIM7_IRQn = 55, /*!< TIM7 Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
mapped at postion 60 only if the MISC_REMAP bit in
the AFIO_MAPR2 register is set) */
#endif /* STM32F10X_HD_VL */
#ifdef STM32F10X_XL
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
FSMC_IRQn = 48, /*!< FSMC global Interrupt */
SDIO_IRQn = 49, /*!< SDIO global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
#endif /* STM32F10X_XL */
#ifdef STM32F10X_CL
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
@ -341,10 +499,6 @@ typedef __I uint32_t vuc32; /*!< Read Only */
typedef __I uint16_t vuc16; /*!< Read Only */
typedef __I uint8_t vuc8; /*!< Read Only */
#ifndef __cplusplus
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
#endif
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
@ -352,6 +506,10 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
#define HSE_Value HSE_VALUE
#define HSI_Value HSI_VALUE
/**
* @}
*/
@ -486,7 +644,7 @@ typedef struct
__IO uint16_t DR42;
uint16_t RESERVED45;
} BKP_TypeDef;
/**
* @brief Controller Area Network TxMailBox
*/
@ -555,6 +713,20 @@ typedef struct
#endif /* STM32F10X_CL */
} CAN_TypeDef;
/**
* @brief Consumer Electronics Control (CEC)
*/
typedef struct
{
__IO uint32_t CFGR;
__IO uint32_t OAR;
__IO uint32_t PRES;
__IO uint32_t ESR;
__IO uint32_t CSR;
__IO uint32_t TXD;
__IO uint32_t RXD;
} CEC_TypeDef;
/**
* @brief CRC calculation unit
*/
@ -587,6 +759,9 @@ typedef struct
__IO uint32_t DHR8RD;
__IO uint32_t DOR1;
__IO uint32_t DOR2;
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
__IO uint32_t SR;
#endif
} DAC_TypeDef;
/**
@ -717,6 +892,14 @@ typedef struct
__IO uint32_t RESERVED;
__IO uint32_t OBR;
__IO uint32_t WRPR;
#ifdef STM32F10X_XL
uint32_t RESERVED1[8];
__IO uint32_t KEYR2;
uint32_t RESERVED2;
__IO uint32_t SR2;
__IO uint32_t CR2;
__IO uint32_t AR2;
#endif /* STM32F10X_XL */
} FLASH_TypeDef;
/**
@ -818,6 +1001,8 @@ typedef struct
__IO uint32_t EVCR;
__IO uint32_t MAPR;
__IO uint32_t EXTICR[4];
uint32_t RESERVED0;
__IO uint32_t MAPR2;
} AFIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
@ -883,10 +1068,16 @@ typedef struct
__IO uint32_t APB1ENR;
__IO uint32_t BDCR;
__IO uint32_t CSR;
#ifdef STM32F10X_CL
__IO uint32_t AHBRSTR;
__IO uint32_t CFGR2;
#endif /* STM32F10X_CL */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
uint32_t RESERVED0;
__IO uint32_t CFGR2;
#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
} RCC_TypeDef;
/**
@ -1060,11 +1251,13 @@ typedef struct
* @{
*/
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
@ -1079,6 +1272,9 @@ typedef struct
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
@ -1095,6 +1291,7 @@ typedef struct
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
@ -1112,6 +1309,12 @@ typedef struct
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
#define SDIO_BASE (PERIPH_BASE + 0x18000)
@ -1163,6 +1366,9 @@ typedef struct
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
@ -1179,6 +1385,7 @@ typedef struct
#define BKP ((BKP_TypeDef *) BKP_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define CEC ((CEC_TypeDef *) CEC_BASE)
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@ -1195,6 +1402,12 @@ typedef struct
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
@ -1580,6 +1793,40 @@ typedef struct
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
/*!< MCO configuration */
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
#else
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
@ -1646,27 +1893,48 @@ typedef struct
#endif /* STM32F10X_CL */
/***************** Bit definition for RCC_APB2RSTR register *****************/
#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */
#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */
#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */
#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
#ifndef STM32F10X_LD
#define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */
#endif /* STM32F10X_HD */
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
#endif
#ifdef STM32F10X_HD
#define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */
#define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */
#define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
#define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
#endif /* STM32F10X_HD */
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
#endif
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
#endif
#ifdef STM32F10X_XL
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */
#endif /* STM32F10X_XL */
/***************** Bit definition for RCC_APB1RSTR register *****************/
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
@ -1674,22 +1942,26 @@ typedef struct
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
#endif
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
#ifndef STM32F10X_LD
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
#endif /* STM32F10X_HD */
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
@ -1699,24 +1971,51 @@ typedef struct
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
#endif
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
#endif
#ifdef STM32F10X_CL
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
#endif /* STM32F10X_CL */
#ifdef STM32F10X_XL
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
#endif /* STM32F10X_XL */
/****************** Bit definition for RCC_AHBENR register ******************/
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
#endif
#ifdef STM32F10X_HD
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
#endif /* STM32F10X_HD */
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
#endif
#ifdef STM32F10X_CL
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
@ -1726,27 +2025,48 @@ typedef struct
#endif /* STM32F10X_CL */
/****************** Bit definition for RCC_APB2ENR register *****************/
#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
#ifndef STM32F10X_LD
#define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
#endif /* STM32F10X_HD */
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
#endif
#ifdef STM32F10X_HD
#define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
#define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
#define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
#define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
#endif /* STM32F10X_HD */
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
#endif
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
#endif
#ifdef STM32F10X_XL
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */
#endif
/***************** Bit definition for RCC_APB1ENR register ******************/
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
@ -1754,16 +2074,20 @@ typedef struct
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
#endif
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
#ifndef STM32F10X_LD
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
#endif /* STM32F10X_HD */
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
@ -1779,10 +2103,33 @@ typedef struct
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
#endif
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
#endif
#ifdef STM32F10X_HD_VL
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
#endif /* STM32F10X_HD_VL */
#ifdef STM32F10X_CL
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
#endif /* STM32F10X_CL */
#ifdef STM32F10X_XL
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
#endif /* STM32F10X_XL */
/******************* Bit definition for RCC_BDCR register *******************/
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
@ -1907,6 +2254,33 @@ typedef struct
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
#endif /* STM32F10X_CL */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/******************* Bit definition for RCC_CFGR2 register ******************/
/*!< PREDIV1 configuration */
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
#endif
/******************************************************************************/
/* */
/* General Purpose and Alternate Function I/O */
@ -2460,6 +2834,34 @@ typedef struct
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/****************** Bit definition for AFIO_MAPR2 register ******************/
#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
#endif
#ifdef STM32F10X_HD_VL
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */
#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */
#endif
#ifdef STM32F10X_XL
/****************** Bit definition for AFIO_MAPR2 register ******************/
#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */
#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */
#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
#endif
/******************************************************************************/
/* */
/* SystemTick */
@ -3712,6 +4114,56 @@ typedef struct
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
/* CEC */
/* */
/******************************************************************************/
/******************** Bit definition for CEC_CFGR register ******************/
#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
/******************** Bit definition for CEC_OAR register ******************/
#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
/******************** Bit definition for CEC_PRES register ******************/
#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
/******************** Bit definition for CEC_ESR register ******************/
#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */
/******************** Bit definition for CEC_CSR register ******************/
#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
/******************** Bit definition for CEC_TXD register ******************/
#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
/******************** Bit definition for CEC_RXD register ******************/
#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
/******************************************************************************/
/* */
/* TIM */
@ -3938,6 +4390,7 @@ typedef struct
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
@ -4131,6 +4584,7 @@ typedef struct
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BCR2 register *******************/
@ -4153,6 +4607,7 @@ typedef struct
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BCR3 register *******************/
@ -4175,6 +4630,7 @@ typedef struct
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BCR4 register *******************/
@ -4197,6 +4653,7 @@ typedef struct
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BTR1 register ******************/
@ -7202,6 +7659,7 @@ typedef struct
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
@ -7230,6 +7688,7 @@ typedef struct
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
@ -7295,6 +7754,15 @@ typedef struct
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */
/******************************************************************************/
/* */
@ -7347,7 +7815,7 @@ typedef struct
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
#define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */
#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
@ -7848,4 +8316,4 @@ typedef struct
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

15
flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/system_stm32f10x.h Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
*
@ -14,7 +14,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
******************************************************************************
*/
@ -49,11 +49,7 @@
* @{
*/
extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
extern const uint32_t SystemFrequency_SysClk; /*!< System clock */
extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */
extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */
extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
@ -80,6 +76,7 @@ extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high)
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
@ -97,4 +94,4 @@ extern void SystemInit(void);
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

12
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -158,7 +158,7 @@ typedef struct
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @}
@ -193,7 +193,7 @@ typedef struct
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(const NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
@ -216,4 +216,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

11
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_adc.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -189,6 +189,9 @@ typedef struct
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
@ -476,4 +479,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_bkp.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the BKP firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -191,4 +191,4 @@ void BKP_ClearITPendingBit(void);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

106
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_can.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -427,41 +427,88 @@ typedef struct
/** @defgroup CAN_flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\
((FLAG) == CAN_FLAG_BOF))
/* Receive Flags */
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
((FLAG) == CAN_FLAG_SLAK ))
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
/**
* @}
*/
/** @defgroup CAN_interrupts
* @{
*/
#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */
#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */
#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */
#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
/* Flags named as Interrupts : kept only for FW compatibility */
#define CAN_IT_RQCP0 CAN_IT_TME
#define CAN_IT_RQCP1 CAN_IT_TME
#define CAN_IT_RQCP2 CAN_IT_TME
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
@ -469,12 +516,13 @@ typedef struct
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\
((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
@ -532,4 +580,4 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

209
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h Executable file
View File

@ -0,0 +1,209 @@
/**
******************************************************************************
* @file stm32f10x_cec.h
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the CEC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CEC_H
#define __STM32F10x_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup CEC
* @{
*/
/** @defgroup CEC_Exported_Types
* @{
*/
/**
* @brief CEC Init structure definition
*/
typedef struct
{
uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
This parameter can be a value of @ref CEC_BitTiming_Mode */
uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
This parameter can be a value of @ref CEC_BitPeriod_Mode */
}CEC_InitTypeDef;
/**
* @}
*/
/** @defgroup CEC_Exported_Constants
* @{
*/
/** @defgroup CEC_BitTiming_Mode
* @{
*/
#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
((MODE) == CEC_BitTimingErrFreeMode))
/**
* @}
*/
/** @defgroup CEC_BitPeriod_Mode
* @{
*/
#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
((MODE) == CEC_BitPeriodFlexibleMode))
/**
* @}
*/
/** @defgroup CEC_interrupts_definition
* @{
*/
#define CEC_IT_TERR CEC_CSR_TERR
#define CEC_IT_TBTRF CEC_CSR_TBTRF
#define CEC_IT_RERR CEC_CSR_RERR
#define CEC_IT_RBTF CEC_CSR_RBTF
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
/**
* @}
*/
/** @defgroup CEC_Own_Addres
* @{
*/
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
/**
* @}
*/
/** @defgroup CEC_Prescaler
* @{
*/
#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
/**
* @}
*/
/** @defgroup CEC_flags_definition
* @{
*/
/**
* @brief ESR register flags
*/
#define CEC_FLAG_BTE ((uint32_t)0x10010000)
#define CEC_FLAG_BPE ((uint32_t)0x10020000)
#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
#define CEC_FLAG_SBE ((uint32_t)0x10080000)
#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
#define CEC_FLAG_LINE ((uint32_t)0x10200000)
#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
/**
* @brief CSR register flags
*/
#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
#define CEC_FLAG_TERR ((uint32_t)0x00000004)
#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
#define CEC_FLAG_REOM ((uint32_t)0x00000020)
#define CEC_FLAG_RERR ((uint32_t)0x00000040)
#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
/**
* @}
*/
/**
* @}
*/
/** @defgroup CEC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Exported_Functions
* @{
*/
void CEC_DeInit(void);
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
void CEC_Cmd(FunctionalState NewState);
void CEC_ITConfig(FunctionalState NewState);
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
void CEC_SetPrescaler(uint16_t CEC_Prescaler);
void CEC_SendDataByte(uint8_t Data);
uint8_t CEC_ReceiveDataByte(void);
void CEC_StartOfMessage(void);
void CEC_EndOfMessageCmd(FunctionalState NewState);
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
void CEC_ClearFlag(uint32_t CEC_FLAG);
ITStatus CEC_GetITStatus(uint8_t CEC_IT);
void CEC_ClearITPendingBit(uint16_t CEC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_CEC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_crc.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -90,4 +90,4 @@ uint8_t CRC_GetIDRegister(void);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

44
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_dac.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -81,9 +81,11 @@ typedef struct
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in High-density devices*/
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in Connectivity line devices */
only in Connectivity line, Medium-density and Low-density Value Line devices */
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
only in Medium-density and Low-density Value Line devices*/
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
@ -232,6 +234,29 @@ typedef struct
/**
* @}
*/
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/** @defgroup DAC_interrupts_definition
* @{
*/
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
/**
* @}
*/
/** @defgroup DAC_flags_definition
* @{
*/
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
/**
* @}
*/
#endif
/**
* @}
@ -253,6 +278,9 @@ void DAC_DeInit(void);
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
#endif
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
@ -261,6 +289,12 @@ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
#endif
#ifdef __cplusplus
}
@ -279,4 +313,4 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

21
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_dbgmcu.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the DBGMCU
* firmware library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -67,8 +67,17 @@
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
@ -106,4 +115,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

11
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_dma.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -407,10 +407,11 @@ typedef struct
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, const DMA_InitTypeDef* DMA_InitStruct);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
void DMA_ClearFlag(uint32_t DMA_FLAG);
@ -434,4 +435,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

16
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_exti.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -118,11 +118,10 @@ typedef struct
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
@ -134,6 +133,7 @@ typedef struct
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
/**
* @}
*/
@ -180,4 +180,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

159
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_flash.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -142,76 +142,77 @@ typedef enum
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 Medium-density and Connectivity line devices:
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
@ -251,17 +252,44 @@ typedef enum
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
#ifdef STM32F10X_XL
/**
* @}
*/
/** @defgroup FLASH_Boot
* @{
*/
#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank1(Default) */
#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2 or Bank 1,
depending on the activation of the bank */
#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
#endif
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#ifdef STM32F10X_XL
#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
#else
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
#endif
/**
* @}
@ -270,6 +298,16 @@ typedef enum
/** @defgroup FLASH_Flags
* @{
*/
#ifdef STM32F10X_XL
#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
@ -277,10 +315,33 @@ typedef enum
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR)|| \
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
#else
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
#endif
/**
* @}
@ -302,6 +363,7 @@ typedef enum
* @{
*/
/*------------ Functions used for all STM32F10x devices -----*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
@ -320,12 +382,29 @@ uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
void FLASH_ClearFlag(uint16_t FLASH_FLAG);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
/*------------ New function used for all STM32F10x devices -----*/
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseAllBank1Pages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
#ifdef STM32F10X_XL
/*---- New Functions used only with STM32F10x_XL density devices -----*/
void FLASH_UnlockBank2(void);
void FLASH_LockBank2(void);
FLASH_Status FLASH_EraseAllBank2Pages(void);
FLASH_Status FLASH_GetBank2Status(void);
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
#endif
#ifdef __cplusplus
}
#endif
@ -343,4 +422,4 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

24
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_fsmc.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -107,6 +107,10 @@ typedef struct
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
@ -338,7 +342,19 @@ typedef struct
/**
* @}
*/
/** @defgroup FSMC_AsynchronousWait
* @{
*/
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
((STATE) == FSMC_AsynchronousWait_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal_Polarity
* @{
*/
@ -713,4 +729,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

45
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_gpio.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -195,11 +195,29 @@ typedef enum
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
to TIM2 Internal Trigger 1 for calibration
(only for Connectivity line devices) */
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
only for High density Value line devices) */
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
@ -215,7 +233,14 @@ typedef enum
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS))
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
/**
* @}
@ -295,8 +320,8 @@ typedef enum
/** @defgroup Ethernet_Media_Interface
* @{
*/
#define GPIO_ETH_MediaInterface_MII ((uint32_t)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
@ -322,7 +347,7 @@ typedef enum
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, const GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
@ -356,4 +381,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

320
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_i2c.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -290,77 +290,176 @@ typedef struct
* @{
*/
/*========================================
I2C Master Events (Events grouped in order of communication)
==========================================*/
/**
* @brief EV1
* @brief Communication start
*
* After sending the START condition (I2C_GenerateSTART() function) the master
* has to wait for this event. It means that the Start condition has been correctly
* released on the I2C bus (the bus is free, no other devices is communicating).
*
*/
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/**
* @brief EV2
*/
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/**
* @brief EV3
*/
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
/**
* @brief EV4
*/
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/**
* @brief EV5
*/
/* --EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/**
* @brief EV6
* @brief Address Acknowledge
*
* After checking on EV5 (start condition correctly released on the bus), the
* master sends the address of the slave(s) with which it will communicate
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will
* be set:
*
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set.
*
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set
*
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
* function). Then master should wait on EV9. It means that the 10-bit addressing
* header has been correctly sent on the bus. Then master should send the second part of
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
* should wait for event EV6.
*
*/
/* --EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/**
* @brief EV7
*/
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/**
* @brief EV8
*/
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/**
* @brief EV8_2
*/
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/**
* @brief EV9
*/
/* --EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/**
* @brief EV3_2
* @brief Communication events
*
* If a communication is established (START condition generated and slave address
* acknowledged) then the master has to check on one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
* the data received from the slave (I2C_ReceiveData() function).
*
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
* function) then to wait on event EV8 or EV8_2.
* These two events are similar:
* - EV8 means that the data has been written in the data register and is
* being shifted out.
* - EV8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EV8 is sufficient for the application.
* Using EV8_2 leads to a slower communication but ensure more reliable test.
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
* (before Stop condition generation).
*
* @note In case the user software does not guarantee that this event EV7 is
* managed before the current byte end of transfer, then user may check on EV7
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Master RECEIVER mode -----------------------------*/
/* --EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master TRANSMITTER mode --------------------------*/
/* --EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* --EV8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/*========================================
I2C Slave Events (Events grouped in order of communication)
==========================================*/
/**
* @brief Communication start events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a Start condition on the bus (generated by master
* device) followed by the peripheral address. The peripheral generates an ACK
* condition on the bus (if the acknowledge feature is enabled through function
* I2C_AcknowledgeConfig()) and the events listed above are set :
*
* 1) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* 2) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* 3) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* --EV1 (all the events below are variants of EV1) */
/* 1) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* 2) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* 3) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/**
* @brief Communication events
*
* Wait on one of these events when EV1 has already been checked and:
*
* - Slave RECEIVER mode:
* - EV2: When the application is expecting a data byte to be received.
* - EV4: When the application is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EV3: When a byte has been transmitted by the slave and the application is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
* used when the user software doesn't guarantee the EV3 is managed before the
* current byte end of tranfer.
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
* shall end (before sending the STOP condition). In this case slave has to stop sending
* data bytes and expect a Stop condition on the bus.
*
* @note In case the user software does not guarantee that the event EV2 is
* managed before the current byte end of transfer, then user may check on EV2
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Slave RECEIVER mode --------------------------*/
/* --EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* --EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave TRANSMITTER mode -----------------------*/
/* --EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/* --EV3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
/*=========================== End of Events Description ==========================================*/
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
@ -420,7 +519,7 @@ typedef struct
*/
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, const I2C_InitTypeDef* I2C_InitStruct);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
@ -445,9 +544,108 @@ uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/**
* @brief
****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* depending on the application requirements and constraints:
*
*
* 1) Basic state monitoring:
* Using I2C_CheckEvent() function:
* It compares the status registers (SR1 and SR2) content to a given event
* (can be the combination of one or more flags).
* It returns SUCCESS if the current status includes the given flags
* and returns ERROR if one or more flags are missing in the current status.
* - When to use:
* - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (RM0008).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs (ie. error flags are set besides to the monitored flags),
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* hold or corrupted real state.
* In this case, it is advised to use error interrupts to monitor the error
* events and handle them in the interrupt IRQ handler.
*
* @note
* For error management, it is advised to use the following functions:
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
* - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
* in order to determine which error occured.
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
* and/or I2C_GenerateStop() in order to clear the error flag and source,
* and return to correct communication status.
*
*
* 2) Advanced state monitoring:
* Using the function I2C_GetLastEvent() which returns the image of both status
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
* by 16 bits and concatenated to Status Register 1).
* - When to use:
* - This function is suitable for the same applications above but it allows to
* overcome the limitations of I2C_GetFlagStatus() function (see below).
* The returned value could be compared to events already defined in the
* library (stm32f10x_i2c.h) or to custom values defined by user.
* - This function is suitable when multiple flags are monitored at the same time.
* - At the opposite of I2C_CheckEvent() function, this function allows user to
* choose when an event is accepted (when all events flags are set and no
* other flags are set or just when the needed flags are set like
* I2C_CheckEvent() function).
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* 3) Flag-based state monitoring:
* Using the function I2C_GetFlagStatus() which simply returns the status of
* one single flag (ie. I2C_FLAG_RXNE ...).
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed (most I2C events
* are monitored through multiple flags).
* - Limitations:
* - When calling this function, the Status register is accessed. Some flags are
* cleared when the status register is accessed. So checking the status
* of one Flag, may clear other ones.
* - Function may need to be called twice or more in order to monitor one
* single event.
*
*/
/**
*
* 1) Basic state monitoring
*******************************************************************************
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/**
*
* 2) Advanced state monitoring
*******************************************************************************
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/**
*
* 3) Flag-based state monitoring
*******************************************************************************
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
/**
*
*******************************************************************************
*/
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
@ -469,4 +667,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_iwdg.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -136,4 +136,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_pwr.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -152,4 +152,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

54
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_rcc.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the RCC firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -79,7 +79,7 @@ typedef struct
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#ifndef STM32F10X_CL
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
@ -87,7 +87,7 @@ typedef struct
((SOURCE) == RCC_PLLSource_HSE_Div2))
#else
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_PREDIV1))
#endif /* STM32F10X_CL */
@ -141,10 +141,10 @@ typedef struct
* @}
*/
#ifdef STM32F10X_CL
/** @defgroup PREDIV1_division_factor
* @{
*/
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
@ -170,6 +170,7 @@ typedef struct
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
#endif
/**
* @}
*/
@ -178,17 +179,24 @@ typedef struct
/** @defgroup PREDIV1_clock_source
* @{
*/
/* PREDIV1 clock source (only for STM32 connectivity line devices) */
#ifdef STM32F10X_CL
/* PREDIV1 clock source (for STM32 connectivity line devices) */
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
((SOURCE) == RCC_PREDIV1_Source_PLL2))
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/* PREDIV1 clock source (for STM32 Value line devices) */
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
#endif
/**
* @}
*/
#ifdef STM32F10X_CL
/** @defgroup PREDIV2_division_factor
* @{
*/
@ -368,6 +376,9 @@ typedef struct
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
/**
* @}
*/
#else
/** @defgroup USB_OTG_FS_clock_source
* @{
@ -377,10 +388,11 @@ typedef struct
#define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
#endif /* STM32F10X_CL */
/**
* @}
*/
#endif /* STM32F10X_CL */
#ifdef STM32F10X_CL
/** @defgroup I2S2_clock_source
@ -496,8 +508,14 @@ typedef struct
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
@ -512,6 +530,9 @@ typedef struct
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
@ -523,11 +544,13 @@ typedef struct
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00))
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
@ -628,8 +651,11 @@ void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
#ifdef STM32F10X_CL
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
#endif
#ifdef STM32F10X_CL
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
void RCC_PLL2Cmd(FunctionalState NewState);
@ -697,4 +723,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_rtc.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -131,4 +131,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

12
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_sdio.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -455,8 +455,8 @@ typedef struct
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/**
@ -527,4 +527,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

50
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_spi.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -49,32 +49,32 @@
typedef struct
{
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be any combination of @ref SPI_data_direction */
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
This parameter can be any combination of @ref SPI_mode */
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
This parameter can be any combination of @ref SPI_data_size */
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be any combination of @ref SPI_Clock_Polarity */
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be any combination of @ref SPI_Clock_Phase */
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be any combination of @ref SPI_Slave_Select_management */
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be any combination of @ref SPI_BaudRate_Prescaler.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be any combination of @ref SPI_MSB_LSB_transmission */
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
@ -87,22 +87,22 @@ typedef struct
{
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
This parameter can be any combination of @ref I2S_Mode */
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be any combination of @ref I2S_Standard */
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be any combination of @ref I2S_Data_Format */
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be any combination of @ref I2S_MCLK_Output */
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be any combination of @ref I2S_Audio_Frequency */
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be any combination of @ref I2S_Clock_Polarity */
This parameter can be a value of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
/**
@ -298,6 +298,7 @@ typedef struct
* @{
*/
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
@ -307,14 +308,9 @@ typedef struct
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \
((FREQ) == I2S_AudioFreq_48k) || \
((FREQ) == I2S_AudioFreq_44k) || \
((FREQ) == I2S_AudioFreq_32k) || \
((FREQ) == I2S_AudioFreq_22k) || \
((FREQ) == I2S_AudioFreq_16k) || \
((FREQ) == I2S_AudioFreq_11k) || \
((FREQ) == I2S_AudioFreq_8k) || \
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
((FREQ) <= I2S_AudioFreq_192k)) || \
((FREQ) == I2S_AudioFreq_Default))
/**
* @}
@ -447,7 +443,7 @@ typedef struct
*/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, const SPI_InitTypeDef* SPI_InitStruct);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
@ -487,4 +483,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

115
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_tim.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -172,17 +172,110 @@ typedef struct
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8))
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10)|| \
((PERIPH) == TIM11)|| \
((PERIPH) == TIM12)|| \
((PERIPH) == TIM13)|| \
((PERIPH) == TIM14)|| \
((PERIPH) == TIM15)|| \
((PERIPH) == TIM16)|| \
((PERIPH) == TIM17))
#define IS_TIM_18_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM8))
/* LIST1: TIM 1 and 8 */
#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM8))
#define IS_TIM_123458_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
/* LIST2: TIM 1, 8, 15 16 and 17 */
#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM15)|| \
((PERIPH) == TIM16)|| \
((PERIPH) == TIM17))
/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM8))
/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM15)|| \
((PERIPH) == TIM16)|| \
((PERIPH) == TIM17))
/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM15))
/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM8))
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM12)|| \
((PERIPH) == TIM15))
/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM12)|| \
((PERIPH) == TIM15))
/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10)|| \
((PERIPH) == TIM11)|| \
((PERIPH) == TIM12)|| \
((PERIPH) == TIM13)|| \
((PERIPH) == TIM14)|| \
((PERIPH) == TIM15)|| \
((PERIPH) == TIM16)|| \
((PERIPH) == TIM17))
/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM15)|| \
((PERIPH) == TIM16)|| \
((PERIPH) == TIM17))
/**
* @}
*/
@ -458,8 +551,12 @@ typedef struct
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
((POLARITY) == TIM_ICPolarity_Falling))
#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
((POLARITY) == TIM_ICPolarity_Falling)|| \
((POLARITY) == TIM_ICPolarity_BothEdge))
/**
* @}
*/
@ -1037,4 +1134,4 @@ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

14
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_usart.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -51,7 +51,7 @@ typedef struct
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
@ -362,7 +362,7 @@ typedef struct
*/
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, const USART_InitTypeDef* USART_InitStruct);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
@ -382,6 +382,8 @@ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
@ -406,4 +408,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_wwdg.h
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -111,4 +111,4 @@ void WWDG_ClearFlag(void);
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

10
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
******************************************************************************
@ -16,7 +16,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -108,7 +108,7 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(const NVIC_InitTypeDef* NVIC_InitStruct)
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
@ -220,4 +220,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_adc.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the ADC firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -1303,4 +1303,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

24
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_bkp.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the BKP firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -75,12 +75,8 @@
/* ---------------------- BKP registers bit mask ------------------------ */
/* RTCCR register bit mask */
#define RTCCR_CAL_Mask ((uint16_t)0xFF80)
#define RTCCR_Mask ((uint16_t)0xFC7F)
/* CSR register bit mask */
#define CSR_CTE_Set ((uint16_t)0x0001)
#define CSR_CTI_Set ((uint16_t)0x0002)
#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
#define RTCCR_MASK ((uint16_t)0xFC7F)
/**
* @}
@ -187,7 +183,7 @@ void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
tmpreg = BKP->RTCCR;
/* Clear CCO, ASOE and ASOS bits */
tmpreg &= RTCCR_Mask;
tmpreg &= RTCCR_MASK;
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
tmpreg |= BKP_RTCOutputSource;
@ -208,7 +204,7 @@ void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
tmpreg = BKP->RTCCR;
/* Clear CAL[6:0] bits */
tmpreg &= RTCCR_CAL_Mask;
tmpreg &= RTCCR_CAL_MASK;
/* Set CAL[6:0] bits according to CalibrationValue value */
tmpreg |= CalibrationValue;
/* Store the new value */
@ -272,7 +268,7 @@ FlagStatus BKP_GetFlagStatus(void)
void BKP_ClearFlag(void)
{
/* Set CTE bit to clear Tamper Pin Event flag */
BKP->CSR |= CSR_CTE_Set;
BKP->CSR |= BKP_CSR_CTE;
}
/**
@ -293,7 +289,7 @@ ITStatus BKP_GetITStatus(void)
void BKP_ClearITPendingBit(void)
{
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
BKP->CSR |= CSR_CTI_Set;
BKP->CSR |= BKP_CSR_CTI;
}
/**
@ -308,4 +304,4 @@ void BKP_ClearITPendingBit(void)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

582
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_can.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the CAN firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -44,51 +44,9 @@
*/
/* CAN Master Control Register bits */
#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */
#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */
#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */
#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */
#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */
#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */
#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */
#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */
#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */
#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
/* CAN Master Status Register bits */
#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */
#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */
#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */
/* CAN Transmit Status Register bits */
#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */
#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */
#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */
#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */
#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */
#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */
#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */
#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */
#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */
#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */
#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */
#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */
/* CAN Receive FIFO 0 Register bits */
#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */
#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */
#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */
/* CAN Receive FIFO 1 Register bits */
#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */
#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */
#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */
/* CAN Error Status Register bits */
#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */
#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */
#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */
/* CAN Mailbox Transmit Request */
#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
@ -96,10 +54,23 @@
#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
/* Time out for INAK bit */
#define INAK_TimeOut ((uint32_t)0x0000FFFF)
#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
/* Time out for SLAK bit */
#define SLAK_TimeOut ((uint32_t)0x0000FFFF)
#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
/* Flags in TSR register */
#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
/* Flags in RF1R register */
#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
/* Flags in RF0R register */
#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
/* Flags in MSR register */
#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
/* Flags in ESR register */
#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
/**
* @}
@ -189,19 +160,19 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
/* exit from sleep mode */
CANx->MCR &= ~MCR_SLEEP;
CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
/* Request initialisation */
CANx->MCR |= MCR_INRQ ;
CANx->MCR |= CAN_MCR_INRQ ;
/* Wait the acknowledge */
while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut))
while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
{
wait_ack++;
}
/* ...and check acknowledged */
if ((CANx->MSR & MSR_INAK) != MSR_INAK)
if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
InitStatus = CANINITFAILED;
}
@ -210,61 +181,61 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
/* Set the time triggered communication mode */
if (CAN_InitStruct->CAN_TTCM == ENABLE)
{
CANx->MCR |= MCR_TTCM;
CANx->MCR |= CAN_MCR_TTCM;
}
else
{
CANx->MCR &= ~MCR_TTCM;
CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
}
/* Set the automatic bus-off management */
if (CAN_InitStruct->CAN_ABOM == ENABLE)
{
CANx->MCR |= MCR_ABOM;
CANx->MCR |= CAN_MCR_ABOM;
}
else
{
CANx->MCR &= ~MCR_ABOM;
CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
}
/* Set the automatic wake-up mode */
if (CAN_InitStruct->CAN_AWUM == ENABLE)
{
CANx->MCR |= MCR_AWUM;
CANx->MCR |= CAN_MCR_AWUM;
}
else
{
CANx->MCR &= ~MCR_AWUM;
CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
}
/* Set the no automatic retransmission */
if (CAN_InitStruct->CAN_NART == ENABLE)
{
CANx->MCR |= MCR_NART;
CANx->MCR |= CAN_MCR_NART;
}
else
{
CANx->MCR &= ~MCR_NART;
CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
}
/* Set the receive FIFO locked mode */
if (CAN_InitStruct->CAN_RFLM == ENABLE)
{
CANx->MCR |= MCR_RFLM;
CANx->MCR |= CAN_MCR_RFLM;
}
else
{
CANx->MCR &= ~MCR_RFLM;
CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
}
/* Set the transmit FIFO priority */
if (CAN_InitStruct->CAN_TXFP == ENABLE)
{
CANx->MCR |= MCR_TXFP;
CANx->MCR |= CAN_MCR_TXFP;
}
else
{
CANx->MCR &= ~MCR_TXFP;
CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
}
/* Set the bit timing register */
@ -273,18 +244,18 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
/* Request leave initialisation */
CANx->MCR &= ~MCR_INRQ;
CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
/* Wait the acknowledge */
wait_ack = 0x00;
while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut))
while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
{
wait_ack++;
}
/* ...and check acknowledged */
if ((CANx->MSR & MSR_INAK) == MSR_INAK)
if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
InitStatus = CANINITFAILED;
}
@ -444,14 +415,23 @@ void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
}
/**
* @brief Enables or disables the specified CAN interrupts.
* @brief Enables or disables the specified CANx interrupts.
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
* This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,
* CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,
* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
* CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or
* CAN_IT_SLK.
* This parameter can be:
* -CAN_IT_TME,
* -CAN_IT_FMP0,
* -CAN_IT_FF0,
* -CAN_IT_FOV0,
* -CAN_IT_FMP1,
* -CAN_IT_FF1,
* -CAN_IT_FOV1,
* -CAN_IT_EWG,
* -CAN_IT_EPV,
* -CAN_IT_LEC,
* -CAN_IT_ERR,
* -CAN_IT_WKU or
* -CAN_IT_SLK.
* @param NewState: new state of the CAN interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
@ -460,17 +440,17 @@ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
assert_param(IS_CAN_ITConfig(CAN_IT));
assert_param(IS_CAN_IT(CAN_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected CAN interrupt */
/* Enable the selected CANx interrupt */
CANx->IER |= CAN_IT;
}
else
{
/* Disable the selected CAN interrupt */
/* Disable the selected CANx interrupt */
CANx->IER &= ~CAN_IT;
}
}
@ -493,15 +473,15 @@ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
assert_param(IS_CAN_DLC(TxMessage->DLC));
/* Select one empty transmit mailbox */
if ((CANx->TSR&TSR_TME0) == TSR_TME0)
if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmit_mailbox = 0;
}
else if ((CANx->TSR&TSR_TME1) == TSR_TME1)
else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmit_mailbox = 1;
}
else if ((CANx->TSR&TSR_TME2) == TSR_TME2)
else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
{
transmit_mailbox = 2;
}
@ -562,17 +542,17 @@ uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
switch (TransmitMailbox)
{
case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2);
state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0);
state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26);
case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2);
state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26);
break;
case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6);
state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8);
state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27);
case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27);
break;
case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14);
state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16);
state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28);
case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28);
break;
default:
state = CANTXFAILED;
@ -610,11 +590,11 @@ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
/* abort transmission */
switch (Mailbox)
{
case (0): CANx->TSR |= TSR_ABRQ0;
case (0): CANx->TSR |= CAN_TSR_ABRQ0;
break;
case (1): CANx->TSR |= TSR_ABRQ1;
case (1): CANx->TSR |= CAN_TSR_ABRQ1;
break;
case (2): CANx->TSR |= TSR_ABRQ2;
case (2): CANx->TSR |= CAN_TSR_ABRQ2;
break;
default:
break;
@ -635,12 +615,12 @@ void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
{
CANx->RF0R = RF0R_RFOM0;
CANx->RF0R |= CAN_RF0R_RFOM0;
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
CANx->RF1R = RF1R_RFOM1;
CANx->RF1R |= CAN_RF1R_RFOM1;
}
}
@ -751,7 +731,7 @@ uint8_t CAN_Sleep(CAN_TypeDef* CANx)
assert_param(IS_CAN_ALL_PERIPH(CANx));
/* Request Sleep mode */
CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP);
CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
/* Sleep mode status */
if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
@ -770,14 +750,14 @@ uint8_t CAN_Sleep(CAN_TypeDef* CANx)
*/
uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
{
uint32_t wait_slak = SLAK_TimeOut ;
uint32_t wait_slak = SLAK_TIMEOUT;
uint8_t wakeupstatus = CANWAKEUPFAILED;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
/* Wake up request */
CANx->MCR &= ~MCR_SLEEP;
CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
/* Sleep mode status */
while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
@ -797,25 +777,102 @@ uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
* @brief Checks whether the specified CAN flag is set or not.
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_FLAG: specifies the flag to check.
* This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF.
* This parameter can be one of the following flags:
* - CAN_FLAG_EWG
* - CAN_FLAG_EPV
* - CAN_FLAG_BOF
* - CAN_FLAG_RQCP0
* - CAN_FLAG_RQCP1
* - CAN_FLAG_RQCP2
* - CAN_FLAG_FMP1
* - CAN_FLAG_FF1
* - CAN_FLAG_FOV1
* - CAN_FLAG_FMP0
* - CAN_FLAG_FF0
* - CAN_FLAG_FOV0
* - CAN_FLAG_WKU
* - CAN_FLAG_SLAK
* - CAN_FLAG_LEC
* @retval The new state of CAN_FLAG (SET or RESET).
*/
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
assert_param(IS_CAN_FLAG(CAN_FLAG));
/* Check the status of the specified CAN flag */
if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET)
{
/* CAN_FLAG is set */
bitstatus = SET;
assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
{
/* Check the status of the specified CAN flag */
if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
{
/* CAN_FLAG is set */
bitstatus = SET;
}
else
{
/* CAN_FLAG is reset */
bitstatus = RESET;
}
}
else
{
/* CAN_FLAG is reset */
bitstatus = RESET;
else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
{
/* Check the status of the specified CAN flag */
if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
{
/* CAN_FLAG is set */
bitstatus = SET;
}
else
{
/* CAN_FLAG is reset */
bitstatus = RESET;
}
}
else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
{
/* Check the status of the specified CAN flag */
if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
{
/* CAN_FLAG is set */
bitstatus = SET;
}
else
{
/* CAN_FLAG is reset */
bitstatus = RESET;
}
}
else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
{
/* Check the status of the specified CAN flag */
if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
{
/* CAN_FLAG is set */
bitstatus = SET;
}
else
{
/* CAN_FLAG is reset */
bitstatus = RESET;
}
}
else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
{
/* Check the status of the specified CAN flag */
if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
{
/* CAN_FLAG is set */
bitstatus = SET;
}
else
{
/* CAN_FLAG is reset */
bitstatus = RESET;
}
}
/* Return the CAN_FLAG status */
return bitstatus;
@ -825,131 +882,250 @@ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
* @brief Clears the CAN's pending flags.
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_FLAG: specifies the flag to clear.
* This parameter can be one of the following flags:
* - CAN_FLAG_RQCP0
* - CAN_FLAG_RQCP1
* - CAN_FLAG_RQCP2
* - CAN_FLAG_FF1
* - CAN_FLAG_FOV1
* - CAN_FLAG_FF0
* - CAN_FLAG_FOV0
* - CAN_FLAG_WKU
* - CAN_FLAG_SLAK
* - CAN_FLAG_LEC
* @retval None.
*/
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
{
uint32_t flagtmp=0;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
assert_param(IS_CAN_FLAG(CAN_FLAG));
/* Clear the selected CAN flags */
CANx->ESR &= ~CAN_FLAG;
assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
{
/* Clear the selected CAN flags */
CANx->ESR = (uint32_t)RESET;
}
else /* MSR or TSR or RF0R or RF1R */
{
flagtmp = CAN_FLAG & 0x000FFFFF;
if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
{
/* Receive Flags */
CANx->RF0R = (uint32_t)(flagtmp);
}
else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
{
/* Receive Flags */
CANx->RF1R = (uint32_t)(flagtmp);
}
else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
{
/* Transmit Flags */
CANx->TSR = (uint32_t)(flagtmp);
}
else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
{
/* Operating mode Flags */
CANx->MSR = (uint32_t)(flagtmp);
}
}
}
/**
* @brief Checks whether the specified CAN interrupt has occurred or not.
* @brief Checks whether the specified CANx interrupt has occurred or not.
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_IT: specifies the CAN interrupt source to check.
* This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,
* CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,
* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
* CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.
* @retval The new state of CAN_IT (SET or RESET).
* This parameter can be one of the following flags:
* - CAN_IT_TME
* - CAN_IT_FMP0
* - CAN_IT_FF0
* - CAN_IT_FOV0
* - CAN_IT_FMP1
* - CAN_IT_FF1
* - CAN_IT_FOV1
* - CAN_IT_WKU
* - CAN_IT_SLK
* - CAN_IT_EWG
* - CAN_IT_EPV
* - CAN_IT_BOF
* - CAN_IT_LEC
* - CAN_IT_ERR
* @retval The current state of CAN_IT (SET or RESET).
*/
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
{
ITStatus pendingbitstatus = RESET;
ITStatus itstatus = RESET;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
assert_param(IS_CAN_ITStatus(CAN_IT));
switch (CAN_IT)
{
case CAN_IT_RQCP0:
pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0);
break;
case CAN_IT_RQCP1:
pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1);
break;
case CAN_IT_RQCP2:
pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2);
break;
case CAN_IT_FF0:
pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0);
break;
case CAN_IT_FOV0:
pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0);
break;
case CAN_IT_FF1:
pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1);
break;
case CAN_IT_FOV1:
pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1);
break;
case CAN_IT_EWG:
pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF);
break;
case CAN_IT_EPV:
pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF);
break;
case CAN_IT_BOF:
pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF);
break;
case CAN_IT_SLK:
pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI);
break;
case CAN_IT_WKU:
pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI);
break;
default :
pendingbitstatus = RESET;
break;
assert_param(IS_CAN_IT(CAN_IT));
/* check the enable interrupt bit */
if((CANx->IER & CAN_IT) != RESET)
{
/* in case the Interrupt is enabled, .... */
switch (CAN_IT)
{
case CAN_IT_TME:
/* Check CAN_TSR_RQCPx bits */
itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
break;
case CAN_IT_FMP0:
/* Check CAN_RF0R_FMP0 bit */
itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
break;
case CAN_IT_FF0:
/* Check CAN_RF0R_FULL0 bit */
itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
break;
case CAN_IT_FOV0:
/* Check CAN_RF0R_FOVR0 bit */
itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
break;
case CAN_IT_FMP1:
/* Check CAN_RF1R_FMP1 bit */
itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
break;
case CAN_IT_FF1:
/* Check CAN_RF1R_FULL1 bit */
itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
break;
case CAN_IT_FOV1:
/* Check CAN_RF1R_FOVR1 bit */
itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
break;
case CAN_IT_WKU:
/* Check CAN_MSR_WKUI bit */
itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
break;
case CAN_IT_SLK:
/* Check CAN_MSR_SLAKI bit */
itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
break;
case CAN_IT_EWG:
/* Check CAN_ESR_EWGF bit */
itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
break;
case CAN_IT_EPV:
/* Check CAN_ESR_EPVF bit */
itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
break;
case CAN_IT_BOF:
/* Check CAN_ESR_BOFF bit */
itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
break;
case CAN_IT_LEC:
/* Check CAN_ESR_LEC bit */
itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
break;
case CAN_IT_ERR:
/* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */
itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC);
itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
break;
default :
/* in case of error, return RESET */
itstatus = RESET;
break;
}
}
else
{
/* in case the Interrupt is not enabled, return RESET */
itstatus = RESET;
}
/* Return the CAN_IT status */
return pendingbitstatus;
return itstatus;
}
/**
* @brief Clears the CAN’s interrupt pending bits.
* @brief Clears the CANx’s interrupt pending bits.
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_IT: specifies the interrupt pending bit to clear.
* - CAN_IT_TME
* - CAN_IT_FF0
* - CAN_IT_FOV0
* - CAN_IT_FF1
* - CAN_IT_FOV1
* - CAN_IT_WKU
* - CAN_IT_SLK
* - CAN_IT_EWG
* - CAN_IT_EPV
* - CAN_IT_BOF
* - CAN_IT_LEC
* - CAN_IT_ERR
* @retval None.
*/
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
{
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
assert_param(IS_CAN_ITStatus(CAN_IT));
assert_param(IS_CAN_CLEAR_IT(CAN_IT));
switch (CAN_IT)
{
case CAN_IT_RQCP0:
CANx->TSR = TSR_RQCP0; /* rc_w1*/
break;
case CAN_IT_RQCP1:
CANx->TSR = TSR_RQCP1; /* rc_w1*/
break;
case CAN_IT_RQCP2:
CANx->TSR = TSR_RQCP2; /* rc_w1*/
break;
case CAN_IT_FF0:
CANx->RF0R = RF0R_FULL0; /* rc_w1*/
break;
case CAN_IT_FOV0:
CANx->RF0R = RF0R_FOVR0; /* rc_w1*/
break;
case CAN_IT_FF1:
CANx->RF1R = RF1R_FULL1; /* rc_w1*/
break;
case CAN_IT_FOV1:
CANx->RF1R = RF1R_FOVR1; /* rc_w1*/
break;
case CAN_IT_EWG:
CANx->ESR &= ~ ESR_EWGF; /* rw */
break;
case CAN_IT_EPV:
CANx->ESR &= ~ ESR_EPVF; /* rw */
break;
case CAN_IT_BOF:
CANx->ESR &= ~ ESR_BOFF; /* rw */
break;
case CAN_IT_WKU:
CANx->MSR = MSR_WKUI; /* rc_w1*/
break;
case CAN_IT_SLK:
CANx->MSR = MSR_SLAKI; /* rc_w1*/
break;
default :
break;
}
case CAN_IT_TME:
/* Clear CAN_TSR_RQCPx (rc_w1)*/
CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
break;
case CAN_IT_FF0:
/* Clear CAN_RF0R_FULL0 (rc_w1)*/
CANx->RF0R = CAN_RF0R_FULL0;
break;
case CAN_IT_FOV0:
/* Clear CAN_RF0R_FOVR0 (rc_w1)*/
CANx->RF0R = CAN_RF0R_FOVR0;
break;
case CAN_IT_FF1:
/* Clear CAN_RF1R_FULL1 (rc_w1)*/
CANx->RF1R = CAN_RF1R_FULL1;
break;
case CAN_IT_FOV1:
/* Clear CAN_RF1R_FOVR1 (rc_w1)*/
CANx->RF1R = CAN_RF1R_FOVR1;
break;
case CAN_IT_WKU:
/* Clear CAN_MSR_WKUI (rc_w1)*/
CANx->MSR = CAN_MSR_WKUI;
break;
case CAN_IT_SLK:
/* Clear CAN_MSR_SLAKI (rc_w1)*/
CANx->MSR = CAN_MSR_SLAKI;
break;
case CAN_IT_EWG:
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
/* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
break;
case CAN_IT_EPV:
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
/* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
break;
case CAN_IT_BOF:
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
/* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
break;
case CAN_IT_LEC:
/* Clear LEC bits */
CANx->ESR = RESET;
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
break;
case CAN_IT_ERR:
/*Clear LEC bits */
CANx->ESR = RESET;
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
/* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/
break;
default :
break;
}
}
/**
@ -987,4 +1163,4 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

432
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c Executable file
View File

@ -0,0 +1,432 @@
/**
******************************************************************************
* @file stm32f10x_cec.c
* @author MCD Application Team
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the CEC firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_cec.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup CEC
* @brief CEC driver modules
* @{
*/
/** @defgroup CEC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_Defines
* @{
*/
/* ------------ CEC registers bit address in the alias region ----------- */
#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
/* --- CFGR Register ---*/
/* Alias word address of PE bit */
#define CFGR_OFFSET (CEC_OFFSET + 0x00)
#define PE_BitNumber 0x00
#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
/* Alias word address of IE bit */
#define IE_BitNumber 0x01
#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of TSOM bit */
#define CSR_OFFSET (CEC_OFFSET + 0x10)
#define TSOM_BitNumber 0x00
#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
/* Alias word address of TEOM bit */
#define TEOM_BitNumber 0x01
#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
/**
* @}
*/
/** @defgroup CEC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_Functions
* @{
*/
/**
* @brief Deinitializes the CEC peripheral registers to their default reset
* values.
* @param None
* @retval None
*/
void CEC_DeInit(void)
{
/* Enable CEC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
/* Release CEC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
}
/**
* @brief Initializes the CEC peripheral according to the specified
* parameters in the CEC_InitStruct.
* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
* contains the configuration information for the specified
* CEC peripheral.
* @retval None
*/
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
/*---------------------------- CEC CFGR Configuration -----------------*/
/* Get the CEC CFGR value */
tmpreg = CEC->CFGR;
/* Clear BTEM and BPEM bits */
tmpreg &= CFGR_CLEAR_Mask;
/* Configure CEC: Bit Timing Error and Bit Period Error */
tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
/* Write to CEC CFGR register*/
CEC->CFGR = tmpreg;
}
/**
* @brief Enables or disables the specified CEC peripheral.
* @param NewState: new state of the CEC peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CEC_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
if(NewState == DISABLE)
{
/* Wait until the PE bit is cleared by hardware (Idle Line detected) */
while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
{
}
}
}
/**
* @brief Enables or disables the CEC interrupt.
* @param NewState: new state of the CEC interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CEC_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
}
/**
* @brief Defines the Own Address of the CEC device.
* @param CEC_OwnAddress: The CEC own address
* @retval None
*/
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
{
/* Check the parameters */
assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
/* Set the CEC own address */
CEC->OAR = CEC_OwnAddress;
}
/**
* @brief Sets the CEC prescaler value.
* @param CEC_Prescaler: CEC prescaler new value
* @retval None
*/
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
{
/* Check the parameters */
assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
/* Set the Prescaler value*/
CEC->PRES = CEC_Prescaler;
}
/**
* @brief Transmits single data through the CEC peripheral.
* @param Data: the data to transmit.
* @retval None
*/
void CEC_SendDataByte(uint8_t Data)
{
/* Transmit Data */
CEC->TXD = Data ;
}
/**
* @brief Returns the most recent received data by the CEC peripheral.
* @param None
* @retval The received data.
*/
uint8_t CEC_ReceiveDataByte(void)
{
/* Receive Data */
return (uint8_t)(CEC->RXD);
}
/**
* @brief Starts a new message.
* @param None
* @retval None
*/
void CEC_StartOfMessage(void)
{
/* Starts of new message */
*(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
}
/**
* @brief Transmits message with or without an EOM bit.
* @param NewState: new state of the CEC Tx End Of Message.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CEC_EndOfMessageCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* The data byte will be transmitted with or without an EOM bit*/
*(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
}
/**
* @brief Gets the CEC flag status
* @param CEC_FLAG: specifies the CEC flag to check.
* This parameter can be one of the following values:
* @arg CEC_FLAG_BTE: Bit Timing Error
* @arg CEC_FLAG_BPE: Bit Period Error
* @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
* @arg CEC_FLAG_SBE: Start Bit Error
* @arg CEC_FLAG_ACKE: Block Acknowledge Error
* @arg CEC_FLAG_LINE: Line Error
* @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error
* @arg CEC_FLAG_TEOM: Tx End Of Message
* @arg CEC_FLAG_TERR: Tx Error
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
* @arg CEC_FLAG_RSOM: Rx Start Of Message
* @arg CEC_FLAG_REOM: Rx End Of Message
* @arg CEC_FLAG_RERR: Rx Error
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
* @retval The new state of CEC_FLAG (SET or RESET)
*/
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t cecreg = 0, cecbase = 0;
/* Check the parameters */
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
/* Get the CEC peripheral base address */
cecbase = (uint32_t)(CEC_BASE);
/* Read flag register index */
cecreg = CEC_FLAG >> 28;
/* Get bit[23:0] of the flag */
CEC_FLAG &= FLAG_Mask;
if(cecreg != 0)
{
/* Flag in CEC ESR Register */
CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
/* Get the CEC ESR register address */
cecbase += 0xC;
}
else
{
/* Get the CEC CSR register address */
cecbase += 0x10;
}
if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
{
/* CEC_FLAG is set */
bitstatus = SET;
}
else
{
/* CEC_FLAG is reset */
bitstatus = RESET;
}
/* Return the CEC_FLAG status */
return bitstatus;
}
/**
* @brief Clears the CEC's pending flags.
* @param CEC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg CEC_FLAG_TERR: Tx Error
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
* @arg CEC_FLAG_RSOM: Rx Start Of Message
* @arg CEC_FLAG_REOM: Rx End Of Message
* @arg CEC_FLAG_RERR: Rx Error
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
* @retval None
*/
void CEC_ClearFlag(uint32_t CEC_FLAG)
{
uint32_t tmp = 0x0;
/* Check the parameters */
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
tmp = CEC->CSR & 0x2;
/* Clear the selected CEC flags */
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
}
/**
* @brief Checks whether the specified CEC interrupt has occurred or not.
* @param CEC_IT: specifies the CEC interrupt source to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TERR: Tx Error
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
* @arg CEC_IT_RERR: Rx Error
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
* @retval The new state of CEC_IT (SET or RESET).
*/
ITStatus CEC_GetITStatus(uint8_t CEC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_CEC_GET_IT(CEC_IT));
/* Get the CEC IT enable bit status */
enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
/* Check the status of the specified CEC interrupt */
if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
{
/* CEC_IT is set */
bitstatus = SET;
}
else
{
/* CEC_IT is reset */
bitstatus = RESET;
}
/* Return the CEC_IT status */
return bitstatus;
}
/**
* @brief Clears the CEC's interrupt pending bits.
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg CEC_IT_TERR: Tx Error
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
* @arg CEC_IT_RERR: Rx Error
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
* @retval None
*/
void CEC_ClearITPendingBit(uint16_t CEC_IT)
{
uint32_t tmp = 0x0;
/* Check the parameters */
assert_param(IS_CEC_GET_IT(CEC_IT));
tmp = CEC->CSR & 0x2;
/* Clear the selected CEC interrupt pending bits */
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

14
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_crc.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -42,10 +42,6 @@
* @{
*/
/* CR register bit mask */
#define CR_RESET_Set ((uint32_t)0x00000001)
/**
* @}
*/
@ -86,7 +82,7 @@
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CR_RESET_Set;
CRC->CR = CRC_CR_RESET;
}
/**
@ -160,4 +156,4 @@ uint8_t CRC_GetIDRegister(void)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

205
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_dac.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the DAC firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -43,29 +43,20 @@
* @{
*/
/* DAC EN mask */
#define CR_EN_Set ((uint32_t)0x00000001)
/* DAC DMAEN mask */
#define CR_DMAEN_Set ((uint32_t)0x00001000)
/* CR register Mask */
#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)
/* DAC SWTRIG mask */
#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)
#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_Offset ((uint32_t)0x00000008)
#define DHR12R2_Offset ((uint32_t)0x00000014)
#define DHR12RD_Offset ((uint32_t)0x00000020)
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_Offset ((uint32_t)0x0000002C)
#define DOR_OFFSET ((uint32_t)0x0000002C)
/**
* @}
*/
@ -134,7 +125,7 @@ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave genration,
mask/amplitude for wave genration */
/* Set TSELx and TENx bits according to DAC_Trigger value */
@ -186,14 +177,47 @@ void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= CR_EN_Set << DAC_Channel;
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= ~(CR_EN_Set << DAC_Channel);
DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
}
}
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/**
* @brief Enables or disables the specified DAC interrupts.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @param NewState: new state of the specified DAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_DAC_IT(DAC_IT));
if (NewState != DISABLE)
{
/* Enable the selected DAC interrupts */
DAC->CR |= (DAC_IT << DAC_Channel);
}
else
{
/* Disable the selected DAC interrupts */
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
}
}
#endif
/**
* @brief Enables or disables the specified DAC channel DMA request.
@ -213,12 +237,12 @@ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= CR_DMAEN_Set << DAC_Channel;
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
}
}
@ -240,12 +264,12 @@ void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
}
}
@ -263,12 +287,12 @@ void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
}
}
@ -323,7 +347,7 @@ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_Offset + DAC_Align;
tmp += DHR12R1_OFFSET + DAC_Align;
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
@ -348,7 +372,7 @@ void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_Offset + DAC_Align;
tmp += DHR12R2_OFFSET + DAC_Align;
/* Set the DAC channel2 selected data holding register */
*(__IO uint32_t *)tmp = Data;
@ -388,7 +412,7 @@ void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
}
tmp = (uint32_t)DAC_BASE;
tmp += DHR12RD_Offset + DAC_Align;
tmp += DHR12RD_OFFSET + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
@ -410,12 +434,127 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
assert_param(IS_DAC_CHANNEL(DAC_Channel));
tmp = (uint32_t) DAC_BASE ;
tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2);
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/**
* @brief Checks whether the specified DAC flag is set or not.
* @param DAC_Channel: thee selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to check.
* This parameter can be only of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @retval The new state of DAC_FLAG (SET or RESET).
*/
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Check the status of the specified DAC flag */
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
{
/* DAC_FLAG is set */
bitstatus = SET;
}
else
{
/* DAC_FLAG is reset */
bitstatus = RESET;
}
/* Return the DAC_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DAC channelx's pending flags.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to clear.
* This parameter can be of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @retval None
*/
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Clear the selected DAC flags */
DAC->SR = (DAC_FLAG << DAC_Channel);
}
/**
* @brief Checks whether the specified DAC interrupt has occurred or not.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt source to check.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @retval The new state of DAC_IT (SET or RESET).
*/
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Get the DAC_IT enable bit status */
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
/* Check the status of the specified DAC interrupt */
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
{
/* DAC_IT is set */
bitstatus = SET;
}
else
{
/* DAC_IT is reset */
bitstatus = RESET;
}
/* Return the DAC_IT status */
return bitstatus;
}
/**
* @brief Clears the DAC channelx’s interrupt pending bits.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @retval None
*/
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Clear the selected DAC interrupt pending bits */
DAC->SR = (DAC_IT << DAC_Channel);
}
#endif
/**
* @}
*/
@ -428,4 +567,4 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

23
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_dbgmcu.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -42,7 +42,7 @@
* @{
*/
#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF)
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
* @}
*/
@ -92,7 +92,7 @@ uint32_t DBGMCU_GetREVID(void)
*/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
}
/**
@ -116,7 +116,16 @@ uint32_t DBGMCU_GetDEVID(void)
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -149,4 +158,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

64
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_dma.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the DMA firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -42,25 +42,22 @@
* @{
*/
/* DMA ENABLE mask */
#define CCR_ENABLE_Set ((uint32_t)0x00000001)
#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)
#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)
#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)
#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)
#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)
#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
/* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000000)
@ -111,8 +108,10 @@ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
@ -199,7 +198,7 @@ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
* contains the configuration information for the specified DMA Channel.
* @retval None
*/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, const DMA_InitTypeDef* DMA_InitStruct)
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
uint32_t tmpreg = 0;
@ -300,12 +299,12 @@ void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
if (NewState != DISABLE)
{
/* Enable the selected DMAy Channelx */
DMAy_Channelx->CCR |= CCR_ENABLE_Set;
DMAy_Channelx->CCR |= DMA_CCR1_EN;
}
else
{
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
}
}
@ -341,6 +340,25 @@ void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, Functiona
}
}
/**
* @brief Sets the number of data units in the current DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DataNumber: The number of data units in the current DMAy Channelx
* transfer.
* @note This function can only be used when the DMAy_Channelx is disabled.
* @retval None.
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DataNumber;
}
/**
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
@ -690,4 +708,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

12
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_exti.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the EXTI firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -42,7 +42,7 @@
* @{
*/
#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
/**
* @}
@ -155,7 +155,7 @@ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
@ -265,4 +265,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

929
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_flash.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the FLASH firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -70,16 +70,19 @@
#define WRP1_Mask ((uint32_t)0x0000FF00)
#define WRP2_Mask ((uint32_t)0x00FF0000)
#define WRP3_Mask ((uint32_t)0xFF000000)
#define OB_USER_BFB2 ((uint16_t)0x0008)
/* FLASH Keys */
#define RDP_Key ((uint16_t)0x00A5)
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
/* Delay definition */
#define EraseTimeout ((uint32_t)0x00000FFF)
#define ProgramTimeout ((uint32_t)0x0000000F)
/* FLASH BANK address */
#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
/* Delay definition */
#define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00002000)
/**
* @}
*/
@ -103,8 +106,7 @@
/** @defgroup FLASH_Private_FunctionPrototypes
* @{
*/
static void delay(void);
/**
* @}
*/
@ -113,8 +115,134 @@ static void delay(void);
* @{
*/
/**
@code
This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
including the latest STM32F10x_XL density devices.
STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
- bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
- bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
In version V3.3.0, some functions were updated and new ones were added to support
STM32F10x_XL devices. Thus some functions manages all devices, while other are
dedicated for XL devices only.
The table below presents the list of available functions depending on the used STM32F10x devices.
***************************************************
* Legacy functions used for all STM32F10x devices *
***************************************************
+----------------------------------------------------------------------------------------------------------------------------------+
| Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
| | devices | devices | |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_SetLatency | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_HalfCycleAccessCmd | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_PrefetchBufferCmd | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |
| | | | - For other devices: unlock Bank1 and it is equivalent |
| | | | to FLASH_UnlockBank1 function. |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |
| | | | - For other devices: lock Bank1 and it is equivalent |
| | | | to FLASH_LockBank1 function. |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |
| | | | - For other devices: erase a page in Bank1 |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
| | | | - For other devices: erase all pages in Bank1 |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_EraseOptionBytes | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_ProgramOptionByteData | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_EnableWriteProtection | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_ReadOutProtection | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_UserOptionByteConfig | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_GetUserOptionByte | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
| | | | - For other devices: enable Bank1's interrupts |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
| | | | - For other devices: return Bank1's flag status |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |
| | | | - For other devices: clear Bank1's flag |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |
| | | | equivalent to FLASH_GetBank1Status function |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |
| | | | equivalent to: FLASH_WaitForLastBank1Operation function |
+----------------------------------------------------------------------------------------------------------------------------------+
************************************************************************************************************************
* New functions used for all STM32F10x devices to manage Bank1: *
* - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
* - For other devices, these functions are optional (covered by functions listed above) *
************************************************************************************************************************
+----------------------------------------------------------------------------------------------------------------------------------+
| Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
| | devices | devices | |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |
+----------------------------------------------------------------------------------------------------------------------------------+
*****************************************************************************
* New Functions used only with STM32F10x_XL density devices to manage Bank2 *
*****************************************************************************
+----------------------------------------------------------------------------------------------------------------------------------+
| Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
| | devices | devices | |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |
|----------------------------------------------------------------------------------------------------------------------------------|
|FLASH_LockBank2 | Yes | No | - Lock Bank2 |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |
|----------------------------------------------------------------------------------------------------------------------------------|
| FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |
+----------------------------------------------------------------------------------------------------------------------------------+
@endcode
*/
/**
* @brief Sets the code latency value.
* @note This function can be used for all STM32F10x devices.
* @param FLASH_Latency: specifies the FLASH Latency value.
* This parameter can be one of the following values:
* @arg FLASH_Latency_0: FLASH Zero Latency cycle
@ -142,6 +270,7 @@ void FLASH_SetLatency(uint32_t FLASH_Latency)
/**
* @brief Enables or disables the Half cycle flash access.
* @note This function can be used for all STM32F10x devices.
* @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
* This parameter can be one of the following values:
* @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
@ -160,6 +289,7 @@ void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
/**
* @brief Enables or disables the Prefetch Buffer.
* @note This function can be used for all STM32F10x devices.
* @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
* This parameter can be one of the following values:
* @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
@ -178,29 +308,109 @@ void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
/**
* @brief Unlocks the FLASH Program Erase Controller.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
* - For all other devices it unlocks Bank1 and it is equivalent
* to FLASH_UnlockBank1 function..
* @param None
* @retval None
*/
void FLASH_Unlock(void)
{
/* Authorize the FPEC Access */
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
#ifdef STM32F10X_XL
/* Authorize the FPEC of Bank2 Access */
FLASH->KEYR2 = FLASH_KEY1;
FLASH->KEYR2 = FLASH_KEY2;
#endif /* STM32F10X_XL */
}
/**
* @brief Unlocks the FLASH Bank1 Program Erase Controller.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices this function unlocks Bank1.
* - For all other devices it unlocks Bank1 and it is
* equivalent to FLASH_Unlock function.
* @param None
* @retval None
*/
void FLASH_UnlockBank1(void)
{
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
#ifdef STM32F10X_XL
/**
* @brief Unlocks the FLASH Bank2 Program Erase Controller.
* @note This function can be used only for STM32F10X_XL density devices.
* @param None
* @retval None
*/
void FLASH_UnlockBank2(void)
{
/* Authorize the FPEC of Bank2 Access */
FLASH->KEYR2 = FLASH_KEY1;
FLASH->KEYR2 = FLASH_KEY2;
}
#endif /* STM32F10X_XL */
/**
* @brief Locks the FLASH Program Erase Controller.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
* - For all other devices it Locks Bank1 and it is equivalent
* to FLASH_LockBank1 function.
* @param None
* @retval None
*/
void FLASH_Lock(void)
{
/* Set the Lock Bit to lock the FPEC and the FCR */
/* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
FLASH->CR |= CR_LOCK_Set;
#ifdef STM32F10X_XL
/* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
FLASH->CR2 |= CR_LOCK_Set;
#endif /* STM32F10X_XL */
}
/**
* @brief Locks the FLASH Bank1 Program Erase Controller.
* @note this function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices this function Locks Bank1.
* - For all other devices it Locks Bank1 and it is equivalent
* to FLASH_Lock function.
* @param None
* @retval None
*/
void FLASH_LockBank1(void)
{
/* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
FLASH->CR |= CR_LOCK_Set;
}
#ifdef STM32F10X_XL
/**
* @brief Locks the FLASH Bank2 Program Erase Controller.
* @note This function can be used only for STM32F10X_XL density devices.
* @param None
* @retval None
*/
void FLASH_LockBank2(void)
{
/* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
FLASH->CR2 |= CR_LOCK_Set;
}
#endif /* STM32F10X_XL */
/**
* @brief Erases a specified FLASH page.
* @note This function can be used for all STM32F10x devices.
* @param Page_Address: The page address to be erased.
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
@ -210,6 +420,45 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Page_Address));
#ifdef STM32F10X_XL
if(Page_Address < FLASH_BANK1_END_ADDRESS)
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase the page */
FLASH->CR|= CR_PER_Set;
FLASH->AR = Page_Address;
FLASH->CR|= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
/* Disable the PER Bit */
FLASH->CR &= CR_PER_Reset;
}
}
else
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase the page */
FLASH->CR2|= CR_PER_Set;
FLASH->AR2 = Page_Address;
FLASH->CR2|= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(EraseTimeout);
/* Disable the PER Bit */
FLASH->CR2 &= CR_PER_Reset;
}
}
#else
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
@ -222,18 +471,19 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status != FLASH_TIMEOUT)
{
/* if the erase operation is completed, disable the PER Bit */
FLASH->CR &= CR_PER_Reset;
}
/* Disable the PER Bit */
FLASH->CR &= CR_PER_Reset;
}
#endif /* STM32F10X_XL */
/* Return the Erase Status */
return status;
}
/**
* @brief Erases all FLASH pages.
* @note This function can be used for all STM32F10x devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
@ -241,9 +491,38 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
FLASH_Status FLASH_EraseAllPages(void)
{
FLASH_Status status = FLASH_COMPLETE;
#ifdef STM32F10X_XL
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all pages */
FLASH->CR |= CR_MER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
/* Disable the MER Bit */
FLASH->CR &= CR_MER_Reset;
}
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all pages */
FLASH->CR2 |= CR_MER_Set;
FLASH->CR2 |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(EraseTimeout);
/* Disable the MER Bit */
FLASH->CR2 &= CR_MER_Reset;
}
#else
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all pages */
@ -252,30 +531,99 @@ FLASH_Status FLASH_EraseAllPages(void)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status != FLASH_TIMEOUT)
{
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= CR_MER_Reset;
}
}
/* Disable the MER Bit */
FLASH->CR &= CR_MER_Reset;
}
#endif /* STM32F10X_XL */
/* Return the Erase Status */
return status;
}
/**
* @brief Erases all Bank1 FLASH pages.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices this function erases all Bank1 pages.
* - For all other devices it erases all Bank1 pages and it is equivalent
* to FLASH_EraseAllPages function.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllBank1Pages(void)
{
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all pages */
FLASH->CR |= CR_MER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
/* Disable the MER Bit */
FLASH->CR &= CR_MER_Reset;
}
/* Return the Erase Status */
return status;
}
#ifdef STM32F10X_XL
/**
* @brief Erases all Bank2 FLASH pages.
* @note This function can be used only for STM32F10x_XL density devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllBank2Pages(void)
{
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all pages */
FLASH->CR2 |= CR_MER_Set;
FLASH->CR2 |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(EraseTimeout);
/* Disable the MER Bit */
FLASH->CR2 &= CR_MER_Reset;
}
/* Return the Erase Status */
return status;
}
#endif /* STM32F10X_XL */
/**
* @brief Erases the FLASH option bytes.
* @note This functions erases all option bytes and then deactivates the Read
* protection. If the user needs to keep the Read protection activated,
* he has to enable it after this function call (using
* FLASH_ReadOutProtection function)
* @note This functions erases all option bytes except the Read protection (RDP).
* @note This function can be used for all STM32F10x devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseOptionBytes(void)
{
uint16_t rdptmp = RDP_Key;
FLASH_Status status = FLASH_COMPLETE;
/* Get the actual read protection Option Byte value */
if(FLASH_GetReadOutProtectionStatus() != RESET)
{
rdptmp = 0x00;
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
@ -297,8 +645,8 @@ FLASH_Status FLASH_EraseOptionBytes(void)
/* Enable the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
/* Disable the Read protection */
OB->RDP= RDP_Key;
/* Restore the last read protection Option Byte value */
OB->RDP = (uint16_t)rdptmp;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
@ -323,6 +671,7 @@ FLASH_Status FLASH_EraseOptionBytes(void)
/**
* @brief Programs a word at a specified address.
* @note This function can be used for all STM32F10x devices.
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
@ -335,6 +684,129 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
#ifdef STM32F10X_XL
if(Address < FLASH_BANK1_END_ADDRESS - 2)
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new first
half word */
FLASH->CR |= CR_PG_Set;
*(__IO uint16_t*)Address = (uint16_t)Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new second
half word */
tmp = Address + 2;
*(__IO uint16_t*) tmp = Data >> 16;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
else
{
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
}
else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new first
half word */
FLASH->CR |= CR_PG_Set;
*(__IO uint16_t*)Address = (uint16_t)Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
else
{
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new second
half word */
FLASH->CR2 |= CR_PG_Set;
tmp = Address + 2;
*(__IO uint16_t*) tmp = Data >> 16;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR2 &= CR_PG_Reset;
}
else
{
/* Disable the PG Bit */
FLASH->CR2 &= CR_PG_Reset;
}
}
else
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new first
half word */
FLASH->CR2 |= CR_PG_Set;
*(__IO uint16_t*)Address = (uint16_t)Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new second
half word */
tmp = Address + 2;
*(__IO uint16_t*) tmp = Data >> 16;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR2 &= CR_PG_Reset;
}
else
{
/* Disable the PG Bit */
FLASH->CR2 &= CR_PG_Reset;
}
}
}
#else
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
@ -359,27 +831,24 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
else
{
if (status != FLASH_TIMEOUT)
{
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
}
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
#endif /* STM32F10X_XL */
/* Return the Program Status */
return status;
}
/**
* @brief Programs a half word at a specified address.
* @note This function can be used for all STM32F10x devices.
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
@ -390,6 +859,42 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
#ifdef STM32F10X_XL
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(Address < FLASH_BANK1_END_ADDRESS)
{
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new data */
FLASH->CR |= CR_PG_Set;
*(__IO uint16_t*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
else
{
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new data */
FLASH->CR2 |= CR_PG_Set;
*(__IO uint16_t*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR2 &= CR_PG_Reset;
}
}
#else
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
@ -401,18 +906,19 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
*(__IO uint16_t*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
/* if the program operation is completed, disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
#endif /* STM32F10X_XL */
/* Return the Program Status */
return status;
}
/**
* @brief Programs a half word at a specified Option Byte Data address.
* @note This function can be used for all STM32F10x devices.
* @param Address: specifies the address to be programmed.
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
* @param Data: specifies the data to be programmed.
@ -425,6 +931,7 @@ FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
/* Check the parameters */
assert_param(IS_OB_DATA_ADDRESS(Address));
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorize the small information block programming */
@ -441,13 +948,14 @@ FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
}
/* Return the Option Byte Data Program Status */
return status;
}
/**
* @brief Write protects the desired pages
* @note This function can be used for all STM32F10x devices.
* @param FLASH_Pages: specifies the address of the pages to be write protected.
* This parameter can be:
* @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
@ -457,6 +965,8 @@ FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
* @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
* @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
* @arg FLASH_WRProt_AllPages
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
@ -529,6 +1039,7 @@ FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
* @brief Enables or disables the read out protection.
* @note If the user has already programmed the other option bytes before calling
* this function, he must re-program them since this function erases all option bytes.
* @note This function can be used for all STM32F10x devices.
* @param Newstate: new state of the ReadOut Protection.
* This parameter can be: ENABLE or DISABLE.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
@ -582,11 +1093,12 @@ FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
}
}
/* Return the protection operation Status */
return status;
return status;
}
/**
* @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
* @note This function can be used for all STM32F10x devices.
* @param OB_IWDG: Selects the IWDG mode
* This parameter can be one of the following values:
* @arg OB_IWDG_SW: Software IWDG selected
@ -637,8 +1149,65 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint
return status;
}
#ifdef STM32F10X_XL
/**
* @brief Configures to boot from Bank1 or Bank2.
* @note This function can be used only for STM32F10x_XL density devices.
* @param FLASH_BOOT: select the FLASH Bank to boot from.
* This parameter can be one of the following values:
* @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
* position and this parameter is selected the device will boot from Bank1(Default).
* @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
* position and this parameter is selected the device will boot from Bank2 or Bank1,
* depending on the activation of the bank. The active banks are checked in
* the following order: Bank2, followed by Bank1.
* The active bank is recognized by the value programmed at the base address
* of the respective bank (corresponding to the initial stack pointer value
* in the interrupt vector table).
* For more information, please refer to AN2606 from www.st.com.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
{
FLASH_Status status = FLASH_COMPLETE;
assert_param(IS_FLASH_BOOT(FLASH_BOOT));
/* Authorize the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* Enable the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
if(FLASH_BOOT == FLASH_BOOT_Bank1)
{
OB->USER |= OB_USER_BFB2;
}
else
{
OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
/* Return the Option Byte program Status */
return status;
}
#endif /* STM32F10X_XL */
/**
* @brief Returns the FLASH User Option Bytes values.
* @note This function can be used for all STM32F10x devices.
* @param None
* @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
* and RST_STDBY(Bit2).
@ -651,6 +1220,7 @@ uint32_t FLASH_GetUserOptionByte(void)
/**
* @brief Returns the FLASH Write Protection Option Bytes Register value.
* @note This function can be used for all STM32F10x devices.
* @param None
* @retval The FLASH Write Protection Option Bytes Register value
*/
@ -662,6 +1232,7 @@ uint32_t FLASH_GetWriteProtectionOptionByte(void)
/**
* @brief Checks whether the FLASH Read Out Protection Status is set or not.
* @note This function can be used for all STM32F10x devices.
* @param None
* @retval FLASH ReadOut Protection Status(SET or RESET)
*/
@ -681,6 +1252,7 @@ FlagStatus FLASH_GetReadOutProtectionStatus(void)
/**
* @brief Checks whether the FLASH Prefetch Buffer status is set or not.
* @note This function can be used for all STM32F10x devices.
* @param None
* @retval FLASH Prefetch Buffer Status (SET or RESET).
*/
@ -702,6 +1274,10 @@ FlagStatus FLASH_GetPrefetchBufferStatus(void)
/**
* @brief Enables or disables the specified FLASH interrupts.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
for Bank1 and Bank2.
* - For other devices it enables or disables the specified FLASH interrupts for Bank1.
* @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg FLASH_IT_ERROR: FLASH Error Interrupt
@ -710,11 +1286,44 @@ FlagStatus FLASH_GetPrefetchBufferStatus(void)
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
{
#ifdef STM32F10X_XL
/* Check the parameters */
assert_param(IS_FLASH_IT(FLASH_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if((FLASH_IT & 0x80000000) != 0x0)
{
if(NewState != DISABLE)
{
/* Enable the interrupt sources */
FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
}
else
{
/* Disable the interrupt sources */
FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
}
}
else
{
if(NewState != DISABLE)
{
/* Enable the interrupt sources */
FLASH->CR |= FLASH_IT;
}
else
{
/* Disable the interrupt sources */
FLASH->CR &= ~(uint32_t)FLASH_IT;
}
}
#else
/* Check the parameters */
assert_param(IS_FLASH_IT(FLASH_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState != DISABLE)
{
/* Enable the interrupt sources */
@ -725,10 +1334,16 @@ void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)
/* Disable the interrupt sources */
FLASH->CR &= ~(uint32_t)FLASH_IT;
}
#endif /* STM32F10X_XL */
}
/**
* @brief Checks whether the specified FLASH flag is set or not.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices, this function checks whether the specified
* Bank1 or Bank2 flag is set or not.
* - For other devices, it checks whether the specified Bank1 flag is
* set or not.
* @param FLASH_FLAG: specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg FLASH_FLAG_BSY: FLASH Busy flag
@ -738,9 +1353,50 @@ void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)
* @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
{
FlagStatus bitstatus = RESET;
#ifdef STM32F10X_XL
/* Check the parameters */
assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
{
if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if((FLASH_FLAG & 0x80000000) != 0x0)
{
if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
}
#else
/* Check the parameters */
assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
@ -765,12 +1421,17 @@ FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)
bitstatus = RESET;
}
}
#endif /* STM32F10X_XL */
/* Return the new state of FLASH_FLAG (SET or RESET) */
return bitstatus;
}
/**
* @brief Clears the FLASH’s pending flags.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags
* - For other devices, it clears Bank1’s pending flags.
* @param FLASH_FLAG: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_PGERR: FLASH Program error flag
@ -778,17 +1439,36 @@ FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @retval None
*/
void FLASH_ClearFlag(uint16_t FLASH_FLAG)
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
{
#ifdef STM32F10X_XL
/* Check the parameters */
assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
if((FLASH_FLAG & 0x80000000) != 0x0)
{
/* Clear the flags */
FLASH->SR2 = FLASH_FLAG;
}
else
{
/* Clear the flags */
FLASH->SR = FLASH_FLAG;
}
#else
/* Check the parameters */
assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
/* Clear the flags */
FLASH->SR = FLASH_FLAG;
#endif /* STM32F10X_XL */
}
/**
* @brief Returns the FLASH Status.
* @note This function can be used for all STM32F10x devices, it is equivalent
* to FLASH_GetBank1Status function.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE
@ -823,8 +1503,90 @@ FLASH_Status FLASH_GetStatus(void)
return flashstatus;
}
/**
* @brief Returns the FLASH Bank1 Status.
* @note This function can be used for all STM32F10x devices, it is equivalent
* to FLASH_GetStatus function.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE
*/
FLASH_Status FLASH_GetBank1Status(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
{
flashstatus = FLASH_BUSY;
}
else
{
if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
/* Return the Flash Status */
return flashstatus;
}
#ifdef STM32F10X_XL
/**
* @brief Returns the FLASH Bank2 Status.
* @note This function can be used for STM32F10x_XL density devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE
*/
FLASH_Status FLASH_GetBank2Status(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
{
flashstatus = FLASH_BUSY;
}
else
{
if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
/* Return the Flash Status */
return flashstatus;
}
#endif /* STM32F10X_XL */
/**
* @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
* @note This function can be used for all STM32F10x devices,
* it is equivalent to FLASH_WaitForLastBank1Operation.
* - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
* to complete or a TIMEOUT to occur.
* - For all other devices it waits for a Flash operation to complete
* or a TIMEOUT to occur.
* @param Timeout: FLASH progamming Timeout
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
@ -834,12 +1596,11 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
FLASH_Status status = FLASH_COMPLETE;
/* Check for the Flash Status */
status = FLASH_GetStatus();
status = FLASH_GetBank1Status();
/* Wait for a Flash operation to complete or a TIMEOUT to occur */
while((status == FLASH_BUSY) && (Timeout != 0x00))
{
delay();
status = FLASH_GetStatus();
status = FLASH_GetBank1Status();
Timeout--;
}
if(Timeout == 0x00 )
@ -851,18 +1612,62 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
}
/**
* @brief Inserts a time delay.
* @param None
* @retval None
* @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
* @note This function can be used for all STM32F10x devices,
* it is equivalent to FLASH_WaitForLastOperation.
* @param Timeout: FLASH progamming Timeout
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
static void delay(void)
{
__IO uint32_t i = 0;
for(i = 0xFF; i != 0; i--)
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check for the Flash Status */
status = FLASH_GetBank1Status();
/* Wait for a Flash operation to complete or a TIMEOUT to occur */
while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
{
status = FLASH_GetBank1Status();
Timeout--;
}
if(Timeout == 0x00 )
{
status = FLASH_TIMEOUT;
}
/* Return the operation status */
return status;
}
#ifdef STM32F10X_XL
/**
* @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
* @note This function can be used only for STM32F10x_XL density devices.
* @param Timeout: FLASH progamming Timeout
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check for the Flash Status */
status = FLASH_GetBank2Status();
/* Wait for a Flash operation to complete or a TIMEOUT to occur */
while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
{
status = FLASH_GetBank2Status();
Timeout--;
}
if(Timeout == 0x00 )
{
status = FLASH_TIMEOUT;
}
/* Return the operation status */
return status;
}
#endif /* STM32F10X_XL */
/**
* @}
*/
@ -875,4 +1680,4 @@ static void delay(void)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

13
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c Normal file → Executable file
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_fsmc.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the FSMC firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -180,6 +180,7 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
@ -201,6 +202,7 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
@ -208,10 +210,12 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
}
/* Bank1 NOR/SRAM timing register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
@ -378,6 +382,7 @@ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
@ -855,4 +860,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

110
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c Normal file → Executable file
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_gpio.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the GPIO firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -57,7 +57,7 @@
/* --- MAPR Register ---*/
/* Alias word address of MII_RMII_SEL bit */
#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
#define MII_RMII_SEL_BitNumber ((u8)0x17)
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
@ -169,7 +169,7 @@ void GPIO_AFIODeInit(void)
* contains the configuration information for the specified GPIO peripheral.
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, const GPIO_InitTypeDef* GPIO_InitStruct)
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
uint32_t tmpreg = 0x00, pinmask = 0x00;
@ -491,38 +491,54 @@ void GPIO_EventOutputCmd(FunctionalState NewState)
* @brief Changes the mapping of the specified pin.
* @param GPIO_Remap: selects the pin to remap.
* This parameter can be one of the following values:
* @arg GPIO_Remap_SPI1
* @arg GPIO_Remap_I2C1
* @arg GPIO_Remap_USART1
* @arg GPIO_Remap_USART2
* @arg GPIO_PartialRemap_USART3
* @arg GPIO_FullRemap_USART3
* @arg GPIO_PartialRemap_TIM1
* @arg GPIO_FullRemap_TIM1
* @arg GPIO_PartialRemap1_TIM2
* @arg GPIO_PartialRemap2_TIM2
* @arg GPIO_FullRemap_TIM2
* @arg GPIO_PartialRemap_TIM3
* @arg GPIO_FullRemap_TIM3
* @arg GPIO_Remap_TIM4
* @arg GPIO_Remap1_CAN1
* @arg GPIO_Remap2_CAN1
* @arg GPIO_Remap_PD01
* @arg GPIO_Remap_TIM5CH4_LSI
* @arg GPIO_Remap_ADC1_ETRGINJ
* @arg GPIO_Remap_ADC1_ETRGREG
* @arg GPIO_Remap_ADC2_ETRGINJ
* @arg GPIO_Remap_ADC2_ETRGREG
* @arg GPIO_Remap_ETH
* @arg GPIO_Remap_CAN2
* @arg GPIO_Remap_SWJ_NoJTRST
* @arg GPIO_Remap_SWJ_JTAGDisable
* @arg GPIO_Remap_SWJ_Disable
* @arg GPIO_Remap_SPI3
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF
* @arg GPIO_Remap_PTP_PPS
* @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected
* to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
* @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
* @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
* @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
* @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
* @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
* @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
* @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
* @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
* @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
* @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
* @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
* @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
* @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
* @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
* @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
* @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
* @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
* @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
* @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
* @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
* @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
* @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
* @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
* @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
* @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
* @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
* Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
* @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
* @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
* @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
* @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
* @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
* @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
* @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
* @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
* @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
* @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
* @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
* only for High density Value line devices)
* @param NewState: new state of the port pin remapping.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -535,7 +551,14 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
assert_param(IS_GPIO_REMAP(GPIO_Remap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmpreg = AFIO->MAPR;
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
tmpreg = AFIO->MAPR2;
}
else
{
tmpreg = AFIO->MAPR;
}
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
@ -562,7 +585,14 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
}
AFIO->MAPR = tmpreg;
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
AFIO->MAPR2 = tmpreg;
}
else
{
AFIO->MAPR = tmpreg;
}
}
/**
@ -614,4 +644,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

211
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_i2c.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the I2C firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -187,7 +187,7 @@ void I2C_DeInit(I2C_TypeDef* I2Cx)
* contains the configuration information for the specified I2C peripheral.
* @retval None
*/
void I2C_Init(I2C_TypeDef* I2Cx, const I2C_InitTypeDef* I2C_InitStruct)
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
{
uint16_t tmpreg = 0, freqrange = 0;
uint16_t result = 0x04;
@ -360,7 +360,7 @@ void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
}
/**
* @brief Specifies that the next DMA transfer is the last one.
* @brief Specifies if the next DMA transfer will be the last one.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param NewState: new state of the I2C DMA last transfer.
* This parameter can be: ENABLE or DISABLE.
@ -546,7 +546,7 @@ void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
// assert_param(IS_I2C_CONFIG_IT(I2C_IT)); // TODO: Why?
assert_param(IS_I2C_CONFIG_IT(I2C_IT));
if (NewState != DISABLE)
{
@ -858,26 +858,94 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
}
}
/**
* @brief Returns the last I2Cx Event.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @retval The last event
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Read the I2Cx status register */
flag1 = I2Cx->SR1;
flag2 = I2Cx->SR2;
flag2 = flag2 << 16;
/* Get the last event value from I2C status register */
lastevent = (flag1 | flag2) & FLAG_Mask;
/* Return status */
return lastevent;
}
* @brief
****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* depending on the application requirements and constraints:
*
*
* 1) Basic state monitoring:
* Using I2C_CheckEvent() function:
* It compares the status registers (SR1 and SR2) content to a given event
* (can be the combination of one or more flags).
* It returns SUCCESS if the current status includes the given flags
* and returns ERROR if one or more flags are missing in the current status.
* - When to use:
* - This function is suitable for most applciations as well as for startup
* activity since the events are fully described in the product reference manual
* (RM0008).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs (ie. error flags are set besides to the monitored flags),
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* hold or corrupted real state.
* In this case, it is advised to use error interrupts to monitor the error
* events and handle them in the interrupt IRQ handler.
*
* @note
* For error management, it is advised to use the following functions:
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
* - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
* in order to determine which error occured.
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
* and/or I2C_GenerateStop() in order to clear the error flag and source,
* and return to correct communication status.
*
*
* 2) Advanced state monitoring:
* Using the function I2C_GetLastEvent() which returns the image of both status
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
* by 16 bits and concatenated to Status Register 1).
* - When to use:
* - This function is suitable for the same applications above but it allows to
* overcome the mentionned limitation of I2C_GetFlagStatus() function.
* The returned value could be compared to events already defined in the
* library (stm32f10x_i2c.h) or to custom values defiend by user.
* - This function is suitable when multiple flags are monitored at the same time.
* - At the opposite of I2C_CheckEvent() function, this function allows user to
* choose when an event is accepted (when all events flags are set and no
* other flags are set or just when the needed flags are set like
* I2C_CheckEvent() function).
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* 3) Flag-based state monitoring:
* Using the function I2C_GetFlagStatus() which simply returns the status of
* one single flag (ie. I2C_FLAG_RXNE ...).
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed (most I2C events
* are monitored through multiple flags).
* - Limitations:
* - When calling this function, the Status register is accessed. Some flags are
* cleared when the status register is accessed. So checking the status
* of one Flag, may clear other ones.
* - Function may need to be called twice or more in order to monitor one
* single event.
*
* For detailed description of Events, please refer to section I2C_Events in
* stm32f10x_i2c.h file.
*
*/
/**
*
* 1) Basic state monitoring
*******************************************************************************
*/
/**
* @brief Checks whether the last I2Cx Event is equal to the one passed
@ -885,16 +953,30 @@ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_EVENT: specifies the event to be checked.
* This parameter can be one of the following values:
* @arg I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1
* @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
* @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
* @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2
* @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
* @arg I2C_EVENT_MASTER_MODE_SELECTED : EV6
* @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
* @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8
* @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
* @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
* @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
* @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
* @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
* @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
* @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
* @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
* @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
* @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
* @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
* @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
* @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
* @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
* @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
* @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
* @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
* @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
* @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
* @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
* @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
* @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
*
* @note: For detailed description of Events, please refer to section
* I2C_Events in stm32f10x_i2c.h file.
*
* @retval An ErrorStatus enumuration value:
* - SUCCESS: Last event is equal to the I2C_EVENT
* - ERROR: Last event is different from the I2C_EVENT
@ -904,17 +986,21 @@ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_EVENT(I2C_EVENT));
/* Read the I2Cx status register */
flag1 = I2Cx->SR1;
flag2 = I2Cx->SR2;
flag2 = flag2 << 16;
/* Get the last event value from I2C status register */
lastevent = (flag1 | flag2) & FLAG_Mask;
/* Check whether the last event is equal to I2C_EVENT */
if (lastevent == I2C_EVENT )
/* Check whether the last event contains the I2C_EVENT */
if ((lastevent & I2C_EVENT) == I2C_EVENT)
{
/* SUCCESS: last event is equal to I2C_EVENT */
status = SUCCESS;
@ -928,6 +1014,47 @@ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
return status;
}
/**
*
* 2) Advanced state monitoring
*******************************************************************************
*/
/**
* @brief Returns the last I2Cx Event.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
*
* @note: For detailed description of Events, please refer to section
* I2C_Events in stm32f10x_i2c.h file.
*
* @retval The last event
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Read the I2Cx status register */
flag1 = I2Cx->SR1;
flag2 = I2Cx->SR2;
flag2 = flag2 << 16;
/* Get the last event value from I2C status register */
lastevent = (flag1 | flag2) & FLAG_Mask;
/* Return status */
return lastevent;
}
/**
*
* 3) Flag-based state monitoring
*******************************************************************************
*/
/**
* @brief Checks whether the specified I2C flag is set or not.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
@ -1003,6 +1130,8 @@ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
return bitstatus;
}
/**
* @brief Clears the I2Cx's pending flags.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
@ -1072,13 +1201,17 @@ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_GET_IT(I2C_IT));
/* Check if the interrupt source is enabled or not */
enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
/* Get bit[23:0] of the flag */
I2C_IT &= FLAG_Mask;
/* Check the status of the specified I2C flag */
if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
{
@ -1149,4 +1282,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_iwdg.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the IWDG firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -186,4 +186,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

35
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_pwr.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the PWR firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -67,18 +67,10 @@
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_PDDS_Set ((uint32_t)0x00000002)
#define CR_DS_Mask ((uint32_t)0xFFFFFFFC)
#define CR_CWUF_Set ((uint32_t)0x00000004)
#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F)
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
/* --------- Cortex System Control register bit mask ---------------- */
/* Cortex System Control register address */
#define SCB_SysCtrl ((uint32_t)0xE000ED10)
/* SLEEPDEEP bit mask */
#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)
/**
* @}
*/
@ -169,7 +161,7 @@ void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_Mask;
tmpreg &= CR_PLS_MASK;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
@ -211,13 +203,13 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_Mask;
tmpreg &= CR_DS_MASK;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
SCB->SCR |= SCB_SCR_SLEEPDEEP;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
@ -230,6 +222,9 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
}
/**
@ -240,11 +235,11 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wake-up flag */
PWR->CR |= CR_CWUF_Set;
PWR->CR |= PWR_CR_CWUF;
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
PWR->CR |= PWR_CR_PDDS;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
SCB->SCR |= SCB_SCR_SLEEPDEEP;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM )
__force_stores();
@ -308,4 +303,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

108
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_rcc.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the RCC firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -124,10 +124,10 @@
#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
/* CFGR register bit mask */
#ifndef STM32F10X_CL
#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
#define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
#else
#define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
#endif /* STM32F10X_CL */
#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
@ -147,10 +147,12 @@
/* CSR register bit mask */
#define CSR_RMVF_Set ((uint32_t)0x01000000)
#ifdef STM32F10X_CL
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
/* CFGR2 register bit mask */
#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
#define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
#endif
#ifdef STM32F10X_CL
#define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
#define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
#define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
@ -159,11 +161,6 @@
/* RCC Flag Mask */
#define FLAG_Mask ((uint8_t)0x1F)
#ifndef HSI_Value
/* Typical Value of the HSI in Hz */
#define HSI_Value ((uint32_t)8000000)
#endif /* HSI_Value */
/* CIR register byte 2 (Bits[15:8]) base address */
#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
@ -176,11 +173,6 @@
/* BDCR register base address */
#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
#ifndef HSEStartUp_TimeOut
/* Time out for HSE start up */
#define HSEStartUp_TimeOut ((uint16_t)0x0500)
#endif /* HSEStartUp_TimeOut */
/**
* @}
*/
@ -242,10 +234,7 @@ void RCC_DeInit(void)
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifndef STM32F10X_CL
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#else
#ifdef STM32F10X_CL
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
@ -254,7 +243,17 @@ void RCC_DeInit(void)
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */
}
/**
@ -312,7 +311,7 @@ ErrorStatus RCC_WaitForHSEStartUp(void)
{
HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
StartUpCounter++;
} while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET));
} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
{
@ -362,8 +361,8 @@ void RCC_HSICmd(FunctionalState NewState)
* @brief Configures the PLL clock source and multiplication factor.
* @note This function must be used only when the PLL is disabled.
* @param RCC_PLLSource: specifies the PLL entry clock source.
* For @b STM32_Connectivity_line_devices, this parameter can be one of the
* following values:
* For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices,
* this parameter can be one of the following values:
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
* For @b other_STM32_devices, this parameter can be one of the following values:
@ -406,16 +405,19 @@ void RCC_PLLCmd(FunctionalState NewState)
*(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
}
#ifdef STM32F10X_CL
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
/**
* @brief Configures the PREDIV1 division factor.
* @note
* - This function must be used only when the PLL is disabled.
* - This function applies only to STM32 Connectivity line devices.
* - This function applies only to STM32 Connectivity line and Value line
* devices.
* @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
* This parameter can be one of the following values:
* @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
* @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
* @note
* For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE
* @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
* This parameter can be RCC_PREDIV1_Divx where x:[1,16]
* @retval None
@ -436,8 +438,9 @@ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
/* Store the new value */
RCC->CFGR2 = tmpreg;
}
#endif
#ifdef STM32F10X_CL
/**
* @brief Configures the PREDIV2 division factor.
* @note
@ -896,7 +899,9 @@ void RCC_RTCCLKCmd(FunctionalState NewState)
/**
* @brief Returns the frequencies of different on chip clocks.
* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
* the clocks frequencies.
* the clocks frequencies.
* @note The result of this function could be not correct when using
* fractional value for HSE crystal.
* @retval None
*/
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
@ -906,6 +911,10 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
#ifdef STM32F10X_CL
uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
#endif /* STM32F10X_CL */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
uint32_t prediv1factor = 0;
#endif
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & CFGR_SWS_Mask;
@ -913,10 +922,10 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
switch (tmp)
{
case 0x00: /* HSI used as system clock */
RCC_Clocks->SYSCLK_Frequency = HSI_Value;
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
RCC_Clocks->SYSCLK_Frequency = HSE_Value;
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock */
@ -929,18 +938,25 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
if (pllsource == 0x00)
{/* HSI oscillator clock divided by 2 selected as PLL clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
}
else
{/* HSE selected as PLL clock entry */
{
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
}
else
{
RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
}
#endif
}
#else
pllmull = pllmull >> 18;
@ -956,7 +972,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
if (pllsource == 0x00)
{/* HSI oscillator clock divided by 2 selected as PLL clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
@ -967,7 +983,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
if (prediv1source == 0)
{ /* HSE oscillator clock selected as PREDIV1 clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
@ -975,14 +991,14 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F10X_CL */
break;
default:
RCC_Clocks->SYSCLK_Frequency = HSI_Value;
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
break;
}
@ -1068,7 +1084,9 @@ void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
* RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
* RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1098,7 +1116,8 @@ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
* RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1155,7 +1174,9 @@ void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
* RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
* RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
* @param NewState: new state of the specified peripheral reset.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1185,7 +1206,8 @@ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
* RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1444,4 +1466,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

27
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_rtc.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the RTC firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -40,11 +40,8 @@
/** @defgroup RTC_Private_Defines
* @{
*/
#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */
#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */
#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
/**
* @}
@ -113,7 +110,7 @@ void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
void RTC_EnterConfigMode(void)
{
/* Set the CNF flag to enter in the Configuration Mode */
RTC->CRL |= CRL_CNF_Set;
RTC->CRL |= RTC_CRL_CNF;
}
/**
@ -124,7 +121,7 @@ void RTC_EnterConfigMode(void)
void RTC_ExitConfigMode(void)
{
/* Reset the CNF flag to exit from the Configuration Mode */
RTC->CRL &= CRL_CNF_Reset;
RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
}
/**
@ -150,7 +147,7 @@ void RTC_SetCounter(uint32_t CounterValue)
/* Set RTC COUNTER MSB word */
RTC->CNTH = CounterValue >> 16;
/* Set RTC COUNTER LSB word */
RTC->CNTL = (CounterValue & RTC_LSB_Mask);
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
@ -166,9 +163,9 @@ void RTC_SetPrescaler(uint32_t PrescalerValue)
RTC_EnterConfigMode();
/* Set RTC PRESCALER MSB word */
RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;
RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
/* Set RTC PRESCALER LSB word */
RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
@ -183,7 +180,7 @@ void RTC_SetAlarm(uint32_t AlarmValue)
/* Set the ALARM MSB word */
RTC->ALRH = AlarmValue >> 16;
/* Set the ALARM LSB word */
RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
@ -338,4 +335,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_sdio.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the SDIO firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -795,4 +795,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

10
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_spi.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the SPI firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -154,7 +154,7 @@ void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
* contains the configuration information for the specified SPI peripheral.
* @retval None
*/
void SPI_Init(SPI_TypeDef* SPIx, const SPI_InitTypeDef* SPI_InitStruct)
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
{
uint16_t tmpreg = 0;
@ -904,4 +904,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

799
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_tim.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the TIM firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -44,77 +44,11 @@
*/
/* ---------------------- TIM registers bit mask ------------------------ */
#define CR1_CEN_Set ((uint16_t)0x0001)
#define CR1_CEN_Reset ((uint16_t)0x03FE)
#define CR1_UDIS_Set ((uint16_t)0x0002)
#define CR1_UDIS_Reset ((uint16_t)0x03FD)
#define CR1_URS_Set ((uint16_t)0x0004)
#define CR1_URS_Reset ((uint16_t)0x03FB)
#define CR1_OPM_Reset ((uint16_t)0x03F7)
#define CR1_CounterMode_Mask ((uint16_t)0x038F)
#define CR1_ARPE_Set ((uint16_t)0x0080)
#define CR1_ARPE_Reset ((uint16_t)0x037F)
#define CR1_CKD_Mask ((uint16_t)0x00FF)
#define CR2_CCPC_Set ((uint16_t)0x0001)
#define CR2_CCPC_Reset ((uint16_t)0xFFFE)
#define CR2_CCUS_Set ((uint16_t)0x0004)
#define CR2_CCUS_Reset ((uint16_t)0xFFFB)
#define CR2_CCDS_Set ((uint16_t)0x0008)
#define CR2_CCDS_Reset ((uint16_t)0xFFF7)
#define CR2_MMS_Mask ((uint16_t)0xFF8F)
#define CR2_TI1S_Set ((uint16_t)0x0080)
#define CR2_TI1S_Reset ((uint16_t)0xFF7F)
#define CR2_OIS1_Reset ((uint16_t)0x7EFF)
#define CR2_OIS1N_Reset ((uint16_t)0x7DFF)
#define CR2_OIS2_Reset ((uint16_t)0x7BFF)
#define CR2_OIS2N_Reset ((uint16_t)0x77FF)
#define CR2_OIS3_Reset ((uint16_t)0x6FFF)
#define CR2_OIS3N_Reset ((uint16_t)0x5FFF)
#define CR2_OIS4_Reset ((uint16_t)0x3FFF)
#define SMCR_SMS_Mask ((uint16_t)0xFFF8)
#define SMCR_ETR_Mask ((uint16_t)0x00FF)
#define SMCR_TS_Mask ((uint16_t)0xFF8F)
#define SMCR_MSM_Reset ((uint16_t)0xFF7F)
#define SMCR_ECE_Set ((uint16_t)0x4000)
#define CCMR_CC13S_Mask ((uint16_t)0xFFFC)
#define CCMR_CC24S_Mask ((uint16_t)0xFCFF)
#define CCMR_TI13Direct_Set ((uint16_t)0x0001)
#define CCMR_TI24Direct_Set ((uint16_t)0x0100)
#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB)
#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF)
#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7)
#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF)
#define CCMR_OC13M_Mask ((uint16_t)0xFF8F)
#define CCMR_OC24M_Mask ((uint16_t)0x8FFF)
#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F)
#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF)
#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3)
#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF)
#define CCMR_IC13F_Mask ((uint16_t)0xFF0F)
#define CCMR_IC24F_Mask ((uint16_t)0x0FFF)
#define SMCR_ETR_Mask ((uint16_t)0x00FF)
#define CCMR_Offset ((uint16_t)0x0018)
#define CCER_CCE_Set ((uint16_t)0x0001)
#define CCER_CCNE_Set ((uint16_t)0x0004)
#define CCER_CC1P_Reset ((uint16_t)0xFFFD)
#define CCER_CC2P_Reset ((uint16_t)0xFFDF)
#define CCER_CC3P_Reset ((uint16_t)0xFDFF)
#define CCER_CC4P_Reset ((uint16_t)0xDFFF)
#define CCER_CC1NP_Reset ((uint16_t)0xFFF7)
#define CCER_CC2NP_Reset ((uint16_t)0xFF7F)
#define CCER_CC3NP_Reset ((uint16_t)0xF7FF)
#define CCER_CC1E_Set ((uint16_t)0x0001)
#define CCER_CC1E_Reset ((uint16_t)0xFFFE)
#define CCER_CC1NE_Reset ((uint16_t)0xFFFB)
#define CCER_CC2E_Set ((uint16_t)0x0010)
#define CCER_CC2E_Reset ((uint16_t)0xFFEF)
#define CCER_CC2NE_Reset ((uint16_t)0xFFBF)
#define CCER_CC3E_Set ((uint16_t)0x0100)
#define CCER_CC3E_Reset ((uint16_t)0xFEFF)
#define CCER_CC3NE_Reset ((uint16_t)0xFBFF)
#define CCER_CC4E_Set ((uint16_t)0x1000)
#define CCER_CC4E_Reset ((uint16_t)0xEFFF)
#define BDTR_MOE_Set ((uint16_t)0x8000)
#define BDTR_MOE_Reset ((uint16_t)0x7FFF)
#define CCER_CCE_Set ((uint16_t)0x0001)
#define CCER_CCNE_Set ((uint16_t)0x0004)
/**
* @}
*/
@ -181,7 +115,7 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
/**
* @brief Deinitializes the TIMx peripheral registers to their default reset values.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @retval None
*/
void TIM_DeInit(TIM_TypeDef* TIMx)
@ -224,12 +158,57 @@ void TIM_DeInit(TIM_TypeDef* TIMx)
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
}
else if (TIMx == TIM8)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
}
else if (TIMx == TIM9)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
}
else if (TIMx == TIM10)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
}
else if (TIMx == TIM11)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
}
else if (TIMx == TIM12)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
}
else if (TIMx == TIM13)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
}
else if (TIMx == TIM14)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
}
else if (TIMx == TIM15)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
}
else if (TIMx == TIM16)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
}
else
{
if (TIMx == TIM8)
if (TIMx == TIM17)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
}
}
}
@ -237,42 +216,60 @@ void TIM_DeInit(TIM_TypeDef* TIMx)
/**
* @brief Initializes the TIMx Time Base Unit peripheral according to
* the specified parameters in the TIM_TimeBaseInitStruct.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
* structure that contains the configuration information for the specified TIM peripheral.
* @retval None
*/
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
{
uint16_t tmpcr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_ALL_PERIPH(TIMx));
assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
/* Select the Counter Mode and set the clock division */
TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision |
TIM_TimeBaseInitStruct->TIM_CounterMode;
tmpcr1 = TIMx->CR1;
if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
(TIMx == TIM4) || (TIMx == TIM5))
{
/* Select the Counter Mode */
tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
}
if((TIMx != TIM6) && (TIMx != TIM7))
{
/* Set the clock division */
tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
}
TIMx->CR1 = tmpcr1;
/* Set the Autoreload value */
TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
/* Set the Prescaler value */
TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE))
if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
{
/* Set the Repetition Counter value */
TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
}
/* Generate an update event to reload the Prescaler value immediatly */
TIMx->EGR = TIM_PSCReloadMode_Immediate;
/* Generate an update event to reload the Prescaler and the Repetition counter
values immediately */
TIMx->EGR = TIM_PSCReloadMode_Immediate;
}
/**
* @brief Initializes the TIMx Channel1 according to the specified
* parameters in the TIM_OCInitStruct.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
* that contains the configuration information for the specified TIM peripheral.
* @retval None
@ -282,13 +279,12 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= CCER_CC1E_Reset;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
@ -297,21 +293,23 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask;
/* Reset the Output Compare Mode Bits */
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
/* Select the Output Compare Mode */
tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
/* Reset the Output Polarity level */
tmpccer &= CCER_CC1P_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
/* Set the Output Compare Polarity */
tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
/* Set the Output State */
tmpccer |= TIM_OCInitStruct->TIM_OutputState;
if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
(TIMx == TIM16)|| (TIMx == TIM17))
{
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
@ -319,17 +317,19 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= CCER_CC1NP_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
/* Set the Output N Polarity */
tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
/* Reset the Output N State */
tmpccer &= CCER_CC1NE_Reset;
/* Reset the Output N State */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
/* Set the Output N State */
tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
/* Reset the Ouput Compare and Output Compare N IDLE State */
tmpcr2 &= CR2_OIS1_Reset;
tmpcr2 &= CR2_OIS1N_Reset;
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
/* Set the Output Idle state */
tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
/* Set the Output N Idle state */
@ -342,8 +342,8 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
TIMx->CCMR1 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
}
@ -351,7 +351,8 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
/**
* @brief Initializes the TIMx Channel2 according to the specified
* parameters in the TIM_OCInitStruct.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
* the TIM peripheral.
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
* that contains the configuration information for the specified TIM peripheral.
* @retval None
@ -361,12 +362,12 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= CCER_CC2E_Reset;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
@ -375,22 +376,23 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask;
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
/* Select the Output Compare Mode */
tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
/* Reset the Output Polarity level */
tmpccer &= CCER_CC2P_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
/* Set the Output Compare Polarity */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
/* Set the Output State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
if((TIMx == TIM1) || (TIMx == TIM8))
{
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
@ -398,17 +400,19 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= CCER_CC2NP_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
/* Set the Output N Polarity */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
/* Reset the Output N State */
tmpccer &= CCER_CC2NE_Reset;
/* Reset the Output N State */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
/* Set the Output N State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
/* Reset the Ouput Compare and Output Compare N IDLE State */
tmpcr2 &= CR2_OIS2_Reset;
tmpcr2 &= CR2_OIS2N_Reset;
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
/* Set the Output Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
/* Set the Output N Idle state */
@ -440,12 +444,12 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= CCER_CC3E_Reset;
TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
@ -456,20 +460,20 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask;
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
/* Select the Output Compare Mode */
tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
/* Reset the Output Polarity level */
tmpccer &= CCER_CC3P_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
/* Set the Output Compare Polarity */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
/* Set the Output State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
if((TIMx == TIM1) || (TIMx == TIM8))
{
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
@ -477,17 +481,17 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= CCER_CC3NP_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
/* Set the Output N Polarity */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
/* Reset the Output N State */
tmpccer &= CCER_CC3NE_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
/* Set the Output N State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
/* Reset the Ouput Compare and Output Compare N IDLE State */
tmpcr2 &= CR2_OIS3_Reset;
tmpcr2 &= CR2_OIS3N_Reset;
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
/* Set the Output Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
/* Set the Output N Idle state */
@ -519,12 +523,12 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 2: Reset the CC4E Bit */
TIMx->CCER &= CCER_CC4E_Reset;
TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
@ -535,24 +539,25 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask;
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
/* Select the Output Compare Mode */
tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
/* Reset the Output Polarity level */
tmpccer &= CCER_CC4P_Reset;
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
/* Set the Output Compare Polarity */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
/* Set the Output State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
if((TIMx == TIM1) || (TIMx == TIM8))
{
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Ouput Compare IDLE State */
tmpcr2 &= CR2_OIS4_Reset;
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
/* Set the Output Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
}
@ -572,7 +577,7 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
/**
* @brief Initializes the TIM peripheral according to the specified
* parameters in the TIM_ICInitStruct.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
* that contains the configuration information for the specified TIM peripheral.
* @retval None
@ -580,15 +585,23 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
(TIMx == TIM4) ||(TIMx == TIM5))
{
assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
}
else
{
assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
}
if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
{
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
/* TI1 Configuration */
TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
@ -598,6 +611,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
}
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
{
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
/* TI2 Configuration */
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
@ -607,6 +621,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
}
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
{
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
/* TI3 Configuration */
TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
@ -616,6 +631,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
}
else
{
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
/* TI4 Configuration */
TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
@ -628,7 +644,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
/**
* @brief Configures the TIM peripheral according to the specified
* parameters in the TIM_ICInitStruct to measure an external PWM signal.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
* that contains the configuration information for the specified TIM peripheral.
* @retval None
@ -638,7 +654,7 @@ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
/* Select the Opposite Input Polarity */
if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
{
@ -694,7 +710,7 @@ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
@ -780,7 +796,7 @@ void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
/**
* @brief Enables or disables the specified TIM peripheral.
* @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
* @param NewState: new state of the TIMx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -794,18 +810,18 @@ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
if (NewState != DISABLE)
{
/* Enable the TIM Counter */
TIMx->CR1 |= CR1_CEN_Set;
TIMx->CR1 |= TIM_CR1_CEN;
}
else
{
/* Disable the TIM Counter */
TIMx->CR1 &= CR1_CEN_Reset;
TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
}
}
/**
* @brief Enables or disables the TIM peripheral Main Outputs.
* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
* @param NewState: new state of the TIM peripheral Main Outputs.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -813,23 +829,23 @@ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the TIM Main Output */
TIMx->BDTR |= BDTR_MOE_Set;
TIMx->BDTR |= TIM_BDTR_MOE;
}
else
{
/* Disable the TIM Main Output */
TIMx->BDTR &= BDTR_MOE_Reset;
TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
}
}
/**
* @brief Enables or disables the specified TIM interrupts.
* @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg TIM_IT_Update: TIM update Interrupt source
@ -841,8 +857,12 @@ void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
* @arg TIM_IT_Break: TIM Break Interrupt source
* @note
* - TIM6 and TIM7 can only generate an update interrupt.
* - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
* - TIM6 and TIM7 can only generate an update interrupt.
* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
* TIM_IT_CC2 or TIM_IT_Trigger.
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
* @param NewState: new state of the TIM interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -868,7 +888,7 @@ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
/**
* @brief Configures the TIMx event to be generate by software.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_EventSource: specifies the event source.
* This parameter can be one or more of the following values:
* @arg TIM_EventSource_Update: Timer update Event source
@ -896,7 +916,8 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
/**
* @brief Configures the TIMx’s DMA interface.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
* the TIM peripheral.
* @param TIM_DMABase: DMA Base address.
* This parameter can be one of the following values:
* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
@ -914,7 +935,7 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST4_PERIPH(TIMx));
assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
/* Set the DMA Base and the DMA Burst Length */
@ -923,7 +944,8 @@ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurs
/**
* @brief Enables or disables the TIMx’s DMA Requests.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
* to select the TIM peripheral.
* @param TIM_DMASource: specifies the DMA Request sources.
* This parameter can be any combination of the following values:
* @arg TIM_DMA_Update: TIM update Interrupt source
@ -940,7 +962,7 @@ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurs
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
assert_param(IS_TIM_LIST9_PERIPH(TIMx));
assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
assert_param(IS_FUNCTIONAL_STATE(NewState));
@ -958,20 +980,21 @@ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewSt
/**
* @brief Configures the TIMx interrnal Clock
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
* to select the TIM peripheral.
* @retval None
*/
void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
/* Disable slave mode to clock the prescaler directly with the internal clock */
TIMx->SMCR &= SMCR_SMS_Mask;
TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
}
/**
* @brief Configures the TIMx Internal Trigger as External Clock
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_ITRSource: Trigger source.
* This parameter can be one of the following values:
* @param TIM_TS_ITR0: Internal Trigger 0
@ -983,7 +1006,7 @@ void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
/* Select the Internal Trigger */
TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
@ -993,7 +1016,7 @@ void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSou
/**
* @brief Configures the TIMx Trigger as External Clock
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_TIxExternalCLKSource: Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
@ -1011,7 +1034,7 @@ void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSo
uint16_t TIM_ICPolarity, uint16_t ICFilter)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
assert_param(IS_TIM_IC_FILTER(ICFilter));
@ -1052,7 +1075,7 @@ void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, ui
{
uint16_t tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
@ -1062,11 +1085,11 @@ void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, ui
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
/* Reset the SMS Bits */
tmpsmcr &= SMCR_SMS_Mask;
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
/* Select the External clock mode1 */
tmpsmcr |= TIM_SlaveMode_External1;
/* Select the Trigger selection : ETRF */
tmpsmcr &= SMCR_TS_Mask;
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
tmpsmcr |= TIM_TS_ETRF;
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
@ -1093,14 +1116,14 @@ void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
/* Configure the ETR Clock source */
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
/* Enable the External clock mode2 */
TIMx->SMCR |= SMCR_ECE_Set;
TIMx->SMCR |= TIM_SMCR_ECE;
}
/**
@ -1125,7 +1148,7 @@ void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM
{
uint16_t tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
@ -1140,12 +1163,12 @@ void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM
/**
* @brief Configures the TIMx Prescaler.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param Prescaler: specifies the Prescaler Register value
* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
* This parameter can be one of the following values:
* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
* @retval None
*/
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
@ -1175,11 +1198,11 @@ void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
{
uint16_t tmpcr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
tmpcr1 = TIMx->CR1;
/* Reset the CMS and DIR Bits */
tmpcr1 &= CR1_CounterMode_Mask;
tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
/* Set the Counter Mode */
tmpcr1 |= TIM_CounterMode;
/* Write to TIMx CR1 register */
@ -1188,7 +1211,7 @@ void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
/**
* @brief Selects the Input Trigger source
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_InputTriggerSource: The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal Trigger 0
@ -1205,12 +1228,12 @@ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
{
uint16_t tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
/* Reset the TS Bits */
tmpsmcr &= SMCR_TS_Mask;
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
/* Set the Input Trigger source */
tmpsmcr |= TIM_InputTriggerSource;
/* Write to TIMx SMCR */
@ -1244,45 +1267,43 @@ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST5_PERIPH(TIMx));
assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
/* Get the TIMx CCMR1 register value */
tmpccmr1 = TIMx->CCMR1;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Set the encoder Mode */
tmpsmcr &= SMCR_SMS_Mask;
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
tmpsmcr |= TIM_EncoderMode;
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
/* Set the TI1 and the TI2 Polarities */
tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmr1;
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
}
/**
* @brief Forces the TIMx output 1 waveform to active or inactive level.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
* This parameter can be one of the following values:
* @arg TIM_ForcedAction_Active: Force active level on OC1REF
@ -1293,11 +1314,11 @@ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC1M Bits */
tmpccmr1 &= CCMR_OC13M_Mask;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
/* Configure The Forced output Mode */
tmpccmr1 |= TIM_ForcedAction;
/* Write to TIMx CCMR1 register */
@ -1306,7 +1327,7 @@ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
/**
* @brief Forces the TIMx output 2 waveform to active or inactive level.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
* This parameter can be one of the following values:
* @arg TIM_ForcedAction_Active: Force active level on OC2REF
@ -1317,11 +1338,11 @@ void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC2M Bits */
tmpccmr1 &= CCMR_OC24M_Mask;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
/* Configure The Forced output Mode */
tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
/* Write to TIMx CCMR1 register */
@ -1341,11 +1362,11 @@ void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC1M Bits */
tmpccmr2 &= CCMR_OC13M_Mask;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
/* Configure The Forced output Mode */
tmpccmr2 |= TIM_ForcedAction;
/* Write to TIMx CCMR2 register */
@ -1365,11 +1386,11 @@ void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC2M Bits */
tmpccmr2 &= CCMR_OC24M_Mask;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
/* Configure The Forced output Mode */
tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
/* Write to TIMx CCMR2 register */
@ -1378,7 +1399,7 @@ void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
/**
* @brief Enables or disables TIMx peripheral Preload register on ARR.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param NewState: new state of the TIMx peripheral Preload register
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1391,18 +1412,18 @@ void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
if (NewState != DISABLE)
{
/* Set the ARR Preload Bit */
TIMx->CR1 |= CR1_ARPE_Set;
TIMx->CR1 |= TIM_CR1_ARPE;
}
else
{
/* Reset the ARR Preload Bit */
TIMx->CR1 &= CR1_ARPE_Reset;
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
}
}
/**
* @brief Selects the TIM peripheral Commutation event.
* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
* @param NewState: new state of the Commutation event.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1410,23 +1431,24 @@ void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Set the COM Bit */
TIMx->CR2 |= CR2_CCUS_Set;
TIMx->CR2 |= TIM_CR2_CCUS;
}
else
{
/* Reset the COM Bit */
TIMx->CR2 &= CR2_CCUS_Reset;
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
}
}
/**
* @brief Selects the TIMx peripheral Capture Compare DMA source.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
* the TIM peripheral.
* @param NewState: new state of the Capture Compare DMA source
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1434,23 +1456,24 @@ void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST4_PERIPH(TIMx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Set the CCDS Bit */
TIMx->CR2 |= CR2_CCDS_Set;
TIMx->CR2 |= TIM_CR2_CCDS;
}
else
{
/* Reset the CCDS Bit */
TIMx->CR2 &= CR2_CCDS_Reset;
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
}
}
/**
* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
* to select the TIMx peripheral
* @param NewState: new state of the Capture Compare Preload Control bit
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1458,23 +1481,23 @@ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST5_PERIPH(TIMx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Set the CCPC Bit */
TIMx->CR2 |= CR2_CCPC_Set;
TIMx->CR2 |= TIM_CR2_CCPC;
}
else
{
/* Reset the CCPC Bit */
TIMx->CR2 &= CR2_CCPC_Reset;
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
}
}
/**
* @brief Enables or disables the TIMx peripheral Preload register on CCR1.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
* This parameter can be one of the following values:
* @arg TIM_OCPreload_Enable
@ -1485,11 +1508,11 @@ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC1PE Bit */
tmpccmr1 &= CCMR_OC13PE_Reset;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
/* Enable or Disable the Output Compare Preload feature */
tmpccmr1 |= TIM_OCPreload;
/* Write to TIMx CCMR1 register */
@ -1498,7 +1521,8 @@ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
/**
* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
* the TIM peripheral.
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
* This parameter can be one of the following values:
* @arg TIM_OCPreload_Enable
@ -1509,11 +1533,11 @@ void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC2PE Bit */
tmpccmr1 &= CCMR_OC24PE_Reset;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
/* Enable or Disable the Output Compare Preload feature */
tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
/* Write to TIMx CCMR1 register */
@ -1533,11 +1557,11 @@ void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC3PE Bit */
tmpccmr2 &= CCMR_OC13PE_Reset;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
/* Enable or Disable the Output Compare Preload feature */
tmpccmr2 |= TIM_OCPreload;
/* Write to TIMx CCMR2 register */
@ -1557,11 +1581,11 @@ void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC4PE Bit */
tmpccmr2 &= CCMR_OC24PE_Reset;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
/* Enable or Disable the Output Compare Preload feature */
tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
/* Write to TIMx CCMR2 register */
@ -1570,7 +1594,7 @@ void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
/**
* @brief Configures the TIMx Output Compare 1 Fast feature.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
* This parameter can be one of the following values:
* @arg TIM_OCFast_Enable: TIM output compare fast enable
@ -1581,12 +1605,12 @@ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
/* Get the TIMx CCMR1 register value */
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC1FE Bit */
tmpccmr1 &= CCMR_OC13FE_Reset;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
/* Enable or Disable the Output Compare Fast Bit */
tmpccmr1 |= TIM_OCFast;
/* Write to TIMx CCMR1 */
@ -1595,7 +1619,8 @@ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
/**
* @brief Configures the TIMx Output Compare 2 Fast feature.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
* the TIM peripheral.
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
* This parameter can be one of the following values:
* @arg TIM_OCFast_Enable: TIM output compare fast enable
@ -1606,12 +1631,12 @@ void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
/* Get the TIMx CCMR1 register value */
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC2FE Bit */
tmpccmr1 &= CCMR_OC24FE_Reset;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
/* Enable or Disable the Output Compare Fast Bit */
tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
/* Write to TIMx CCMR1 */
@ -1631,12 +1656,12 @@ void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
/* Get the TIMx CCMR2 register value */
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC3FE Bit */
tmpccmr2 &= CCMR_OC13FE_Reset;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
/* Enable or Disable the Output Compare Fast Bit */
tmpccmr2 |= TIM_OCFast;
/* Write to TIMx CCMR2 */
@ -1656,12 +1681,12 @@ void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
/* Get the TIMx CCMR2 register value */
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC4FE Bit */
tmpccmr2 &= CCMR_OC24FE_Reset;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
/* Enable or Disable the Output Compare Fast Bit */
tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
/* Write to TIMx CCMR2 */
@ -1681,11 +1706,13 @@ void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC1CE Bit */
tmpccmr1 &= CCMR_OC13CE_Reset;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
/* Enable or Disable the Output Compare Clear Bit */
tmpccmr1 |= TIM_OCClear;
/* Write to TIMx CCMR1 register */
@ -1705,11 +1732,11 @@ void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
{
uint16_t tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC2CE Bit */
tmpccmr1 &= CCMR_OC24CE_Reset;
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
/* Enable or Disable the Output Compare Clear Bit */
tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
/* Write to TIMx CCMR1 register */
@ -1729,11 +1756,11 @@ void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC3CE Bit */
tmpccmr2 &= CCMR_OC13CE_Reset;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
/* Enable or Disable the Output Compare Clear Bit */
tmpccmr2 |= TIM_OCClear;
/* Write to TIMx CCMR2 register */
@ -1753,11 +1780,11 @@ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
{
uint16_t tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC4CE Bit */
tmpccmr2 &= CCMR_OC24CE_Reset;
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
/* Enable or Disable the Output Compare Clear Bit */
tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
/* Write to TIMx CCMR2 register */
@ -1766,7 +1793,7 @@ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
/**
* @brief Configures the TIMx channel 1 polarity.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_OCPolarity: specifies the OC1 Polarity
* This parmeter can be one of the following values:
* @arg TIM_OCPolarity_High: Output Compare active high
@ -1777,11 +1804,11 @@ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
{
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
tmpccer = TIMx->CCER;
/* Set or Reset the CC1P Bit */
tmpccer &= CCER_CC1P_Reset;
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
tmpccer |= TIM_OCPolarity;
/* Write to TIMx CCER register */
TIMx->CCER = tmpccer;
@ -1789,7 +1816,7 @@ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
/**
* @brief Configures the TIMx Channel 1N polarity.
* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
* @param TIM_OCNPolarity: specifies the OC1N Polarity
* This parmeter can be one of the following values:
* @arg TIM_OCNPolarity_High: Output Compare active high
@ -1800,12 +1827,12 @@ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
{
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
tmpccer = TIMx->CCER;
/* Set or Reset the CC1NP Bit */
tmpccer &= CCER_CC1NP_Reset;
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
tmpccer |= TIM_OCNPolarity;
/* Write to TIMx CCER register */
TIMx->CCER = tmpccer;
@ -1813,7 +1840,7 @@ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
/**
* @brief Configures the TIMx channel 2 polarity.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_OCPolarity: specifies the OC2 Polarity
* This parmeter can be one of the following values:
* @arg TIM_OCPolarity_High: Output Compare active high
@ -1824,11 +1851,11 @@ void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
{
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
tmpccer = TIMx->CCER;
/* Set or Reset the CC2P Bit */
tmpccer &= CCER_CC2P_Reset;
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
/* Write to TIMx CCER register */
TIMx->CCER = tmpccer;
@ -1847,12 +1874,12 @@ void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
{
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST1_PERIPH(TIMx));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
tmpccer = TIMx->CCER;
/* Set or Reset the CC2NP Bit */
tmpccer &= CCER_CC2NP_Reset;
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
/* Write to TIMx CCER register */
TIMx->CCER = tmpccer;
@ -1871,11 +1898,11 @@ void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
{
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
tmpccer = TIMx->CCER;
/* Set or Reset the CC3P Bit */
tmpccer &= CCER_CC3P_Reset;
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
/* Write to TIMx CCER register */
TIMx->CCER = tmpccer;
@ -1895,12 +1922,12 @@ void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST1_PERIPH(TIMx));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
tmpccer = TIMx->CCER;
/* Set or Reset the CC3NP Bit */
tmpccer &= CCER_CC3NP_Reset;
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
/* Write to TIMx CCER register */
TIMx->CCER = tmpccer;
@ -1919,11 +1946,11 @@ void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
{
uint16_t tmpccer = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
tmpccer = TIMx->CCER;
/* Set or Reset the CC4P Bit */
tmpccer &= CCER_CC4P_Reset;
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
/* Write to TIMx CCER register */
TIMx->CCER = tmpccer;
@ -1931,7 +1958,7 @@ void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_Channel: specifies the TIM Channel
* This parmeter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
@ -1947,7 +1974,7 @@ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
uint16_t tmp = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
assert_param(IS_TIM_CCX(TIM_CCx));
@ -1962,7 +1989,7 @@ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
* @param TIM_Channel: specifies the TIM Channel
* This parmeter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
@ -1977,7 +2004,7 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
uint16_t tmp = 0;
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
assert_param(IS_TIM_CCXN(TIM_CCxN));
@ -1995,7 +2022,7 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
* @note This function disables the selected channel before changing the Ouput
* Compare Mode.
* User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_Channel: specifies the TIM Channel
* This parmeter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
@ -2019,7 +2046,7 @@ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode
uint16_t tmp1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
assert_param(IS_TIM_OCM(TIM_OCMode));
@ -2036,7 +2063,7 @@ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode
tmp += (TIM_Channel>>1);
/* Reset the OCxM bits in the CCMRx register */
*(__IO uint32_t *) tmp &= CCMR_OC13M_Mask;
*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
/* Configure the OCxM bits in the CCMRx register */
*(__IO uint32_t *) tmp |= TIM_OCMode;
@ -2046,7 +2073,7 @@ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode
tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
/* Reset the OCxM bits in the CCMRx register */
*(__IO uint32_t *) tmp &= CCMR_OC24M_Mask;
*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
/* Configure the OCxM bits in the CCMRx register */
*(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
@ -2055,7 +2082,7 @@ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode
/**
* @brief Enables or Disables the TIMx Update event.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param NewState: new state of the TIMx UDIS bit
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -2068,18 +2095,18 @@ void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
if (NewState != DISABLE)
{
/* Set the Update Disable Bit */
TIMx->CR1 |= CR1_UDIS_Set;
TIMx->CR1 |= TIM_CR1_UDIS;
}
else
{
/* Reset the Update Disable Bit */
TIMx->CR1 &= CR1_UDIS_Reset;
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
}
}
/**
* @brief Configures the TIMx Update Request Interrupt source.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_UpdateSource: specifies the Update source.
* This parameter can be one of the following values:
* @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
@ -2096,12 +2123,12 @@ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
if (TIM_UpdateSource != TIM_UpdateSource_Global)
{
/* Set the URS Bit */
TIMx->CR1 |= CR1_URS_Set;
TIMx->CR1 |= TIM_CR1_URS;
}
else
{
/* Reset the URS Bit */
TIMx->CR1 &= CR1_URS_Reset;
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
}
}
@ -2115,23 +2142,23 @@ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Set the TI1S Bit */
TIMx->CR2 |= CR2_TI1S_Set;
TIMx->CR2 |= TIM_CR2_TI1S;
}
else
{
/* Reset the TI1S Bit */
TIMx->CR2 &= CR2_TI1S_Reset;
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
}
}
/**
* @brief Selects the TIMx’s One Pulse Mode.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_OPMode: specifies the OPM Mode to be used.
* This parameter can be one of the following values:
* @arg TIM_OPMode_Single
@ -2144,14 +2171,14 @@ void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
assert_param(IS_TIM_ALL_PERIPH(TIMx));
assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
/* Reset the OPM Bit */
TIMx->CR1 &= CR1_OPM_Reset;
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
/* Configure the OPM Mode */
TIMx->CR1 |= TIM_OPMode;
}
/**
* @brief Selects the TIMx Trigger Output Mode.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_TRGOSource: specifies the Trigger Output source.
* This paramter can be one of the following values:
*
@ -2173,17 +2200,17 @@ void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
assert_param(IS_TIM_LIST7_PERIPH(TIMx));
assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
/* Reset the MMS Bits */
TIMx->CR2 &= CR2_MMS_Mask;
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
/* Select the TRGO source */
TIMx->CR2 |= TIM_TRGOSource;
}
/**
* @brief Selects the TIMx Slave Mode.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_SlaveMode: specifies the Timer Slave Mode.
* This paramter can be one of the following values:
* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
@ -2196,17 +2223,17 @@ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
/* Reset the SMS Bits */
TIMx->SMCR &= SMCR_SMS_Mask;
/* Reset the SMS Bits */
TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
/* Select the Slave Mode */
TIMx->SMCR |= TIM_SlaveMode;
}
/**
* @brief Sets or Resets the TIMx Master/Slave Mode.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
* This paramter can be one of the following values:
* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
@ -2217,10 +2244,10 @@ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
/* Reset the MSM Bit */
TIMx->SMCR &= SMCR_MSM_Reset;
TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
/* Set or Reset the MSM Bit */
TIMx->SMCR |= TIM_MasterSlaveMode;
@ -2228,7 +2255,7 @@ void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
/**
* @brief Sets the TIMx Counter Register value
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param Counter: specifies the Counter register new value.
* @retval None
*/
@ -2242,7 +2269,7 @@ void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
/**
* @brief Sets the TIMx Autoreload Register value
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param Autoreload: specifies the Autoreload register new value.
* @retval None
*/
@ -2256,28 +2283,28 @@ void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
/**
* @brief Sets the TIMx Capture Compare1 Register value
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param Compare1: specifies the Capture Compare1 register new value.
* @retval None
*/
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
/* Set the Capture Compare1 Register value */
TIMx->CCR1 = Compare1;
}
/**
* @brief Sets the TIMx Capture Compare2 Register value
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param Compare2: specifies the Capture Compare2 register new value.
* @retval None
*/
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
/* Set the Capture Compare2 Register value */
TIMx->CCR2 = Compare2;
}
@ -2291,7 +2318,7 @@ void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
/* Set the Capture Compare3 Register value */
TIMx->CCR3 = Compare3;
}
@ -2305,14 +2332,14 @@ void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
/* Set the Capture Compare4 Register value */
TIMx->CCR4 = Compare4;
}
/**
* @brief Sets the TIMx Input Capture 1 prescaler.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
* This parameter can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
@ -2324,17 +2351,17 @@ void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
/* Reset the IC1PSC Bits */
TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
/* Set the IC1PSC value */
TIMx->CCMR1 |= TIM_ICPSC;
}
/**
* @brief Sets the TIMx Input Capture 2 prescaler.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
* This parameter can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
@ -2346,10 +2373,10 @@ void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
/* Reset the IC2PSC Bits */
TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
/* Set the IC2PSC value */
TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
}
@ -2368,10 +2395,10 @@ void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
/* Reset the IC3PSC Bits */
TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
/* Set the IC3PSC value */
TIMx->CCMR2 |= TIM_ICPSC;
}
@ -2390,17 +2417,18 @@ void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
/* Reset the IC4PSC Bits */
TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
/* Set the IC4PSC value */
TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
}
/**
* @brief Sets the TIMx Clock Division value.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select
* the TIM peripheral.
* @param TIM_CKD: specifies the clock division value.
* This parameter can be one of the following value:
* @arg TIM_CKD_DIV1: TDTS = Tck_tim
@ -2411,36 +2439,36 @@ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
assert_param(IS_TIM_CKD_DIV(TIM_CKD));
/* Reset the CKD Bits */
TIMx->CR1 &= CR1_CKD_Mask;
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
/* Set the CKD value */
TIMx->CR1 |= TIM_CKD;
}
/**
* @brief Gets the TIMx Input Capture 1 value.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @retval Capture Compare 1 Register value.
*/
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
/* Get the Capture 1 Register value */
return TIMx->CCR1;
}
/**
* @brief Gets the TIMx Input Capture 2 value.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @retval Capture Compare 2 Register value.
*/
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
/* Get the Capture 2 Register value */
return TIMx->CCR2;
}
@ -2453,7 +2481,7 @@ uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
/* Get the Capture 3 Register value */
return TIMx->CCR3;
}
@ -2466,14 +2494,14 @@ uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
/* Get the Capture 4 Register value */
return TIMx->CCR4;
}
/**
* @brief Gets the TIMx Counter value.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @retval Counter Register value.
*/
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
@ -2486,7 +2514,7 @@ uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
/**
* @brief Gets the TIMx Prescaler value.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @retval Prescaler Register value.
*/
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
@ -2499,7 +2527,7 @@ uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
/**
* @brief Checks whether the specified TIM flag is set or not.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg TIM_FLAG_Update: TIM update Flag
@ -2516,7 +2544,11 @@ uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
* @note
* - TIM6 and TIM7 can have only one update flag.
* - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
* @retval The new state of TIM_FLAG (SET or RESET).
*/
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
@ -2539,7 +2571,7 @@ FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
/**
* @brief Clears the TIMx's pending flags.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_FLAG: specifies the flag bit to clear.
* This parameter can be any combination of the following values:
* @arg TIM_FLAG_Update: TIM update Flag
@ -2556,7 +2588,11 @@ FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
* @note
* - TIM6 and TIM7 can have only one update flag.
* - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
* @retval None
*/
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
@ -2571,7 +2607,7 @@ void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
/**
* @brief Checks whether the TIM interrupt has occurred or not.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_IT: specifies the TIM interrupt source to check.
* This parameter can be one of the following values:
* @arg TIM_IT_Update: TIM update Interrupt source
@ -2584,7 +2620,11 @@ void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
* @arg TIM_IT_Break: TIM Break Interrupt source
* @note
* - TIM6 and TIM7 can generate only an update interrupt.
* - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
* TIM_IT_CC2 or TIM_IT_Trigger.
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
* @retval The new state of the TIM_IT(SET or RESET).
*/
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
@ -2611,7 +2651,7 @@ ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
/**
* @brief Clears the TIMx's interrupt pending bits.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_IT: specifies the pending bit to clear.
* This parameter can be any combination of the following values:
* @arg TIM_IT_Update: TIM1 update Interrupt source
@ -2624,7 +2664,11 @@ ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
* @arg TIM_IT_Break: TIM Break Interrupt source
* @note
* - TIM6 and TIM7 can generate only an update interrupt.
* - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
* TIM_IT_CC2 or TIM_IT_Trigger.
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
* @retval None
*/
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
@ -2638,7 +2682,7 @@ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
/**
* @brief Configure the TI1 as Input.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
@ -2657,15 +2701,27 @@ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
{
uint16_t tmpccmr1 = 0, tmpccer = 0;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= CCER_CC1E_Reset;
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
/* Select the Input and set the filter */
tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
/* Select the Polarity and set the CC1E Bit */
tmpccer &= CCER_CC1P_Reset;
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set);
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
(TIMx == TIM4) ||(TIMx == TIM5))
{
/* Select the Polarity and set the CC1E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
}
else
{
/* Select the Polarity and set the CC1E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
}
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
TIMx->CCER = tmpccer;
@ -2673,7 +2729,7 @@ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
/**
* @brief Configure the TI2 as Input.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
@ -2692,17 +2748,29 @@ static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
{
uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= CCER_CC2E_Reset;
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
tmp = (uint16_t)(TIM_ICPolarity << 4);
/* Select the Input and set the filter */
tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= CCER_CC2P_Reset;
tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set);
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
(TIMx == TIM4) ||(TIMx == TIM5))
{
/* Select the Polarity and set the CC2E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
}
else
{
/* Select the Polarity and set the CC2E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
}
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
TIMx->CCER = tmpccer;
@ -2729,23 +2797,35 @@ static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
{
uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
/* Disable the Channel 3: Reset the CC3E Bit */
TIMx->CCER &= CCER_CC3E_Reset;
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
tmpccmr2 = TIMx->CCMR2;
tmpccer = TIMx->CCER;
tmp = (uint16_t)(TIM_ICPolarity << 8);
/* Select the Input and set the filter */
tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
/* Select the Polarity and set the CC3E Bit */
tmpccer &= CCER_CC3P_Reset;
tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set);
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
(TIMx == TIM4) ||(TIMx == TIM5))
{
/* Select the Polarity and set the CC3E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
}
else
{
/* Select the Polarity and set the CC3E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
}
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
TIMx->CCER = tmpccer;
}
/**
* @brief Configure the TI1 as Input.
* @brief Configure the TI4 as Input.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
@ -2765,23 +2845,32 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
{
uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= CCER_CC4E_Reset;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
tmpccmr2 = TIMx->CCMR2;
tmpccer = TIMx->CCER;
tmp = (uint16_t)(TIM_ICPolarity << 12);
/* Select the Input and set the filter */
tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
/* Select the Polarity and set the CC4E Bit */
tmpccer &= CCER_CC4P_Reset;
tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set);
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
(TIMx == TIM4) ||(TIMx == TIM5))
{
/* Select the Polarity and set the CC4E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
}
else
{
/* Select the Polarity and set the CC4E Bit */
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
}
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
TIMx->CCER = tmpccer ;
TIMx->CCER = tmpccer;
}
/**
@ -2796,4 +2885,4 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

112
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_usart.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the USART firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -79,6 +79,14 @@
#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
/* USART OverSampling-8 Mask */
#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */
#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */
/* USART One Bit Sampling Mask */
#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */
#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */
/**
* @}
*/
@ -162,7 +170,7 @@ void USART_DeInit(USART_TypeDef* USARTx)
* that contains the configuration information for the specified USART peripheral.
* @retval None
*/
void USART_Init(USART_TypeDef* USARTx, const USART_InitTypeDef* USART_InitStruct)
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
{
uint32_t tmpreg = 0x00, apbclock = 0x00;
uint32_t integerdivider = 0x00;
@ -230,12 +238,33 @@ void USART_Init(USART_TypeDef* USARTx, const USART_InitTypeDef* USART_InitStruct
{
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
}
/* Determine the integer part */
integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
tmpreg = (integerdivider / 0x64) << 0x04;
if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
{
/* Integer part computing in case Oversampling mode is 8 Samples */
integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
}
else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
{
/* Integer part computing in case Oversampling mode is 16 Samples */
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
}
tmpreg = (integerdivider / 100) << 4;
/* Determine the fractional part */
fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((uint8_t)0x0F);
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
/* Implement the fractional part in the register */
if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
{
tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
}
else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
{
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
}
/* Write to USART BRR */
USARTx->BRR = (uint16_t)tmpreg;
}
@ -402,20 +431,21 @@ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState Ne
* @brief Enables or disables the USART’s DMA interface.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3 or UART4.
* USART1, USART2, USART3, UART4 or UART5.
* @param USART_DMAReq: specifies the DMA request.
* This parameter can be any combination of the following values:
* @arg USART_DMAReq_Tx: USART DMA transmit request
* @arg USART_DMAReq_Rx: USART DMA receive request
* @param NewState: new state of the DMA Request sources.
* This parameter can be: ENABLE or DISABLE.
* @note The DMA mode is not available for UART5.
* @note The DMA mode is not available for UART5 except in the STM32
* High density value line devices(STM32F10X_HD_VL).
* @retval None
*/
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_USART_1234_PERIPH(USARTx));
assert_param(IS_USART_ALL_PERIPH(USARTx));
assert_param(IS_USART_DMAREQ(USART_DMAReq));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
@ -713,6 +743,64 @@ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
}
}
/**
* @brief Enables or disables the USART's 8x oversampling mode.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
* @param NewState: new state of the USART one bit sampling methode.
* This parameter can be: ENABLE or DISABLE.
* @note
* This function has to be called before calling USART_Init()
* function in order to have correct baudrate Divider value.
* @retval None
*/
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_USART_ALL_PERIPH(USARTx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
USARTx->CR1 |= CR1_OVER8_Set;
}
else
{
/* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
USARTx->CR1 &= CR1_OVER8_Reset;
}
}
/**
* @brief Enables or disables the USART's one bit sampling methode.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
* @param NewState: new state of the USART one bit sampling methode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_USART_ALL_PERIPH(USARTx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
USARTx->CR3 |= CR3_ONEBITE_Set;
}
else
{
/* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
USARTx->CR3 &= CR3_ONEBITE_Reset;
}
}
/**
* @brief Configures the USART’s IrDA interface.
* @param USARTx: Select the USART or the UART peripheral.
@ -964,4 +1052,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

8
flight/PiOS/STM32F10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c Normal file → Executable file
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_wwdg.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @version V3.4.0
* @date 10/15/2010
* @brief This file provides all the WWDG firmware functions.
******************************************************************************
* @copy
@ -15,7 +15,7 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
@ -220,4 +220,4 @@ void WWDG_ClearFlag(void)
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/