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OP-1682 - Fixes for review
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@ -249,7 +249,7 @@ static void PIOS_TIM_generic_irq_handler(TIM_TypeDef *timer)
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* get the order wrong, our pulse width calculations could be off by up
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* to ARR ticks. That could be bad.
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*
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* Heuristic: If the edge_count is < 16 ticks above zero then we assume the
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* Heuristic: If the edge_count is < 32 ticks above zero then we assume the
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* edge happened just after the overflow.
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*/
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@ -298,67 +298,6 @@ static void PIOS_TIM_generic_irq_handler(TIM_TypeDef *timer)
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}
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}
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}
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#if 0
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uint16_t val = 0;
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for (uint8_t i = 0; i < pios_pwm_cfg.num_channels; i++) {
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struct pios_pwm_channel channel = pios_pwm_cfg.channels[i];
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if ((channel.timer == timer) && (TIM_GetITStatus(channel.timer, channel.ccr) == SET)) {
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TIM_ClearITPendingBit(channel.timer, channel.ccr);
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switch (channel.channel) {
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case TIM_Channel_1:
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val = TIM_GetCapture1(channel.timer);
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break;
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case TIM_Channel_2:
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val = TIM_GetCapture2(channel.timer);
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break;
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case TIM_Channel_3:
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val = TIM_GetCapture3(channel.timer);
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break;
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case TIM_Channel_4:
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val = TIM_GetCapture4(channel.timer);
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break;
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}
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if (CaptureState[i] == 0) {
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RiseValue[i] = val;
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} else {
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FallValue[i] = val;
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}
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// flip state machine and capture value here
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/* Simple rise or fall state machine */
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TIM_ICInitTypeDef TIM_ICInitStructure = pios_pwm_cfg.tim_ic_init;
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if (CaptureState[i] == 0) {
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/* Switch states */
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CaptureState[i] = 1;
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/* Switch polarity of input capture */
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TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;
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TIM_ICInitStructure.TIM_Channel = channel.channel;
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TIM_ICInit(channel.timer, &TIM_ICInitStructure);
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} else {
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/* Capture computation */
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if (FallValue[i] > RiseValue[i]) {
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CaptureValue[i] = (FallValue[i] - RiseValue[i]);
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} else {
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CaptureValue[i] = ((channel.timer->ARR - RiseValue[i]) + FallValue[i]);
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}
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/* Switch states */
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CaptureState[i] = 0;
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/* Increase supervisor counter */
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CapCounter[i]++;
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/* Switch polarity of input capture */
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TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
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TIM_ICInitStructure.TIM_Channel = channel.channel;
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TIM_ICInit(channel.timer, &TIM_ICInitStructure);
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}
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}
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}
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#endif /* if 0 */
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/* Bind Interrupt Handlers
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*
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