rooty/LibrePilot
1
0
Fork 0
mirror of https://bitbucket.org/librepilot/librepilot.git synced 2024-12-01 09:24:10 +01:00
Code Issues Releases Activity

REVONANO - Fix Prescaler settings for APB1 and 2 (48MHz and 96MHz)

Browse Source
This commit is contained in:
Alessio Morale 2015-04-22 22:23:26 +02:00
parent 25b5278b05
commit 295ca38026
2 changed files with 15 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
flight/pios/stm32f4xx/libraries/CMSIS/Device/ST/STM32F4xx/Source/revonano/system_stm32f4xx.c
View File

@ -52,9 +52,9 @@
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
* APB1 Prescaler | 2
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 8000000
*-----------------------------------------------------------------------------
@ -179,7 +179,7 @@
* @{
*/
uint32_t SystemCoreClock = 84000000;
uint32_t SystemCoreClock = 96000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
@ -372,18 +372,17 @@ static void SetSysClock(void)
if (HSEStatus == (uint32_t)0x01)
{
/* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */
/* Select regulator voltage output Scale 1 mode, System frequency up to 144 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR &= (uint32_t)~(PWR_CR_VOS);
PWR->CR |= PWR_CR_VOS_0 | PWR_CR_VOS_1;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_HPRE) |RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK2 = HCLK / 1*/
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_PPRE2) |RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* PCLK1 = HCLK / 2*/
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_PPRE1) | RCC_CFGR_PPRE1_DIV2;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
@ -412,6 +411,8 @@ static void SetSysClock(void)
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
while(1){
}
}
}

6
flight/targets/boards/revonano/pios_board.h
View File

@ -203,8 +203,8 @@ extern uint32_t pios_packet_handler;
// TIM2,3,4,5,6,7,12,13,14
// Calculated as SYSCLK / APBPresc * (APBPre == 1 ? 1 : 2)
// Default APB1 Prescaler = 4
#define PIOS_PERIPHERAL_APB1_CLOCK (PIOS_SYSCLK / 2)
// Default APB1 Prescaler = 2
#define PIOS_PERIPHERAL_APB1_CLOCK PIOS_SYSCLK
// Peripherals belonging to APB2
// SDIO |EXTI |SYSCFG |SPI1
@ -212,7 +212,7 @@ extern uint32_t pios_packet_handler;
// USART1,6
// TIM1,8,9,10,11
//
// Default APB2 Prescaler = 2
// Default APB2 Prescaler = 1
//
#define PIOS_PERIPHERAL_APB2_CLOCK PIOS_SYSCLK