rooty/LibrePilot
1
0
Fork 0
mirror of https://bitbucket.org/librepilot/librepilot.git synced 2025-02-18 08:54:15 +01:00
Code Issues Releases Activity

OP-1275 support HSI oscillator, fix gpio, usart and sys (vector remapping not working yet)

Browse Source
This commit is contained in:
Alessio Morale 2014-05-27 18:51:44 +02:00
parent ff82d50ee0
commit 2ca1adafe5
5 changed files with 107 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/system_stm32f0xx.c
View File

@ -113,6 +113,10 @@
/** @addtogroup STM32F0xx_System_Private_Defines
* @{
*/
#define PLL_SOURCE_HSI // HSI (~8MHz) used to clock the PLL, and the PLL is used as system clock source
//#define PLL_SOURCE_HSE // HSE (8MHz) used to clock the PLL, and the PLL is used as system clock source
/**
* @}
*/
@ -283,12 +287,49 @@ void SystemCoreClockUpdate (void)
*/
static void SetSysClock(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
#if defined (PLL_SOURCE_HSI)
/* At this stage the HSI is already enabled */
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
/* PLL configuration = (HSI/2) * 12 = ~48 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
#else
#if defined (PLL_SOURCE_HSE)
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
#elif defined (PLL_SOURCE_HSE_BYPASS)
/* HSE oscillator bypassed with external clock */
RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP);
#endif /* PLL_SOURCE_HSE */
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Wait till HSE is ready and if Time out is reached exit */
do
{
@ -341,6 +382,7 @@ static void SetSysClock(void)
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
#endif /* PLL_SOURCE_HSI */
}
/**

2
flight/pios/stm32f0x/link_STM3205x_GPSP_sections.ld
View File

@ -1,5 +1,5 @@
/* This is the size of the stack for all FreeRTOS IRQs */
_irq_stack_size = 0x100;
_irq_stack_size = 0x150;
/* This is the size of the stack for early init: life span is until scheduler starts */
_init_stack_size = 0x100;

32
flight/pios/stm32f0x/pios_gpio.c
View File

@ -56,15 +56,6 @@ int32_t PIOS_GPIO_Init(uint32_t *gpios_dev_id, const struct pios_gpio_cfg *cfg)
case (uint32_t)GPIOC:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
break;
case (uint32_t)GPIOD:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
break;
case (uint32_t)GPIOE:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOE, ENABLE);
break;
case (uint32_t)GPIOF:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
break;
default:
PIOS_Assert(0);
break;
@ -100,9 +91,9 @@ void PIOS_GPIO_On(uint32_t gpios_dev_id, uint8_t gpio_id)
const struct pios_gpio *gpio = &(gpio_cfg->gpios[gpio_id]);
if (gpio->active_low) {
GPIO_ResetBits(gpio->pin.gpio, gpio->pin.init.GPIO_Pin);
gpio->pin.gpio->BRR = gpio->pin.init.GPIO_Pin;
} else {
GPIO_SetBits(gpio->pin.gpio, gpio->pin.init.GPIO_Pin);
gpio->pin.gpio->BSRR = gpio->pin.init.GPIO_Pin;
}
}
@ -124,9 +115,9 @@ void PIOS_GPIO_Off(uint32_t gpios_dev_id, uint8_t gpio_id)
const struct pios_gpio *gpio = &(gpio_cfg->gpios[gpio_id]);
if (gpio->active_low) {
GPIO_SetBits(gpio->pin.gpio, gpio->pin.init.GPIO_Pin);
gpio->pin.gpio->BSRR = gpio->pin.init.GPIO_Pin;
} else {
GPIO_ResetBits(gpio->pin.gpio, gpio->pin.init.GPIO_Pin);
gpio->pin.gpio->BRR = gpio->pin.init.GPIO_Pin;
}
}
@ -147,19 +138,12 @@ void PIOS_GPIO_Toggle(uint32_t gpios_dev_id, uint8_t gpio_id)
const struct pios_gpio *gpio = &(gpio_cfg->gpios[gpio_id]);
if (GPIO_ReadOutputDataBit(gpio->pin.gpio, gpio->pin.init.GPIO_Pin) == Bit_SET) {
if (gpio->active_low) {
PIOS_GPIO_On(gpios_dev_id, gpio_id);
} else {
PIOS_GPIO_Off(gpios_dev_id, gpio_id);
}
if (((gpio->pin.gpio->ODR & gpio->pin.init.GPIO_Pin) != 0) ^ gpio->active_low ) {
PIOS_GPIO_Off(gpios_dev_id, gpio_id);
} else {
if (gpio->active_low) {
PIOS_GPIO_Off(gpios_dev_id, gpio_id);
} else {
PIOS_GPIO_On(gpios_dev_id, gpio_id);
}
PIOS_GPIO_On(gpios_dev_id, gpio_id);
}
}
#endif /* PIOS_INCLUDE_GPIO */

91
flight/pios/stm32f0x/pios_sys.c
View File

@ -37,8 +37,7 @@ __IO uint32_t VectorTable[48] __attribute__((section(".ram_vector_table")));
/* Private Function Prototypes */
void NVIC_Configuration(void);
void SysTick_Handler(void);
void stopHandler();
/* Local Macros */
#define MEM8(addr) (*((volatile uint8_t *)(addr)))
#define MEM16(addr) (*((volatile uint16_t *)(addr)))
@ -73,57 +72,13 @@ void PIOS_SYS_Init(void)
RCC_AHBPeriphClockCmd(
RCC_AHBPeriph_GPIOA |
RCC_AHBPeriph_GPIOB |
// RCC_AHBPeriph_GPIOC |
// RCC_AHBPeriph_GPIOD |
// RCC_AHBPeriph_GPIOE |
// RCC_AHBPeriph_GPIOF |
// RCC_AHBPeriph_CRC |
RCC_AHBPeriph_FLITF |
RCC_AHBPeriph_SRAM |
RCC_AHBPeriph_DMA1
, ENABLE);
/*RCC_APB1PeriphClockCmd(
RCC_APB1Periph_TIM2 |
RCC_APB1Periph_TIM3 |
RCC_APB1Periph_TIM4 |
RCC_APB1Periph_TIM5 |
RCC_APB1Periph_TIM6 |
RCC_APB1Periph_TIM7 |
RCC_APB1Periph_TIM12 |
RCC_APB1Periph_TIM13 |
RCC_APB1Periph_TIM14 |
RCC_APB1Periph_WWDG |
RCC_APB1Periph_SPI2 |
RCC_APB1Periph_SPI3 |
RCC_APB1Periph_USART2 |
RCC_APB1Periph_USART3 |
RCC_APB1Periph_UART4 |
RCC_APB1Periph_UART5 |
RCC_APB1Periph_I2C1 |
RCC_APB1Periph_I2C2 |
RCC_APB1Periph_I2C3 |
RCC_APB1Periph_CAN1 |
RCC_APB1Periph_CAN2 |
RCC_APB1Periph_PWR |
RCC_APB1Periph_DAC |
0, ENABLE);
*/
RCC_APB2PeriphClockCmd(
// RCC_APB2Periph_TIM1 |
// RCC_APB2Periph_TIM8 |
// RCC_APB2Periph_USART1 |
// RCC_APB2Periph_USART6 |
// RCC_APB2Periph_ADC |
// RCC_APB2Periph_ADC1 |
// RCC_APB2Periph_ADC2 |
// RCC_APB2Periph_ADC3 |
// RCC_APB2Periph_SDIO |
// RCC_APB2Periph_SPI1 |
RCC_APB2Periph_SYSCFG |
// RCC_APB2Periph_TIM9 |
// RCC_APB2Periph_TIM10 |
// RCC_APB2Periph_TIM11 |
0, ENABLE);
/*
@ -177,8 +132,6 @@ int32_t PIOS_SYS_Reset(void)
PIOS_LED_Off(PIOS_LED_ALARM);
#endif /* PIOS_LED_ALARM */
/* XXX F10x port resets most (but not all) peripherals ... do we care? */
/* Reset STM32 */
NVIC_SystemReset();
@ -210,7 +163,7 @@ int32_t PIOS_SYS_SerialNumberGetBinary(uint8_t *array)
/* Stored in the so called "electronic signature" */
for (i = 0; i < PIOS_SYS_SERIAL_NUM_BINARY_LEN; ++i) {
uint8_t b = MEM8(0x1fff7a10 + i);
uint8_t b = MEM8(0x1FFFF7AC + i);
array[i] = b;
}
@ -231,7 +184,7 @@ int32_t PIOS_SYS_SerialNumberGet(char *str)
/* Stored in the so called "electronic signature" */
for (i = 0; i < PIOS_SYS_SERIAL_NUM_ASCII_LEN; ++i) {
uint8_t b = MEM8(0x1fff7a10 + (i / 2));
uint8_t b = MEM8(0x1FFFF7AC + (i / 2));
if (!(i & 1)) {
b >>= 4;
}
@ -251,13 +204,15 @@ int32_t PIOS_SYS_SerialNumberGet(char *str)
void NVIC_Configuration(void)
{
/* Relocate by software the vector table to the internal SRAM at 0x20000000 ***/
extern void *pios_isr_vector_table_base;
extern uint32_t pios_isr_vector_table_base;
uint32_t *romTable = &pios_isr_vector_table_base;
/* Copy the vector table from the Flash (mapped at the base of the application
load address 0x08003000) to the base address of the SRAM at 0x20000000. */
load address 0x0800X000) to the base address of the SRAM at 0x20000000. */
for(uint32_t i = 0; i < 48; i++)
{
VectorTable[i] = *(__IO uint32_t*)(pios_isr_vector_table_base + (i<<2));
VectorTable[i] = romTable[i];
}
/* Enable the SYSCFG peripheral clock*/
@ -305,6 +260,36 @@ void assert_failed(uint8_t *file, uint32_t line)
}
#endif /* ifdef USE_FULL_ASSERT */
void NMI_Handler(void)
{
stopHandler();
}
void HardFault_Handler(void)
{
stopHandler();
}
void MemManage_Handler(void)
{
stopHandler();
}
void BusFault_Handler(void)
{
stopHandler();
}
void UsageFault_Handler(void)
{
stopHandler();
}
void stopHandler(){
while (1)
{
}
}
#endif /* PIOS_INCLUDE_SYS */
/**

25
flight/pios/stm32f0x/pios_usart.c
View File

@ -153,12 +153,17 @@ int32_t PIOS_USART_Init(uint32_t *usart_id, const struct pios_usart_cfg *cfg)
/* Enable the USART Pins Software Remapping */
if (usart_dev->cfg->remap) {
GPIO_PinRemapConfig(usart_dev->cfg->remap, ENABLE);
GPIO_PinAFConfig(usart_dev->cfg->rx.gpio,
__builtin_ctz(usart_dev->cfg->rx.init.GPIO_Pin),
usart_dev->cfg->remap);
GPIO_PinAFConfig(usart_dev->cfg->tx.gpio,
__builtin_ctz(usart_dev->cfg->tx.init.GPIO_Pin),
usart_dev->cfg->remap);
}
/* Initialize the USART Rx and Tx pins */
GPIO_Init(usart_dev->cfg->rx.gpio, &usart_dev->cfg->rx.init);
GPIO_Init(usart_dev->cfg->tx.gpio, &usart_dev->cfg->tx.init);
GPIO_Init(usart_dev->cfg->rx.gpio, (GPIO_InitTypeDef*)&usart_dev->cfg->rx.init);
GPIO_Init(usart_dev->cfg->tx.gpio, (GPIO_InitTypeDef*)&usart_dev->cfg->tx.init);
/* Enable USART clock */
switch ((uint32_t)usart_dev->cfg->regs) {
@ -174,7 +179,7 @@ int32_t PIOS_USART_Init(uint32_t *usart_id, const struct pios_usart_cfg *cfg)
}
/* Configure the USART */
USART_Init(usart_dev->cfg->regs, &usart_dev->cfg->init);
USART_Init(usart_dev->cfg->regs, (USART_InitTypeDef*)&usart_dev->cfg->init);
*usart_id = (uint32_t)usart_dev;
@ -190,7 +195,7 @@ int32_t PIOS_USART_Init(uint32_t *usart_id, const struct pios_usart_cfg *cfg)
PIOS_USART_3_id = (uint32_t)usart_dev;
break;
}
NVIC_Init(&usart_dev->cfg->irq.init);
NVIC_Init((NVIC_InitTypeDef*)&usart_dev->cfg->irq.init);
USART_ITConfig(usart_dev->cfg->regs, USART_IT_RXNE, ENABLE);
USART_ITConfig(usart_dev->cfg->regs, USART_IT_TXE, ENABLE);
@ -290,12 +295,12 @@ static void PIOS_USART_generic_irq_handler(uint32_t usart_id)
PIOS_Assert(valid);
/* Force read of dr after sr to make sure to clear error flags */
volatile uint16_t sr = usart_dev->cfg->regs->SR;
volatile uint8_t dr = usart_dev->cfg->regs->DR;
volatile uint16_t sr = usart_dev->cfg->regs->ISR;
volatile uint8_t dr = usart_dev->cfg->regs->RDR;
/* Check if RXNE flag is set */
bool rx_need_yield = false;
if (sr & USART_SR_RXNE) {
if (sr & USART_ISR_RXNE) {
uint8_t byte = dr;
if (usart_dev->rx_in_cb) {
uint16_t rc;
@ -309,7 +314,7 @@ static void PIOS_USART_generic_irq_handler(uint32_t usart_id)
/* Check if TXE flag is set */
bool tx_need_yield = false;
if (sr & USART_SR_TXE) {
if (sr & USART_ISR_TXE) {
if (usart_dev->tx_out_cb) {
uint8_t b;
uint16_t bytes_to_send;
@ -318,7 +323,7 @@ static void PIOS_USART_generic_irq_handler(uint32_t usart_id)
if (bytes_to_send > 0) {
/* Send the byte we've been given */
usart_dev->cfg->regs->DR = b;
usart_dev->cfg->regs->TDR = b;
} else {
/* No bytes to send, disable TXE interrupt */
USART_ITConfig(usart_dev->cfg->regs, USART_IT_TXE, DISABLE);