diff --git a/Makefile b/Makefile index 7ae15391d..1bfdd4269 100644 --- a/Makefile +++ b/Makefile @@ -197,7 +197,7 @@ export OPUAVSYNTHDIR := $(BUILD_DIR)/uavobject-synthetics/flight export OPGCSSYNTHDIR := $(BUILD_DIR)/openpilotgcs-synthetics # Define supported board lists -ALL_BOARDS := coptercontrol oplinkmini revolution osd revoproto simposix discoveryf4bare +ALL_BOARDS := coptercontrol oplinkmini revolution osd revoproto simposix discoveryf4bare gpsplatinum # Short names of each board (used to display board name in parallel builds) coptercontrol_short := 'cc ' @@ -207,6 +207,7 @@ osd_short := 'osd ' revoproto_short := 'revp' simposix_short := 'posx' discoveryf4bare_short := 'df4b' +gpsplatinum_short := 'gps9 ' # SimPosix only builds on Linux so drop it from the list for # all other platforms. @@ -223,7 +224,7 @@ EF_BOARDS := $(ALL_BOARDS) # SimPosix doesn't have a BL, BU or EF target so we need to # filter them out to prevent errors on the all_flight target. BL_BOARDS := $(filter-out simposix, $(BL_BOARDS)) -BU_BOARDS := $(filter-out simposix, $(BU_BOARDS)) +BU_BOARDS := $(filter-out simposix gpsplatinum, $(BU_BOARDS)) EF_BOARDS := $(filter-out simposix, $(EF_BOARDS)) # Generate the targets for whatever boards are left in each list @@ -438,7 +439,7 @@ sim_osx_%: uavobjects_flight ############################## .PHONY: all_ground -all_ground: openpilotgcs +all_ground: openpilotgcs uploader # Convenience target for the GCS .PHONY: gcs gcs_clean @@ -478,6 +479,40 @@ openpilotgcs_clean: @$(ECHO) " CLEAN $(call toprel, $(BUILD_DIR)/openpilotgcs_$(GCS_BUILD_CONF))" $(V1) [ ! -d "$(BUILD_DIR)/openpilotgcs_$(GCS_BUILD_CONF)" ] || $(RM) -r "$(BUILD_DIR)/openpilotgcs_$(GCS_BUILD_CONF)" +################################ +# +# Serial Uploader tool +# +################################ + +.NOTPARALLEL: +.PHONY: uploader +uploader: uploader_qmake uploader_make + +.PHONY: uploader_qmake +uploader_qmake: +ifeq ($(QMAKE_SKIP),) + $(V1) $(MKDIR) -p $(BUILD_DIR)/uploader_$(GCS_BUILD_CONF) + $(V1) ( cd $(BUILD_DIR)/uploader_$(GCS_BUILD_CONF) && \ + $(QMAKE) $(ROOT_DIR)/ground/openpilotgcs/src/experimental/USB_UPLOAD_TOOL/upload.pro -spec $(QT_SPEC) -r CONFIG+="$(GCS_BUILD_CONF) $(GCS_SILENT)" $(GCS_QMAKE_OPTS) \ + ) +else + @$(ECHO) "skipping qmake" +endif + +.PHONY: uploader_make +uploader_make: + $(V1) $(MKDIR) -p $(BUILD_DIR)/uploader_$(GCS_BUILD_CONF) + $(V1) ( cd $(BUILD_DIR)/uploader_$(GCS_BUILD_CONF)/$(MAKE_DIR) && \ + $(MAKE) -w ; \ + ) + +.PHONY: uploader_clean +uploader_clean: + @$(ECHO) " CLEAN $(call toprel, $(BUILD_DIR)/uploader_$(GCS_BUILD_CONF))" + $(V1) [ ! -d "$(BUILD_DIR)/uploader_$(GCS_BUILD_CONF)" ] || $(RM) -r "$(BUILD_DIR)/uploader_$(GCS_BUILD_CONF)" + + ################################ # # Android GCS related components @@ -972,6 +1007,14 @@ help: @$(ECHO) " gcs_clean - Remove the Ground Control System (GCS) application (debug|release)" @$(ECHO) " Supported build configurations: GCS_BUILD_CONF=debug|release (default is $(GCS_BUILD_CONF))" @$(ECHO) + @$(ECHO) " [Uploader Tool]" + @$(ECHO) " uploader - Build the serial uploader tool (debug|release)" + @$(ECHO) " Skip qmake: QMAKE_SKIP=1" + @$(ECHO) " Example: make uploader QMAKE_SKIP=1" + @$(ECHO) " uploader_clean - Remove the serial uploader tool (debug|release)" + @$(ECHO) " Supported build configurations: GCS_BUILD_CONF=debug|release (default is $(GCS_BUILD_CONF))" + @$(ECHO) + @$(ECHO) @$(ECHO) " [AndroidGCS]" @$(ECHO) " androidgcs - Build the Android Ground Control System (GCS) application" @$(ECHO) " androidgcs_install - Use ADB to install the Android GCS application" diff --git a/flight/libraries/fifo_buffer.c b/flight/libraries/fifo_buffer.c index 396ee6ec7..be04d927f 100644 --- a/flight/libraries/fifo_buffer.c +++ b/flight/libraries/fifo_buffer.c @@ -148,14 +148,18 @@ uint16_t fifoBuf_getDataPeek(t_fifo_buffer *buf, void *data, uint16_t len) uint16_t i = 0; while (num_bytes > 0) { - uint16_t j = buf_size - rd; - if (j > num_bytes) { - j = num_bytes; + uint16_t block_len = buf_size - rd; + if (block_len > num_bytes) { + block_len = num_bytes; } - memcpy(p + i, buff + rd, j); - i += j; - num_bytes -= j; - rd += j; + if (block_len == 1) { + *((uint8_t *)(p + i)) = *((uint8_t *)(buff + rd)); + } else { + memcpy(p + i, buff + rd, block_len); + } + i += block_len; + num_bytes -= block_len; + rd += block_len; if (rd >= buf_size) { rd = 0; } @@ -184,14 +188,18 @@ uint16_t fifoBuf_getData(t_fifo_buffer *buf, void *data, uint16_t len) uint16_t i = 0; while (num_bytes > 0) { - uint16_t j = buf_size - rd; - if (j > num_bytes) { - j = num_bytes; + uint16_t block_len = buf_size - rd; + if (block_len > num_bytes) { + block_len = num_bytes; } - memcpy(p + i, buff + rd, j); - i += j; - num_bytes -= j; - rd += j; + if (block_len == 1) { + *((uint8_t *)(p + i)) = *((uint8_t *)(buff + rd)); + } else { + memcpy(p + i, buff + rd, block_len); + } + i += block_len; + num_bytes -= block_len; + rd += block_len; if (rd >= buf_size) { rd = 0; } @@ -243,14 +251,18 @@ uint16_t fifoBuf_putData(t_fifo_buffer *buf, const void *data, uint16_t len) uint16_t i = 0; while (num_bytes > 0) { - uint16_t j = buf_size - wr; - if (j > num_bytes) { - j = num_bytes; + uint16_t block_len = buf_size - wr; + if (block_len > num_bytes) { + block_len = num_bytes; } - memcpy(buff + wr, p + i, j); - i += j; - num_bytes -= j; - wr += j; + if (block_len == 1) { + *((uint8_t *)(buff + wr)) = *((uint8_t *)(p + i)); + } else { + memcpy(buff + wr, p + i, block_len); + } + i += block_len; + num_bytes -= block_len; + wr += block_len; if (wr >= buf_size) { wr = 0; } diff --git a/flight/libraries/inc/op_dfu.h b/flight/libraries/inc/op_dfu.h index 356e6827c..386609ae4 100644 --- a/flight/libraries/inc/op_dfu.h +++ b/flight/libraries/inc/op_dfu.h @@ -50,11 +50,8 @@ typedef struct { /* Exported functions ------------------------------------------------------- */ void processComand(uint8_t *Receive_Buffer); -uint32_t baseOfAdressType(uint8_t type); -uint8_t isBiggerThanAvailable(uint8_t type, uint32_t size); -void OPDfuIni(uint8_t discover); void DataDownload(DownloadAction); -bool flash_read(uint8_t *buffer, uint32_t adr, DFUProgType type); + #endif /* __OP_DFU_H */ /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/flight/libraries/inc/ssp.h b/flight/libraries/inc/ssp.h new file mode 100644 index 000000000..423892588 --- /dev/null +++ b/flight/libraries/inc/ssp.h @@ -0,0 +1,118 @@ +/******************************************************************* +* +* NAME: ssp.h +* +* +*******************************************************************/ +#ifndef SSP_H +#define SSP_H +/** INCLUDE FILES **/ +#include + +/** LOCAL DEFINITIONS **/ +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#define SPP_USES_CRC + +#define SSP_TX_IDLE 0 // not expecting a ACK packet (no current transmissions in progress) +#define SSP_TX_WAITING 1 // waiting for a valid ACK to arrive +#define SSP_TX_TIMEOUT 2 // failed to receive a valid ACK in the timeout period, after retrying. +#define SSP_TX_ACKED 3 // valid ACK received before timeout period. +#define SSP_TX_BUFOVERRUN 4 // amount of data to send execeds the transmission buffer sizeof +#define SSP_TX_BUSY 5 // Attempted to start a transmission while a transmission was already in progress. +// #define SSP_TX_FAIL - failure... + +#define SSP_RX_IDLE 0 +#define SSP_RX_RECEIVING 1 +#define SSP_RX_COMPLETE 2 + +// types of packet that can be received +#define SSP_RX_DATA 5 +#define SSP_RX_ACK 6 +#define SSP_RX_SYNCH 7 + +typedef enum decodeState_ { + decode_len1_e = 0, + decode_seqNo_e, + decode_data_e, + decode_crc1_e, + decode_crc2_e, + decode_idle_e +} DecodeState_t; + +typedef enum ReceiveState { + state_escaped_e = 0, state_unescaped_e +} ReceiveState_t; + +typedef struct { + uint8_t *pbuff; + uint16_t length; + uint16_t crc; + uint8_t seqNo; +} Packet_t; + +typedef struct { + uint8_t *rxBuf; // Buffer used to store rcv data + uint16_t rxBufSize; // rcv buffer size. + uint8_t *txBuf; // Length of data in buffer + uint16_t txBufSize; // CRC for data in Packet buff + uint16_t max_retry; // Maximum number of retrys for a single transmit. + int32_t timeoutLen; // how long to wait for each retry to succeed + void (*pfCallBack)(uint8_t *, uint16_t); // call back function that is called when a full packet has been received + int16_t (*pfSerialRead)(void); // function to call to read a byte from serial hardware + void (*pfSerialWrite)(uint8_t); // function used to write a byte to serial hardware for transmission + uint32_t (*pfGetTime)(void); // function returns time in number of seconds that has elapsed from a given reference point +} PortConfig_t; + +typedef struct Port_tag { + void (*pfCallBack)(uint8_t *, uint16_t); // call back function that is called when a full packet has been received + int16_t (*pfSerialRead)(void); // function to read a character from the serial input stream + void (*pfSerialWrite)(uint8_t); // function to write a byte to be sent out the serial port + uint32_t (*pfGetTime)(void); // function returns time in number of seconds that has elapsed from a given reference point + uint8_t retryCount; // how many times have we tried to transmit the 'send' packet + uint8_t maxRetryCount; // max. times to try to transmit the 'send' packet + int32_t timeoutLen; // how long to wait for each retry to succeed + uint32_t timeout; // current timeout. when 'time' reaches this point we have timed out + uint8_t txSeqNo; // current 'send' packet sequence number + uint16_t rxBufPos; // current buffer position in the receive packet + uint16_t rxBufLen; // number of 'data' bytes in the buffer + uint8_t rxSeqNo; // current 'receive' packet number + uint16_t rxBufSize; // size of the receive buffer. + uint16_t txBufSize; // size of the transmit buffer. + uint8_t *txBuf; // transmit buffer. REquired to store a copy of packet data in case a retry is needed. + uint8_t *rxBuf; // receive buffer. Used to store data as a packet is received. + uint16_t sendSynch; // flag to indicate that we should send a synchronize packet to the host + // this is required when switching from the application to the bootloader + // and vice-versa. This fixes the firwmare download timeout. + // when this flag is set to true, the next time we send a packet we will first + // send a synchronize packet. + ReceiveState_t InputState; + DecodeState_t DecodeState; + uint16_t SendState; + uint16_t crc; + uint32_t RxError; + uint32_t TxError; + uint16_t flags; +} Port_t; + +/** Public Data **/ + +/** PUBLIC FUNCTIONS **/ +int16_t ssp_ReceiveProcess(Port_t *thisport); +int16_t ssp_SendProcess(Port_t *thisport); +uint16_t ssp_SendString(Port_t *thisport, char *str); +int16_t ssp_SendData(Port_t *thisport, const uint8_t *data, + const uint16_t length); +void ssp_Init(Port_t *thisport, const PortConfig_t *const info); +int16_t ssp_ReceiveByte(Port_t *thisport); +uint16_t ssp_Synchronise(Port_t *thisport); + +/** EXTERNAL FUNCTIONS **/ + +#endif // ifndef SSP_H diff --git a/flight/libraries/inc/stopwatch.h b/flight/libraries/inc/stopwatch.h index 26922dff6..b339c8767 100644 --- a/flight/libraries/inc/stopwatch.h +++ b/flight/libraries/inc/stopwatch.h @@ -1,11 +1,11 @@ /** ****************************************************************************** - * @addtogroup CopterControlBL CopterControl BootLoader - * @brief These files contain the code to the CopterControl Bootloader. + * @addtogroup OpenPilot library + * @brief These files contain the code for stopwatch handling. * * @file stopwatch.h - * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010. - * @brief Timer functions for the LED PWM. + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief Generic pios_delay based stopwatch functions. * @see The GNU Public License (GPL) Version 3 * *****************************************************************************/ @@ -27,7 +27,8 @@ #ifndef _STOPWATCH_H #define _STOPWATCH_H - +#include +#include ///////////////////////////////////////////////////////////////////////////// // Global definitions ///////////////////////////////////////////////////////////////////////////// @@ -36,15 +37,46 @@ ///////////////////////////////////////////////////////////////////////////// // Global Types ///////////////////////////////////////////////////////////////////////////// - +typedef struct { + uint32_t raw; + uint32_t resolution; +} stopwatch_t; ///////////////////////////////////////////////////////////////////////////// // Prototypes ///////////////////////////////////////////////////////////////////////////// -extern s32 STOPWATCH_Init(u32 resolution, TIM_TypeDef *TIM); -extern s32 STOPWATCH_Reset(TIM_TypeDef *TIM); -extern u32 STOPWATCH_ValueGet(TIM_TypeDef *TIM); + +inline int32_t STOPWATCH_Init(uint32_t resolution, stopwatch_t *stopwatch) +{ + stopwatch->raw = PIOS_DELAY_GetRaw(); + stopwatch->resolution = resolution; + return 0; // no error +} + +///////////////////////////////////////////////////////////////////////////// +// ! Resets the stopwatch +// ! \return < 0 on errors +///////////////////////////////////////////////////////////////////////////// +inline int32_t STOPWATCH_Reset(stopwatch_t *stopwatch) +{ + stopwatch->raw = PIOS_DELAY_GetRaw(); + return 0; // no error +} + +///////////////////////////////////////////////////////////////////////////// +// ! Returns current value of stopwatch +// ! \return stopwatch value +///////////////////////////////////////////////////////////////////////////// +inline uint32_t STOPWATCH_ValueGet(stopwatch_t *stopwatch) +{ + uint32_t value = PIOS_DELAY_GetuSSince(stopwatch->raw); + + if (stopwatch > 1) { + value = value / stopwatch->resolution; + } + return value; +} ///////////////////////////////////////////////////////////////////////////// diff --git a/flight/libraries/inc/ubx_utils.h b/flight/libraries/inc/ubx_utils.h new file mode 100644 index 000000000..425b4a070 --- /dev/null +++ b/flight/libraries/inc/ubx_utils.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * + * @file ubx_utils.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief UBX Protocol utilities + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef UBX_UTILS_H_ +#define UBX_UTILS_H_ + +#include +#include + +typedef struct { + uint8_t syn1; + uint8_t syn2; + uint8_t class; + uint8_t id; + uint16_t len; +} __attribute__((packed)) UBXHeader_t; + +typedef struct { + uint8_t chk1; + uint8_t chk2; +} __attribute__((packed)) UBXFooter_t; + +typedef union { + uint8_t binarystream[0]; + struct { + UBXHeader_t header; + uint8_t payload[0]; + } packet; +} UBXPacket_t; + +#define UBX_HEADER_LEN (sizeof(UBXHeader_t)) + +#define UBX_SYN1 0xB5 +#define UBX_SYN2 0x62 + +bool ubx_getLastSentence(uint8_t *data, uint16_t bufferCount, uint8_t * *lastSentence, uint16_t *lenght); +void ubx_appendChecksum(UBXPacket_t *pkt); +void ubx_buildPacket(UBXPacket_t *pkt, uint8_t packetClass, uint8_t packetId, uint16_t len); + +#endif /* UBX_UTILS_H_ */ diff --git a/flight/libraries/op_dfu.c b/flight/libraries/op_dfu.c index e952a886c..d10b351e6 100644 --- a/flight/libraries/op_dfu.c +++ b/flight/libraries/op_dfu.c @@ -31,7 +31,6 @@ #include #include "op_dfu.h" #include "pios_bl_helper.h" -#include "pios_com_msg.h" #include // programmable devices Device devicesTable[10]; @@ -71,7 +70,12 @@ DFUTransfer downType = 0; /* Extern variables ----------------------------------------------------------*/ extern DFUStates DeviceState; extern uint8_t JumpToApp; +extern int32_t platform_senddata(const uint8_t *msg, uint16_t msg_len); /* Private function prototypes -----------------------------------------------*/ +static uint32_t baseOfAdressType(uint8_t type); +static uint8_t isBiggerThanAvailable(uint8_t type, uint32_t size); +static void OPDfuIni(uint8_t discover); +bool flash_read(uint8_t *buffer, uint32_t adr, DFUProgType type); /* Private functions ---------------------------------------------------------*/ void sendData(uint8_t *buf, uint16_t size); uint32_t CalcFirmCRC(void); @@ -109,35 +113,40 @@ void DataDownload(__attribute__((unused)) DownloadAction action) sendData(SendBuffer + 1, 63); } } + +static uint32_t unpack_uint32(uint8_t *buffer) +{ + uint32_t ret = buffer[0] << 24; + + ret += buffer[1] << 16; + ret += buffer[2] << 8; + ret += buffer[3]; + return ret; +} + +static void pack_uint32(uint32_t value, uint8_t *buffer) +{ + buffer[0] = value >> 24; + buffer[1] = value >> 16; + buffer[2] = value >> 8; + buffer[3] = value; +} + + void processComand(uint8_t *xReceive_Buffer) { - Command = xReceive_Buffer[COMMAND]; -#ifdef DEBUG_SSP - char str[63] = { 0 }; - sprintf(str, "Received COMMAND:%d|", Command); - PIOS_COM_SendString(PIOS_COM_TELEM_USB, str); -#endif + Command = xReceive_Buffer[COMMAND]; EchoReqFlag = (Command >> 7); EchoAnsFlag = (Command >> 6) & 0x01; StartFlag = (Command >> 5) & 0x01; - Count = xReceive_Buffer[COUNT] << 24; - Count += xReceive_Buffer[COUNT + 1] << 16; - Count += xReceive_Buffer[COUNT + 2] << 8; - Count += xReceive_Buffer[COUNT + 3]; - - Data = xReceive_Buffer[DATA] << 24; - Data += xReceive_Buffer[DATA + 1] << 16; - Data += xReceive_Buffer[DATA + 2] << 8; - Data += xReceive_Buffer[DATA + 3]; - Data0 = xReceive_Buffer[DATA]; - Data1 = xReceive_Buffer[DATA + 1]; - Data2 = xReceive_Buffer[DATA + 2]; - Data3 = xReceive_Buffer[DATA + 3]; + Count = unpack_uint32(&xReceive_Buffer[COUNT]); + Data = unpack_uint32(&xReceive_Buffer[DATA]); + Data0 = xReceive_Buffer[DATA]; + Data1 = xReceive_Buffer[DATA + 1]; + Data2 = xReceive_Buffer[DATA + 2]; + Data3 = xReceive_Buffer[DATA + 3]; for (uint32_t i = 0; i < 3; i++) { - Opt[i] = xReceive_Buffer[DATA + 4 * (i + 1)] << 24 | - xReceive_Buffer[DATA + 4 * (i + 1) + 1] << 16 | - xReceive_Buffer[DATA + 4 * (i + 1) + 2] << 8 | - xReceive_Buffer[DATA + 4 * (i + 1) + 3]; + Opt[i] = unpack_uint32(&xReceive_Buffer[DATA + 4 * (i + 1)]); } Command = Command & 0b00011111; @@ -182,10 +191,7 @@ void processComand(uint8_t *xReceive_Buffer) TransferType = Data0; SizeOfTransfer = Count; Next_Packet = 1; - Expected_CRC = Data2 << 24; - Expected_CRC += Data3 << 16; - Expected_CRC += xReceive_Buffer[DATA + 4] << 8; - Expected_CRC += xReceive_Buffer[DATA + 5]; + Expected_CRC = unpack_uint32(&xReceive_Buffer[DATA + 2]); SizeOfLastPacket = Data1; if (isBiggerThanAvailable(TransferType, (SizeOfTransfer - 1) @@ -229,10 +235,7 @@ void processComand(uint8_t *xReceive_Buffer) case Self_flash: for (uint8_t x = 0; x < numberOfWords; ++x) { offset = 4 * x; - Data = xReceive_Buffer[DATA + offset] << 24; - Data += xReceive_Buffer[DATA + 1 + offset] << 16; - Data += xReceive_Buffer[DATA + 2 + offset] << 8; - Data += xReceive_Buffer[DATA + 3 + offset]; + Data = unpack_uint32(&xReceive_Buffer[DATA + offset]); aux = baseOfAdressType(TransferType) + (uint32_t)( Count * 14 * 4 + x * 4); result = 0; @@ -286,18 +289,12 @@ void processComand(uint8_t *xReceive_Buffer) Buffer[8] = WRFlags >> 8; Buffer[9] = WRFlags; } else { - Buffer[2] = devicesTable[Data0 - 1].sizeOfCode >> 24; - Buffer[3] = devicesTable[Data0 - 1].sizeOfCode >> 16; - Buffer[4] = devicesTable[Data0 - 1].sizeOfCode >> 8; - Buffer[5] = devicesTable[Data0 - 1].sizeOfCode; + pack_uint32(devicesTable[Data0 - 1].sizeOfCode, &Buffer[2]); Buffer[6] = Data0; Buffer[7] = devicesTable[Data0 - 1].BL_Version; Buffer[8] = devicesTable[Data0 - 1].sizeOfDescription; Buffer[9] = devicesTable[Data0 - 1].devID; - Buffer[10] = devicesTable[Data0 - 1].FW_Crc >> 24; - Buffer[11] = devicesTable[Data0 - 1].FW_Crc >> 16; - Buffer[12] = devicesTable[Data0 - 1].FW_Crc >> 8; - Buffer[13] = devicesTable[Data0 - 1].FW_Crc; + pack_uint32(devicesTable[Data0 - 1].FW_Crc, &Buffer[10]); Buffer[14] = devicesTable[Data0 - 1].devID >> 8; Buffer[15] = devicesTable[Data0 - 1].devID; } @@ -341,14 +338,7 @@ void processComand(uint8_t *xReceive_Buffer) } break; case Download_Req: -#ifdef DEBUG_SSP - sprintf(str, "COMMAND:DOWNLOAD_REQ 1 Status=%d|", DeviceState); - PIOS_COM_SendString(PIOS_COM_TELEM_USB, str); -#endif if (DeviceState == DFUidle) { -#ifdef DEBUG_SSP - PIOS_COM_SendString(PIOS_COM_TELEM_USB, "COMMAND:DOWNLOAD_REQ 1|"); -#endif downType = Data0; downPacketTotal = Count; downSizeOfLastPacket = Data1; @@ -370,10 +360,7 @@ void processComand(uint8_t *xReceive_Buffer) Buffer[0] = 0x01; Buffer[1] = Status_Rep; if (DeviceState == wrong_packet_received) { - Buffer[2] = Aditionals >> 24; - Buffer[3] = Aditionals >> 16; - Buffer[4] = Aditionals >> 8; - Buffer[5] = Aditionals; + pack_uint32(Aditionals, &Buffer[2]); } else { Buffer[2] = 0; Buffer[3] = ((uint16_t)Aditionals) >> 8; @@ -469,7 +456,7 @@ uint32_t CalcFirmCRC() } void sendData(uint8_t *buf, uint16_t size) { - PIOS_COM_MSG_Send(PIOS_COM_TELEM_USB, buf, size); + platform_senddata(buf, size); } bool flash_read(uint8_t *buffer, uint32_t adr, DFUProgType type) diff --git a/flight/libraries/ssp.c b/flight/libraries/ssp.c new file mode 100644 index 000000000..287797abc --- /dev/null +++ b/flight/libraries/ssp.c @@ -0,0 +1,795 @@ +/*********************************************************************************************************** +* +* NAME: ssp.c +* DESCRIPTION: simple serial protocol - packet based serial transport layer. +* AUTHOR: Joe Hlebasko +* HISTORY: Created 1/1/2010 +* +* Packet Formats +* Format: +* +------+----+------+---------------------------+--------+ +* | 225 | L1 | S# | App Data (0-254 bytes) | CRC 16 | +* +------+----+------+---------------------------+--------+ +* +* 225 = sync byte, indicates start of a packet +* L1 = 1 byte for size of data payload. (sequence number is part of data payload.) +* S# = 1 byte for sequence number. +* Seq of 0 = seq # synchronise request, forces other end to reset receive sequence number to 1. +* sender of synchronise request will reset the tx seq number to 1 +* Seq # of 1..127 = normal data packets. Sequence number is incremented by for each transmitted +* packet. Rolls over from 127 to 1. +* if most sig. bit is set then the packet is an ACK packet of data packet sequence number of the +* lower 7 bits (1..127) +* App Data may contain 0..254 bytes. The sequence number is consider part of the payload. +* CRC 16 - 16 bits of CRC values of Sequence # and data bytes. +* +* Protocol has two types of packets: data and ack packets. ACK packets have the most sig. bit set in the +* sequence number, this implies that valid sequence numbers are 1..127 +* +* This protocol uses the concept of sequences numbers to determine if a given packet has been received. This +* requires both devices to be able to synchronize sequence numbers. This is accomplished by sending a packet +* length 1 and sequence number = 0. The receive then resets it's transmit sequence number to 1. +* +* ACTIVE_SYNCH is a version that will automatically send a synch request if it receives a synch packet. Only +* one device in the communication should do otherwise you end up with an endless loops of synchronization. +* Right now each side needs to manually issues a synch request. +* +* This protocol is best used in cases where one device is the master and the other is the slave, or a don't +* speak unless spoken to type of approach. +* +* The following are items are required to initialize a port for communications: +* 1. The number attempts for each packet +* 2. time to wait for an ack. +* 3. pointer to buffer to be used for receiving. +* 4. pointer to a buffer to be used for transmission +* 5. length of each buffer (rx and tx) +* 6. Four functions: +* 1. write byte = writes a byte out the serial port (or other comm device) +* 2. read byte = retrieves a byte from the serial port. Returns -1 if a byte is not available +* 3. callback = function to call when a valid data packet has been received. This function is responsible +* to do what needs to be done with the data when it is received. The primary mission of this function +* should be to copy the data to a private buffer out of the working receive buffer to prevent overrun. +* processing should be kept to a minimum. +* 4. get time = function should return the current time. Note that time units are not specified it just +* needs to be some measure of time that increments as time passes by. The timeout values for a given +* port should the units used/returned by the get time function. +* +* All of the state information of a communication port is contained in a Port_t structure. This allows this +* module to operature on multiple communication ports with a single code base. +* +* The ssp_ReceiveProcess and ssp_SendProcess functions need to be called to process data through the +* respective state machines. Typical implementation would have a serial ISR to pull bytes out of the UART +* and place into a circular buffer. The serial read function would then pull bytes out this buffer +* processing. The TX side has the write function placing bytes into a circular buffer with the TX ISR +* pulling bytes out of the buffer and putting into the UART. It is possible to run the receive process from +* the receive ISR but care must be taken on processing data when it is received to avoid holding up the ISR +* and sending ACK packets from the receive ISR. +* +***********************************************************************************************************/ + +/** INCLUDE FILES **/ + +#include +#include +#include +#include +#include "ssp.h" +/** PRIVATE DEFINITIONS **/ +#define SYNC 225 // Sync character used in Serial Protocol +#define ESC 224 // ESC character used in Serial Protocol +#define ESC_SYNC 1 // ESC_SYNC character used in Serial Protocol +#define ACK_BIT 0x80 // Ack bit, bit 7 of sequence number, 1 = Acknowledge, 0 = +// new packet +// packet location definitions. +#define LENGTH 0 +#define SEQNUM 1 +#define DATA 2 + +// Make larger sized integers from smaller sized integers +#define MAKEWORD16(ub, lb) ((uint16_t)0x0000 | ((uint16_t)(ub) << 8) | (uint16_t)(lb)) +#define MAKEWORD32(uw, lw) ((uint32_t)(0x0UL | ((uint32_t)(uw) << 16) | (uint32_t)(lw))) +#define MAKEWORD32B(b3, b2, b1, b0) ((uint32_t)((uint32_t)(b3) << 24) | ((uint32_t)(b2) << 16) | ((uint32_t)(b1) << 8) | ((uint32_t)(b0)) + +// Used to extract smaller integers from larger sized intergers +#define LOWERBYTE(w) (uint8_t)((w) & 0x00ff) +#define UPPERBYTE(w) (uint8_t)(((w) & 0xff00) >> 8) +#define UPPERWORD(lw) (uint16_t)(((lw) & 0xffff0000) >> 16) +#define LOWERWORD(lw) (uint16_t)((lw) & 0x0000ffff) + +// Macros to operate on a target and bitmask. +#define CLEARBIT(a, b) ((a) = (a) & ~(b)) +#define SETBIT(a, b) ((a) = (a) | (b)) +#define TOGGLEBIT(a, b) ((a) = (a) ^ (b)) + +// test bit macros operate using a bit mask. +#define ISBITSET(a, b) (((a) & (b)) == (b) ? TRUE : FALSE) +#define ISBITCLEAR(a, b) ((~(a) & (b)) == (b) ? TRUE : FALSE) + +/** PRIVATE FUNCTIONS **/ +// static void sf_SendSynchPacket( Port_t *thisport ); +static uint16_t sf_checksum(uint16_t crc, uint8_t data); +static void sf_write_byte(Port_t *thisport, uint8_t c); +static void sf_SetSendTimeout(Port_t *thisport); +static uint16_t sf_CheckTimeout(Port_t *thisport); +static int16_t sf_DecodeState(Port_t *thisport, uint8_t c); +static int16_t sf_ReceiveState(Port_t *thisport, uint8_t c); + +static void sf_SendPacket(Port_t *thisport); +static void sf_SendAckPacket(Port_t *thisport, uint8_t seqNumber); +static void sf_MakePacket(uint8_t *buf, const uint8_t *pdata, uint16_t length, + uint8_t seqNo); +static int16_t sf_ReceivePacket(Port_t *thisport); + +/* Flag bit masks...*/ +#define SENT_SYNCH (0x01) +#define ACK_RECEIVED (0x02) +#define ACK_EXPECTED (0x04) + +#define SSP_AWAITING_ACK 0 +#define SSP_ACKED 1 +#define SSP_IDLE 2 + +/** PRIVATE DATA **/ +static const uint16_t CRC_TABLE[] = { 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, + 0x03C0, 0x0280, 0xC241, 0xC601, 0x06C0,0x0780, 0xC741, 0x0500, 0xC5C1, + 0xC481, 0x0440, 0xCC01, 0x0CC0, 0x0D80,0xCD41, 0x0F00, 0xCFC1, 0xCE81, + 0x0E40, 0x0A00, 0xCAC1, 0xCB81, 0x0B40,0xC901, 0x09C0, 0x0880, 0xC841, + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00,0xDBC1, 0xDA81, 0x1A40, 0x1E00, + 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0,0x1C80, 0xDC41, 0x1400, 0xD4C1, + 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680,0xD641, 0xD201, 0x12C0, 0x1380, + 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,0xF001, 0x30C0, 0x3180, 0xF141, + 0x3300, 0xF3C1, 0xF281, 0x3240, 0x3600,0xF6C1, 0xF781, 0x3740, 0xF501, + 0x35C0, 0x3480, 0xF441, 0x3C00, 0xFCC1,0xFD81, 0x3D40, 0xFF01, 0x3FC0, + 0x3E80, 0xFE41, 0xFA01, 0x3AC0, 0x3B80,0xFB41, 0x3900, 0xF9C1, 0xF881, + 0x3840, 0x2800, 0xE8C1, 0xE981, 0x2940,0xEB01, 0x2BC0, 0x2A80, 0xEA41, + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00,0xEDC1, 0xEC81, 0x2C40, 0xE401, + 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1,0xE681, 0x2640, 0x2200, 0xE2C1, + 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080,0xE041, 0xA001, 0x60C0, 0x6180, + 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,0x6600, 0xA6C1, 0xA781, 0x6740, + 0xA501, 0x65C0, 0x6480, 0xA441, 0x6C00,0xACC1, 0xAD81, 0x6D40, 0xAF01, + 0x6FC0, 0x6E80, 0xAE41, 0xAA01, 0x6AC0,0x6B80, 0xAB41, 0x6900, 0xA9C1, + 0xA881, 0x6840, 0x7800, 0xB8C1, 0xB981,0x7940, 0xBB01, 0x7BC0, 0x7A80, + 0xBA41, 0xBE01, 0x7EC0, 0x7F80, 0xBF41,0x7D00, 0xBDC1, 0xBC81, 0x7C40, + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700,0xB7C1, 0xB681, 0x7640, 0x7200, + 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0,0x7080, 0xB041, 0x5000, 0x90C1, + 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280,0x9241, 0x9601, 0x56C0, 0x5780, + 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,0x9C01, 0x5CC0, 0x5D80, 0x9D41, + 0x5F00, 0x9FC1, 0x9E81, 0x5E40, 0x5A00,0x9AC1, 0x9B81, 0x5B40, 0x9901, + 0x59C0, 0x5880, 0x9841, 0x8801, 0x48C0,0x4980, 0x8941, 0x4B00, 0x8BC1, + 0x8A81, 0x4A40, 0x4E00, 0x8EC1, 0x8F81,0x4F40, 0x8D01, 0x4DC0, 0x4C80, + 0x8C41, 0x4400, 0x84C1, 0x8581, 0x4540,0x8701, 0x47C0, 0x4680, 0x8641, + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100,0x81C1, 0x8081, 0x4040 }; + +/** EXTERNAL DATA **/ + +/** EXTERNAL FUNCTIONS **/ + +/** VERIFICATION FUNCTIONS **/ + +/***********************************************************************************************************/ + +/*! + * \brief Initializes the communication port for use + * \param thisport = pointer to port structure to initialize + * \param info = config struct with default values. + * \return None. + * + * \note + * Must be called before calling the Send or REceive process functions. + */ + +void ssp_Init(Port_t *thisport, const PortConfig_t *const info) +{ + thisport->pfCallBack = info->pfCallBack; + thisport->pfSerialRead = info->pfSerialRead; + thisport->pfSerialWrite = info->pfSerialWrite; + thisport->pfGetTime = info->pfGetTime; + + thisport->maxRetryCount = info->max_retry; + thisport->timeoutLen = info->timeoutLen; + thisport->txBufSize = info->txBufSize; + thisport->rxBufSize = info->rxBufSize; + thisport->txBuf = info->txBuf; + thisport->rxBuf = info->rxBuf; + thisport->retryCount = 0; + thisport->sendSynch = FALSE; // TRUE; + thisport->rxSeqNo = 255; + thisport->txSeqNo = 255; + thisport->SendState = SSP_IDLE; +} + +/*! + * \brief Runs the send process, checks for receipt of ack, timeouts and resends if needed. + * \param thisport = which port to use + * \return SSP_TX_WAITING - waiting for a valid ACK to arrive + * \return SSP_TX_TIMEOUT - failed to receive a valid ACK in the timeout period, after retrying. + * \return SSP_TX_IDLE - not expecting a ACK packet (no current transmissions in progress) + * \return SSP_TX_ACKED - valid ACK received before timeout period. + * + * \note + * + */ +int16_t ssp_SendProcess(Port_t *thisport) +{ + int16_t value = SSP_TX_WAITING; + + if (thisport->SendState == SSP_AWAITING_ACK) { + if (sf_CheckTimeout(thisport) == TRUE) { + if (thisport->retryCount < thisport->maxRetryCount) { + // Try again + sf_SendPacket(thisport); + sf_SetSendTimeout(thisport); + value = SSP_TX_WAITING; + } else { + // Give up, # of trys has exceded the limit + value = SSP_TX_TIMEOUT; + CLEARBIT(thisport->flags, ACK_RECEIVED); + thisport->SendState = SSP_IDLE; + } + } else { + value = SSP_TX_WAITING; + } + } else if (thisport->SendState == SSP_ACKED) { + SETBIT(thisport->flags, ACK_RECEIVED); + value = SSP_TX_ACKED; + thisport->SendState = SSP_IDLE; + } else { + thisport->SendState = SSP_IDLE; + value = SSP_TX_IDLE; + } + return value; +} + +/*! + * \brief Runs the receive process. fetches a byte at a time and runs the byte through the protocol receive state machine. + * \param thisport - which port to use. + * \return receive status. + * + * \note + * + */ +int16_t ssp_ReceiveProcess(Port_t *thisport) +{ + int16_t b; + int16_t packet_status = SSP_RX_IDLE; + + do { + b = thisport->pfSerialRead(); // attempt to read a char from the serial buffer + if (b != -1) { + packet_status = sf_ReceiveState(thisport, b); // process the newly received byte in the receive state machine + } + // keep going until either we received a full packet or there are no more bytes to process + } while (packet_status != SSP_RX_COMPLETE && b != -1); + return packet_status; +} + +/*! + * \brief processes a single byte through the receive state machine. + * \param thisport = which port to use + * \return current receive status + * + * \note + * + */ + +int16_t ssp_ReceiveByte(Port_t *thisport) +{ + int16_t b; + int16_t packet_status = SSP_RX_IDLE; + + b = thisport->pfSerialRead(); + if (b != -1) { + packet_status = sf_ReceiveState(thisport, b); + } + return packet_status; +} + +/*! + * \brief Sends a data packet and blocks until timeout or ack is received. + * \param thisport = which port to use + * \param data = pointer to data to send + * \param length = number of data bytes to send. Must be less than 254 + * \return true = ack was received within number of retries + * \return false = ack was not received. + * + * \note + * + */ +uint16_t ssp_SendDataBlock(Port_t *thisport, uint8_t *data, uint16_t length) +{ + int16_t packet_status = SSP_TX_WAITING; + + packet_status = ssp_SendData(thisport, data, length); // send the data + while (packet_status == SSP_TX_WAITING) { // check the status + (void)ssp_ReceiveProcess(thisport); // process any bytes received. + packet_status = ssp_SendProcess(thisport); // check the send status + } + return packet_status == SSP_TX_ACKED; // figure out what happened to the packet +} + +/*! + * \brief sends a chunk of data and does not block + * \param thisport = which port to use + * \param data = pointer to data to send + * \param length = number of bytes to send + * \return SSP_TX_BUFOVERRUN = tried to send too much data + * \return SSP_TX_WAITING = data sent and waiting for an ack to arrive + * \return SSP_TX_BUSY = a packet has already been sent, but not yet acked + * + * \note + * + */ +int16_t ssp_SendData(Port_t *thisport, const uint8_t *data, + const uint16_t length) +{ + int16_t value = SSP_TX_WAITING; + + if ((length + 2) > thisport->txBufSize) { + // TRYING to send too much data. + value = SSP_TX_BUFOVERRUN; + } else if (thisport->SendState == SSP_IDLE) { +#ifdef ACTIVE_SYNCH + if (thisport->sendSynch == TRUE) { + sf_SendSynchPacket(thisport); + } +#endif + +#ifdef SYNCH_SEND + if (length == 0) { + // TODO this method could allow a task/user to start a synchronisation step if a zero is mistakenly passed to this function. + // could add a check for a NULL data pointer, or use some sort of static flag that can only be accessed by a static function + // that must be called before calling this function. + // we are attempting to send a synch packet + thisport->txSeqNo = 0; // make this zero to cause the other end to re-synch with us + SETBIT(thisport->flags, SENT_SYNCH); + } else { + // we are sending a data packet + CLEARBIT(thisport->txSeqNo, ACK_BIT); // make sure we are not sending a ACK packet + thisport->txSeqNo++; // update the sequence number. + if (thisport->txSeqNo > 0x7F) { // check for sequence number rollover + thisport->txSeqNo = 1; // if we do have rollover then reset to 1 not zero, + // zero is reserviced for synchronization requests + } + } + +#else + CLEARBIT(thisport->txSeqNo, ACK_BIT); // make sure we are not sending a ACK packet + thisport->txSeqNo++; // update the sequence number. + if (thisport->txSeqNo > 0x7F) { // check for sequence number rollover + thisport->txSeqNo = 1; // if we do have rollover then reset to 1 not zero, + // zero is reserved for synchronization requests + } +#endif /* ifdef SYNCH_SEND */ + CLEARBIT(thisport->flags, ACK_RECEIVED); + thisport->SendState = SSP_AWAITING_ACK; + value = SSP_TX_WAITING; + thisport->retryCount = 0; // zero out the retry counter for this transmission + sf_MakePacket(thisport->txBuf, data, length, thisport->txSeqNo); + sf_SendPacket(thisport); // punch out the packet to the serial port + sf_SetSendTimeout(thisport); // do the timeout values + } else { + // error we are already sending a packet. Need to wait for the current packet to be acked or timeout. + value = SSP_TX_BUSY; + } + return value; +} + +/*! + * \brief Attempts to synchronize the sequence numbers with the other end of the connectin. + * \param thisport = which port to use + * \return true = success + * \return false = failed to receive an ACK to our synch request + * + * \note + * A. send a packet with a sequence number equal to zero + * B. if timed out then: + * send synch packet again + * increment try counter + * if number of tries exceed maximum try limit then exit + * C. goto A + */ +uint16_t ssp_Synchronise(Port_t *thisport) +{ + int16_t packet_status; + +#ifndef USE_SENDPACKET_DATA + thisport->txSeqNo = 0; // make this zero to cause the other end to re-synch with us + SETBIT(thisport->flags, SENT_SYNCH); + // TODO - should this be using ssp_SendPacketData()?? + sf_MakePacket(thisport->txBuf, NULL, 0, thisport->txSeqNo); // construct the packet + sf_SendPacket(thisport); + sf_SetSendTimeout(thisport); + thisport->SendState = SSP_AWAITING_ACK; + packet_status = SSP_TX_WAITING; +#else + packet_status = ssp_SendData(thisport, NULL, 0); +#endif + while (packet_status == SSP_TX_WAITING) { // we loop until we time out. + (void)ssp_ReceiveProcess(thisport); // do the receive process + packet_status = ssp_SendProcess(thisport); // do the send process + } + thisport->sendSynch = FALSE; + return packet_status == SSP_TX_ACKED; +} + +/*! + * \brief sends out a preformatted packet for a give port + * \param thisport = which port to use. + * \return none. + * + * \note + * Packet should be formed through the use of sf_MakePacket before calling this function. + */ +static void sf_SendPacket(Port_t *thisport) +{ + // add 3 to packet data length for: 1 length + 2 CRC (packet overhead) + uint8_t packetLen = thisport->txBuf[LENGTH] + 3; + + // use the raw serial write function so the SYNC byte does not get 'escaped' + thisport->pfSerialWrite(SYNC); + for (uint8_t x = 0; x < packetLen; x++) { + sf_write_byte(thisport, thisport->txBuf[x]); + } + thisport->retryCount++; +} + +/*! + * \brief converts data to transport layer protocol packet format. + * \param txbuf = buffer to use when forming the packet + * \param pdata = pointer to data to use + * \param length = number of bytes to use + * \param seqNo = sequence number of this packet + * \return none. + * + * \note + * 1. This function does not try to interpret ACK or SYNCH packets. This should + * be done by the caller of this function. + * 2. This function will attempt to format all data upto the size of the tx buffer. + * Any extra data beyond that will be ignored. + * 3. TODO: Should this function return an error if data length to be sent is greater th tx buffer size? + * + */ +void sf_MakePacket(uint8_t *txBuf, const uint8_t *pdata, uint16_t length, + uint8_t seqNo) +{ + uint16_t crc = 0xffff; + uint16_t bufPos = 0; + uint8_t b; + + // add 1 for the seq. number + txBuf[LENGTH] = length + 1; + txBuf[SEQNUM] = seqNo; + crc = sf_checksum(crc, seqNo); + + length = length + 2; // add two for the length and seqno bytes which are added before the loop. + for (bufPos = 2; bufPos < length; bufPos++) { + b = *pdata++; + txBuf[bufPos] = b; + crc = sf_checksum(crc, b); // update CRC value + } + txBuf[bufPos++] = LOWERBYTE(crc); + txBuf[bufPos] = UPPERBYTE(crc); +} + +/*! + * \brief sends out an ack packet to given sequence number + * \param thisport = which port to use + * \param seqNumber = sequence number of the packet we would like to ack + * \return none. + * + * \note + * + */ + +static void sf_SendAckPacket(Port_t *thisport, uint8_t seqNumber) +{ + uint8_t AckSeqNumber = SETBIT(seqNumber, ACK_BIT); + + // create the packet, note we pass AckSequenceNumber directly + sf_MakePacket(thisport->txBuf, NULL, 0, AckSeqNumber); + sf_SendPacket(thisport); + // we don't set the timeout for an ACK because we don't ACK our ACKs in this protocol +} + +/*! + * \brief writes a byte out the output channel. Adds escape byte where needed + * \param thisport = which port to use + * \param c = byte to send + * \return none. + * + * \note + * + */ +static void sf_write_byte(Port_t *thisport, uint8_t c) +{ + if (c == SYNC) { // check for SYNC byte + thisport->pfSerialWrite(ESC); // since we are not starting a packet we must ESCAPE the SYNCH byte + thisport->pfSerialWrite(ESC_SYNC); // now send the escaped synch char + } else if (c == ESC) { // Check for ESC character + thisport->pfSerialWrite(ESC); // if it is, we need to send it twice + thisport->pfSerialWrite(ESC); + } else { + thisport->pfSerialWrite(c); // otherwise write the byte to serial port + } +} + +/************************************************************************************************************ + * + * NAME: uint16_t ssp_crc16( uint16_t crc, uint16_t data ) + * DESCRIPTION: Uses crc_table to calculate new crc + * ARGUMENTS: + * arg1: crc + * arg2: data - byte to calculate into CRC + * RETURN: New crc + * CREATED: 5/8/02 + * + *************************************************************************************************************/ +/*! + * \brief calculates the new CRC value for 'data' + * \param crc = current CRC value + * \param data = new byte + * \return updated CRC value + * + * \note + * + */ + +static uint16_t sf_checksum(uint16_t crc, uint8_t data) +{ +#ifdef SPP_USES_CRC + return (crc >> 8) ^ CRC_TABLE[(crc ^ data) & 0x00FF]; + +#else + uint8_t cka = crc & 0xff; + uint8_t ckb = (crc >> 8) & 0xff; + cka += data; + ckb += cka; + return cka | ckb << 8; + +#endif +} + +/*! + * \brief sets the timeout for the given packet + * \param thisport = which port to use + * \return none. + * + * \note + * + */ + +static void sf_SetSendTimeout(Port_t *thisport) +{ + uint32_t timeout; + + timeout = thisport->pfGetTime() + thisport->timeoutLen; + thisport->timeout = timeout; +} + +/*! + * \brief checks to see if a timeout occured + * \param thisport = which port to use + * \return true = a timeout has occurred + * \return false = has not timed out + * + * \note + * + */ +static uint16_t sf_CheckTimeout(Port_t *thisport) +{ + uint16_t retval = FALSE; + uint32_t current_time; + + current_time = thisport->pfGetTime(); + if (current_time > thisport->timeout) { + retval = TRUE; + } + return retval; +} + +/**************************************************************************** +* NAME: sf_ReceiveState +* DESC: Implements the receive state handling code for escaped and unescaped data +* ARGS: thisport - which port to operate on +* c - incoming byte +* RETURN: +* CREATED: +* NOTES: +* 1. change from using pointer to functions. +****************************************************************************/ +/*! + * \brief implements the receive state handling code for escaped and unescaped data + * \param thisport = which port to use + * \param c = byte to process through the receive state machine + * \return receive status + * + * \note + * + */ +static int16_t sf_ReceiveState(Port_t *thisport, uint8_t c) +{ + int16_t retval = SSP_RX_RECEIVING; + + switch (thisport->InputState) { + case state_unescaped_e: + if (c == SYNC) { + thisport->DecodeState = decode_len1_e; + } else if (c == ESC) { + thisport->InputState = state_escaped_e; + } else { + retval = sf_DecodeState(thisport, c); + } + break; // end of unescaped state. + case state_escaped_e: + thisport->InputState = state_unescaped_e; + if (c == SYNC) { + thisport->DecodeState = decode_len1_e; + } else if (c == ESC_SYNC) { + retval = sf_DecodeState(thisport, SYNC); + } else { + retval = sf_DecodeState(thisport, c); + } + break; // end of the escaped state. + default: + break; + } + return retval; +} + +/**************************************************************************** +* NAME: sf_DecodeState +* DESC: Implements the receive state finite state machine +* ARGS: thisport - which port to operate on +* c - incoming byte +* RETURN: +* CREATED: +* NOTES: +* 1. change from using pointer to functions. +****************************************************************************/ + +/*! + * \brief implements the receiving decoding state machine + * \param thisport = which port to use + * \param c = byte to process + * \return receive status + * + * \note + * + */ +static int16_t sf_DecodeState(Port_t *thisport, uint8_t c) +{ + int16_t retval; + + switch (thisport->DecodeState) { + case decode_idle_e: + // 'c' is ignored in this state as the only way to leave the idle state is + // recognition of the SYNC byte in the sf_ReceiveState function. + retval = SSP_RX_IDLE; + break; + case decode_len1_e: + thisport->rxBuf[LENGTH] = c; + thisport->rxBufLen = c; + if (thisport->rxBufLen <= thisport->rxBufSize) { + thisport->DecodeState = decode_seqNo_e; + retval = SSP_RX_RECEIVING; + } else { + thisport->DecodeState = decode_idle_e; + retval = SSP_RX_IDLE; + } + break; + case decode_seqNo_e: + thisport->rxBuf[SEQNUM] = c; + thisport->crc = 0xffff; + thisport->rxBufLen--; // subtract 1 for the seq. no. + thisport->rxBufPos = 2; + + thisport->crc = sf_checksum(thisport->crc, c); + if (thisport->rxBufLen > 0) { + thisport->DecodeState = decode_data_e; + } else { + thisport->DecodeState = decode_crc1_e; + } + retval = SSP_RX_RECEIVING; + break; + case decode_data_e: + thisport->rxBuf[(thisport->rxBufPos)++] = c; + thisport->crc = sf_checksum(thisport->crc, c); + if (thisport->rxBufPos == (thisport->rxBufLen + 2)) { + thisport->DecodeState = decode_crc1_e; + } + retval = SSP_RX_RECEIVING; + break; + case decode_crc1_e: + thisport->crc = sf_checksum(thisport->crc, c); + thisport->DecodeState = decode_crc2_e; + retval = SSP_RX_RECEIVING; + break; + case decode_crc2_e: + thisport->DecodeState = decode_idle_e; + // verify the CRC value for the packet + if (sf_checksum(thisport->crc, c) == 0) { + // TODO shouldn't the return value of sf_ReceivePacket() be checked? + sf_ReceivePacket(thisport); + retval = SSP_RX_COMPLETE; + } else { + thisport->RxError++; + retval = SSP_RX_IDLE; + } + break; + default: + thisport->DecodeState = decode_idle_e; // unknown state so reset to idle state and wait for the next start of a packet. + retval = SSP_RX_IDLE; + break; + } + return retval; +} + +/************************************************************************************************************ + * + * NAME: int16_t sf_ReceivePacket( ) + * DESCRIPTION: Receive one packet, assumed that data is in rec.buff[] + * ARGUMENTS: + * RETURN: 0 . no new packet was received, could be ack or same packet + * 1 . new packet received + * SSP_PACKET_? + * SSP_PACKET_COMPLETE + * SSP_PACKET_ACK + * CREATED: 5/8/02 + * + *************************************************************************************************************/ +/*! + * \brief receive one packet. calls the callback function if needed. + * \param thisport = which port to use + * \return true = valid data packet received. + * \return false = otherwise + * + * \note + * + * Created: Oct 7, 2010 12:07:22 AM by joe + */ + +static int16_t sf_ReceivePacket(Port_t *thisport) +{ + int16_t value = FALSE; + + if (ISBITSET(thisport->rxBuf[SEQNUM], ACK_BIT)) { + // Received an ACK packet, need to check if it matches the previous sent packet + if ((thisport->rxBuf[SEQNUM] & 0x7F) == (thisport->txSeqNo & 0x7f)) { + // It matches the last packet sent by us + SETBIT(thisport->txSeqNo, ACK_BIT); + thisport->SendState = SSP_ACKED; + + value = FALSE; + } + // else ignore the ACK packet + } else { + // Received a 'data' packet, figure out what type of packet we received... + if (thisport->rxBuf[SEQNUM] == 0) { + // Synchronize sequence number with host +#ifdef ACTIVE_SYNCH + thisport->sendSynch = TRUE; +#endif + sf_SendAckPacket(thisport, thisport->rxBuf[SEQNUM]); + thisport->rxSeqNo = 0; + value = FALSE; + } else if (thisport->rxBuf[SEQNUM] == thisport->rxSeqNo) { + // Already seen this packet, just ack it, don't act on the packet. + sf_SendAckPacket(thisport, thisport->rxBuf[SEQNUM]); + value = FALSE; + } else { + // New Packet + thisport->rxSeqNo = thisport->rxBuf[SEQNUM]; + // Let the application do something with the data/packet. + if (thisport->pfCallBack != NULL) { + // skip the first two bytes (length and seq. no.) in the buffer. + thisport->pfCallBack(&(thisport->rxBuf[2]), thisport->rxBufLen); + } + // after we send the ACK, it is possible for the host to send a new packet. + // Thus the application needs to copy the data and reset the receive buffer + // inside of thisport->pfCallBack() + sf_SendAckPacket(thisport, thisport->rxBuf[SEQNUM]); + value = TRUE; + } + } + return value; +} diff --git a/flight/libraries/stopwatch.c b/flight/libraries/stopwatch.c deleted file mode 100644 index efa00d451..000000000 --- a/flight/libraries/stopwatch.c +++ /dev/null @@ -1,126 +0,0 @@ -/** - ****************************************************************************** - * @addtogroup CopterControlBL CopterControl BootLoader - * @{ - * - * @file stopwatch.c - * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010. - * @brief Timer functions for the LED PWM. - * @see The GNU Public License (GPL) Version 3 - * - *****************************************************************************/ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -///////////////////////////////////////////////////////////////////////////// -// Include files -///////////////////////////////////////////////////////////////////////////// - -#include "stm32f10x_tim.h" - -///////////////////////////////////////////////////////////////////////////// -// Local definitions -///////////////////////////////////////////////////////////////////////////// - -uint32_t STOPWATCH_Init(u32 resolution, TIM_TypeDef *TIM) -{ - uint32_t STOPWATCH_TIMER_RCC; - - switch ((uint32_t)TIM) { - case (uint32_t)TIM1: - STOPWATCH_TIMER_RCC = RCC_APB2Periph_TIM1; - break; - case (uint32_t)TIM2: - STOPWATCH_TIMER_RCC = RCC_APB1Periph_TIM2; - break; - case (uint32_t)TIM3: - STOPWATCH_TIMER_RCC = RCC_APB1Periph_TIM3; - break; - case (uint32_t)TIM4: - STOPWATCH_TIMER_RCC = RCC_APB1Periph_TIM4; - break; - case (uint32_t)TIM5: - STOPWATCH_TIMER_RCC = RCC_APB1Periph_TIM5; - break; - case (uint32_t)TIM6: - STOPWATCH_TIMER_RCC = RCC_APB1Periph_TIM6; - break; - case (uint32_t)TIM7: - STOPWATCH_TIMER_RCC = RCC_APB1Periph_TIM7; - break; - case (uint32_t)TIM8: - STOPWATCH_TIMER_RCC = RCC_APB2Periph_TIM8; - break; - default: - /* Unsupported timer */ - while (1) { - ; - } - } - - // enable timer clock - if (STOPWATCH_TIMER_RCC == RCC_APB2Periph_TIM1 || STOPWATCH_TIMER_RCC - == RCC_APB2Periph_TIM8) { - RCC_APB2PeriphClockCmd(STOPWATCH_TIMER_RCC, ENABLE); - } else { - RCC_APB1PeriphClockCmd(STOPWATCH_TIMER_RCC, ENABLE); - } - - // time base configuration - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - TIM_TimeBaseStructure.TIM_Period = 0xffff; // max period - TIM_TimeBaseStructure.TIM_Prescaler = (72 * resolution) - 1; // uS accuracy @ 72 MHz - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(TIM, &TIM_TimeBaseStructure); - - // enable interrupt request - TIM_ITConfig(TIM, TIM_IT_Update, ENABLE); - - // start counter - TIM_Cmd(TIM, ENABLE); - - return 0; // no error -} - -///////////////////////////////////////////////////////////////////////////// -// ! Resets the stopwatch -// ! \return < 0 on errors -///////////////////////////////////////////////////////////////////////////// -uint32_t STOPWATCH_Reset(TIM_TypeDef *TIM) -{ - // reset counter - TIM->CNT = 1; // set to 1 instead of 0 to avoid new IRQ request - TIM_ClearITPendingBit(TIM, TIM_IT_Update); - - return 0; // no error -} - -///////////////////////////////////////////////////////////////////////////// -// ! Returns current value of stopwatch -// ! \return 1..65535: valid stopwatch value -// ! \return 0xffffffff: counter overrun -///////////////////////////////////////////////////////////////////////////// -uint32_t STOPWATCH_ValueGet(TIM_TypeDef *TIM) -{ - uint32_t value = TIM->CNT; - - if (TIM_GetITStatus(TIM, TIM_IT_Update) != RESET) { - value = 0xffffffff; - } - - return value; -} diff --git a/flight/libraries/ubx_utils.c b/flight/libraries/ubx_utils.c new file mode 100644 index 000000000..0c82069a2 --- /dev/null +++ b/flight/libraries/ubx_utils.c @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * + * @file ubx_utils.c + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief UBX Protocol utilities. + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +bool ubx_getLastSentence(uint8_t *data, uint16_t bufferCount, uint8_t * *lastSentence, uint16_t *length) +{ + const uint8_t packet_overhead = UBX_HEADER_LEN + 2; + uint8_t *current = data + bufferCount - packet_overhead; + + while (current >= data) { + // look for a ubx a sentence + if (current[0] == UBX_SYN1 && current[1] == UBX_SYN2) { + // check whether it fits the current buffer (whole sentence is into buffer) + uint16_t len = current[4] + (current[5] << 8); + if (len + packet_overhead + current <= data + bufferCount) { + *lastSentence = current; + *length = len + packet_overhead; + return true; + } + } + current--; + } + // no complete sentence found + return false; +} + +void ubx_buildPacket(UBXPacket_t *pkt, uint8_t packetClass, uint8_t packetId, uint16_t len) +{ + pkt->packet.header.syn1 = UBX_SYN1; + pkt->packet.header.syn2 = UBX_SYN2; + + // don't make any assumption on alignments... + ((uint8_t *)&pkt->packet.header.len)[0] = len & 0xFF; + ((uint8_t *)&pkt->packet.header.len)[1] = (len >> 8) & 0xFF; + + pkt->packet.header.class = packetClass; + pkt->packet.header.id = packetId; + ubx_appendChecksum(pkt); +} + +void ubx_appendChecksum(UBXPacket_t *pkt) +{ + uint8_t chkA = 0; + uint8_t chkB = 0; + uint16_t len = ((uint8_t *)&pkt->packet.header.len)[0] | ((uint8_t *)&pkt->packet.header.len)[1] << 8; + + // From class field to the end of payload + for (uint8_t i = 2; i < len + UBX_HEADER_LEN; i++) { + chkA += pkt->binarystream[i]; + chkB += chkA; + } + ; + pkt->packet.payload[len] = chkA; + pkt->packet.payload[len + 1] = chkB; +} diff --git a/flight/modules/Attitude/attitude.c b/flight/modules/Attitude/attitude.c index 2e9346764..705c713df 100644 --- a/flight/modules/Attitude/attitude.c +++ b/flight/modules/Attitude/attitude.c @@ -446,31 +446,51 @@ static int32_t updateSensors(AccelStateData *accelState, GyroStateData *gyros) static struct pios_mpu6000_data mpu6000_data; static int32_t updateSensorsCC3D(AccelStateData *accelStateData, GyroStateData *gyrosData) { - float accels[3], gyros[3]; + float accels[3] = { 0 }; + float gyros[3] = { 0 }; + float temp = 0; + uint8_t count = 0; #if defined(PIOS_INCLUDE_MPU6000) xQueueHandle queue = PIOS_MPU6000_GetQueue(); + BaseType_t ret = xQueueReceive(queue, (void *)&mpu6000_data, SENSOR_PERIOD); + while (ret == pdTRUE) { + gyros[0] += mpu6000_data.gyro_x; + gyros[1] += mpu6000_data.gyro_y; + gyros[2] += mpu6000_data.gyro_z; - if (xQueueReceive(queue, (void *)&mpu6000_data, SENSOR_PERIOD) == errQUEUE_EMPTY) { + accels[0] += mpu6000_data.accel_x; + accels[1] += mpu6000_data.accel_y; + accels[2] += mpu6000_data.accel_z; + + temp += mpu6000_data.temperature; + + count++; + // check if further samples are already in queue + ret = xQueueReceive(queue, (void *)&mpu6000_data, 0); + } + + if (!count) { return -1; // Error, no data } // Do not read raw sensor data in simulation mode if (GyroStateReadOnly() || AccelStateReadOnly()) { return 0; } + float invcount = 1.0f / count; PERF_TIMED_SECTION_START(counterUpd); - gyros[0] = mpu6000_data.gyro_x * gyro_scale.X; - gyros[1] = mpu6000_data.gyro_y * gyro_scale.Y; - gyros[2] = mpu6000_data.gyro_z * gyro_scale.Z; + gyros[0] *= gyro_scale.X * invcount; + gyros[1] *= gyro_scale.Y * invcount; + gyros[2] *= gyro_scale.Z * invcount; - accels[0] = mpu6000_data.accel_x * accel_scale.X; - accels[1] = mpu6000_data.accel_y * accel_scale.Y; - accels[2] = mpu6000_data.accel_z * accel_scale.Z; - - float ctemp = mpu6000_data.temperature > temp_calibrated_extent.max ? temp_calibrated_extent.max : - (mpu6000_data.temperature < temp_calibrated_extent.min ? temp_calibrated_extent.min - : mpu6000_data.temperature); + accels[0] *= accel_scale.X * invcount; + accels[1] *= accel_scale.Y * invcount; + accels[2] *= accel_scale.Z * invcount; + temp *= invcount; + float ctemp = temp > temp_calibrated_extent.max ? temp_calibrated_extent.max : + (temp < temp_calibrated_extent.min ? temp_calibrated_extent.min + : temp); if (apply_gyro_temp) { diff --git a/flight/modules/FirmwareIAP/firmwareiap.c b/flight/modules/FirmwareIAP/firmwareiap.c index f2e23e033..0d8b1c900 100644 --- a/flight/modules/FirmwareIAP/firmwareiap.c +++ b/flight/modules/FirmwareIAP/firmwareiap.c @@ -176,6 +176,7 @@ static void FirmwareIAPCallback(UAVObjEvent *ev) case IAP_STATE_STEP_2: if (data.Command == IAP_CMD_STEP_3) { if (delta > iap_time_3_low_end && delta < iap_time_3_high_end) { +#ifndef PIOS_APPS_MINIMAL FlightStatusData flightStatus; FlightStatusGet(&flightStatus); @@ -184,7 +185,7 @@ static void FirmwareIAPCallback(UAVObjEvent *ev) iap_state = IAP_STATE_READY; break; } - +#endif // we've met the three sequence of command numbers // we've met the time requirements. PIOS_IAP_SetRequest1(); diff --git a/flight/modules/GPS/GPS.c b/flight/modules/GPS/GPS.c index e8524fd2e..97151f2fb 100644 --- a/flight/modules/GPS/GPS.c +++ b/flight/modules/GPS/GPS.c @@ -52,6 +52,10 @@ #include "inc/ubx_autoconfig.h" #endif +#include +PERF_DEFINE_COUNTER(counterBytesIn); +PERF_DEFINE_COUNTER(counterRate); +PERF_DEFINE_COUNTER(counterParse); // **************** // Private functions @@ -79,17 +83,24 @@ void updateGpsSettings(UAVObjEvent *ev); // the new location with Set = true. #define GPS_HOMELOCATION_SET_DELAY 5000 +#define GPS_LOOP_DELAY_MS 6 + #ifdef PIOS_GPS_SETS_HOMELOCATION // Unfortunately need a good size stack for the WMM calculation #define STACK_SIZE_BYTES 1024 #else #if defined(PIOS_GPS_MINIMAL) + #define GPS_READ_BUFFER 32 #define STACK_SIZE_BYTES 500 #else #define STACK_SIZE_BYTES 650 #endif // PIOS_GPS_MINIMAL #endif // PIOS_GPS_SETS_HOMELOCATION +#ifndef GPS_READ_BUFFER +#define GPS_READ_BUFFER 128 +#endif + #define TASK_PRIORITY (tskIDLE_PRIORITY + 1) // **************** @@ -238,9 +249,16 @@ static void gpsTask(__attribute__((unused)) void *parameters) #if defined(PIOS_INCLUDE_GPS_UBX_PARSER) && !defined(PIOS_GPS_MINIMAL) updateGpsSettings(0); #endif + + TickType_t xLastWakeTime; + xLastWakeTime = xTaskGetTickCount(); + PERF_INIT_COUNTER(counterBytesIn, 0x97510001); + PERF_INIT_COUNTER(counterRate, 0x97510002); + PERF_INIT_COUNTER(counterParse, 0x97510003); + uint8_t c[GPS_READ_BUFFER]; + // Loop forever while (1) { - uint8_t c; #if defined(PIOS_INCLUDE_GPS_UBX_PARSER) && !defined(PIOS_GPS_MINIMAL) if (gpsSettings.DataProtocol == GPSSETTINGS_DATAPROTOCOL_UBX) { char *buffer = 0; @@ -255,12 +273,16 @@ static void gpsTask(__attribute__((unused)) void *parameters) } #endif // This blocks the task until there is something on the buffer - while (PIOS_COM_ReceiveBuffer(gpsPort, &c, 1, xDelay) > 0) { + uint16_t cnt; + while ((cnt = PIOS_COM_ReceiveBuffer(gpsPort, c, GPS_READ_BUFFER, xDelay)) > 0) { + PERF_TIMED_SECTION_START(counterParse); + PERF_TRACK_VALUE(counterBytesIn, cnt); + PERF_MEASURE_PERIOD(counterRate); int res; switch (gpsSettings.DataProtocol) { #if defined(PIOS_INCLUDE_GPS_NMEA_PARSER) case GPSSETTINGS_DATAPROTOCOL_NMEA: - res = parse_nmea_stream(c, gps_rx_buffer, &gpspositionsensor, &gpsRxStats); + res = parse_nmea_stream(c, cnt, gps_rx_buffer, &gpspositionsensor, &gpsRxStats); break; #endif #if defined(PIOS_INCLUDE_GPS_UBX_PARSER) @@ -280,7 +302,7 @@ static void gpsTask(__attribute__((unused)) void *parameters) lastStatus = gpspositionsensor.AutoConfigStatus; } #endif - res = parse_ubx_stream(c, gps_rx_buffer, &gpspositionsensor, &gpsRxStats); + res = parse_ubx_stream(c, cnt, gps_rx_buffer, &gpspositionsensor, &gpsRxStats); } break; #endif @@ -289,6 +311,7 @@ static void gpsTask(__attribute__((unused)) void *parameters) break; } + PERF_TIMED_SECTION_END(counterParse); if (res == PARSER_COMPLETE) { timeNowMs = xTaskGetTickCount() * portTICK_RATE_MS; timeOfLastUpdateMs = timeNowMs; @@ -336,6 +359,7 @@ static void gpsTask(__attribute__((unused)) void *parameters) AlarmsSet(SYSTEMALARMS_ALARM_GPS, SYSTEMALARMS_ALARM_CRITICAL); } } + vTaskDelayUntil(&xLastWakeTime, GPS_LOOP_DELAY_MS / portTICK_RATE_MS); } } diff --git a/flight/modules/GPS/NMEA.c b/flight/modules/GPS/NMEA.c index e45702990..34eba2f9f 100644 --- a/flight/modules/GPS/NMEA.c +++ b/flight/modules/GPS/NMEA.c @@ -106,75 +106,80 @@ static const struct nmea_parser nmea_parsers[] = { #endif // PIOS_GPS_MINIMAL }; -int parse_nmea_stream(uint8_t c, char *gps_rx_buffer, GPSPositionSensorData *GpsData, struct GPS_RX_STATS *gpsRxStats) +int parse_nmea_stream(uint8_t *rx, uint8_t len, char *gps_rx_buffer, GPSPositionSensorData *GpsData, struct GPS_RX_STATS *gpsRxStats) { + int ret = PARSER_INCOMPLETE; static uint8_t rx_count = 0; static bool start_flag = false; static bool found_cr = false; + uint8_t c; - // detect start while acquiring stream - if (!start_flag && (c == '$')) { // NMEA identifier found - start_flag = true; - found_cr = false; - rx_count = 0; - } else if (!start_flag) { - return PARSER_ERROR; - } - - if (rx_count >= NMEA_MAX_PACKET_LENGTH) { - // The buffer is already full and we haven't found a valid NMEA sentence. - // Flush the buffer and note the overflow event. - gpsRxStats->gpsRxOverflow++; - start_flag = false; - found_cr = false; - rx_count = 0; - return PARSER_OVERRUN; - } else { - gps_rx_buffer[rx_count] = c; - rx_count++; - } - - // look for ending '\r\n' sequence - if (!found_cr && (c == '\r')) { - found_cr = true; - } else if (found_cr && (c != '\n')) { - found_cr = false; // false end flag - } else if (found_cr && (c == '\n')) { - // The NMEA functions require a zero-terminated string - // As we detected \r\n, the string as for sure 2 bytes long, we will also strip the \r\n - gps_rx_buffer[rx_count - 2] = 0; - - // prepare to parse next sentence - start_flag = false; - found_cr = false; - rx_count = 0; - // Our rxBuffer must look like this now: - // [0] = '$' - // ... = zero or more bytes of sentence payload - // [end_pos - 1] = '\r' - // [end_pos] = '\n' - // - // Prepare to consume the sentence from the buffer - - // Validate the checksum over the sentence - if (!NMEA_checksum(&gps_rx_buffer[1])) { // Invalid checksum. May indicate dropped characters on Rx. - // PIOS_DEBUG_PinHigh(2); - gpsRxStats->gpsRxChkSumError++; - // PIOS_DEBUG_PinLow(2); + for (int i = 0; i < len; i++) { + c = rx[i]; + // detect start while acquiring stream + if (!start_flag && (c == '$')) { // NMEA identifier found + start_flag = true; + found_cr = false; + rx_count = 0; + } else if (!start_flag) { return PARSER_ERROR; - } else { // Valid checksum, use this packet to update the GPS position - if (!NMEA_update_position(&gps_rx_buffer[1], GpsData)) { - // PIOS_DEBUG_PinHigh(2); - gpsRxStats->gpsRxParserError++; - // PIOS_DEBUG_PinLow(2); - } else { - gpsRxStats->gpsRxReceived++; - }; + } - return PARSER_COMPLETE; + if (rx_count >= NMEA_MAX_PACKET_LENGTH) { + // The buffer is already full and we haven't found a valid NMEA sentence. + // Flush the buffer and note the overflow event. + gpsRxStats->gpsRxOverflow++; + start_flag = false; + found_cr = false; + rx_count = 0; + ret = PARSER_OVERRUN; + } else { + gps_rx_buffer[rx_count] = c; + rx_count++; + } + + // look for ending '\r\n' sequence + if (!found_cr && (c == '\r')) { + found_cr = true; + } else if (found_cr && (c != '\n')) { + found_cr = false; // false end flag + } else if (found_cr && (c == '\n')) { + // The NMEA functions require a zero-terminated string + // As we detected \r\n, the string as for sure 2 bytes long, we will also strip the \r\n + gps_rx_buffer[rx_count - 2] = 0; + + // prepare to parse next sentence + start_flag = false; + found_cr = false; + rx_count = 0; + // Our rxBuffer must look like this now: + // [0] = '$' + // ... = zero or more bytes of sentence payload + // [end_pos - 1] = '\r' + // [end_pos] = '\n' + // + // Prepare to consume the sentence from the buffer + + // Validate the checksum over the sentence + if (!NMEA_checksum(&gps_rx_buffer[1])) { // Invalid checksum. May indicate dropped characters on Rx. + // PIOS_DEBUG_PinHigh(2); + gpsRxStats->gpsRxChkSumError++; + // PIOS_DEBUG_PinLow(2); + ret = PARSER_ERROR; + } else { // Valid checksum, use this packet to update the GPS position + if (!NMEA_update_position(&gps_rx_buffer[1], GpsData)) { + // PIOS_DEBUG_PinHigh(2); + gpsRxStats->gpsRxParserError++; + // PIOS_DEBUG_PinLow(2); + } else { + gpsRxStats->gpsRxReceived++; + }; + + ret = PARSER_COMPLETE; + } } } - return PARSER_INCOMPLETE; + return ret; } static const struct nmea_parser *NMEA_find_parser_by_prefix(const char *prefix) diff --git a/flight/modules/GPS/UBX.c b/flight/modules/GPS/UBX.c index c883e7a39..76c65bb57 100644 --- a/flight/modules/GPS/UBX.c +++ b/flight/modules/GPS/UBX.c @@ -105,8 +105,9 @@ struct UBX_ACK_NAK ubxLastNak; #define UBX_PVT_TIMEOUT (1000) // parse incoming character stream for messages in UBX binary format -int parse_ubx_stream(uint8_t c, char *gps_rx_buffer, GPSPositionSensorData *GpsData, struct GPS_RX_STATS *gpsRxStats) +int parse_ubx_stream(uint8_t *rx, uint8_t len, char *gps_rx_buffer, GPSPositionSensorData *GpsData, struct GPS_RX_STATS *gpsRxStats) { + int ret = PARSER_INCOMPLETE; // message not (yet) complete enum proto_states { START, UBX_SY2, @@ -119,83 +120,85 @@ int parse_ubx_stream(uint8_t c, char *gps_rx_buffer, GPSPositionSensorData *GpsD UBX_CHK2, FINISHED }; - + uint8_t c; static enum proto_states proto_state = START; static uint8_t rx_count = 0; struct UBXPacket *ubx = (struct UBXPacket *)gps_rx_buffer; - switch (proto_state) { - case START: // detect protocol - if (c == UBX_SYNC1) { // first UBX sync char found - proto_state = UBX_SY2; - } - break; - case UBX_SY2: - if (c == UBX_SYNC2) { // second UBX sync char found - proto_state = UBX_CLASS; - } else { - proto_state = START; // reset state - } - break; - case UBX_CLASS: - ubx->header.class = c; - proto_state = UBX_ID; - break; - case UBX_ID: - ubx->header.id = c; - proto_state = UBX_LEN1; - break; - case UBX_LEN1: - ubx->header.len = c; - proto_state = UBX_LEN2; - break; - case UBX_LEN2: - ubx->header.len += (c << 8); - if (ubx->header.len > sizeof(UBXPayload)) { - gpsRxStats->gpsRxOverflow++; - proto_state = START; - } else { - rx_count = 0; - proto_state = UBX_PAYLOAD; - } - break; - case UBX_PAYLOAD: - if (rx_count < ubx->header.len) { - ubx->payload.payload[rx_count] = c; - if (++rx_count == ubx->header.len) { - proto_state = UBX_CHK1; + for (int i = 0; i < len; i++) { + c = rx[i]; + switch (proto_state) { + case START: // detect protocol + if (c == UBX_SYNC1) { // first UBX sync char found + proto_state = UBX_SY2; } - } else { - gpsRxStats->gpsRxOverflow++; - proto_state = START; + break; + case UBX_SY2: + if (c == UBX_SYNC2) { // second UBX sync char found + proto_state = UBX_CLASS; + } else { + proto_state = START; // reset state + } + break; + case UBX_CLASS: + ubx->header.class = c; + proto_state = UBX_ID; + break; + case UBX_ID: + ubx->header.id = c; + proto_state = UBX_LEN1; + break; + case UBX_LEN1: + ubx->header.len = c; + proto_state = UBX_LEN2; + break; + case UBX_LEN2: + ubx->header.len += (c << 8); + if (ubx->header.len > sizeof(UBXPayload)) { + gpsRxStats->gpsRxOverflow++; + proto_state = START; + } else { + rx_count = 0; + proto_state = UBX_PAYLOAD; + } + break; + case UBX_PAYLOAD: + if (rx_count < ubx->header.len) { + ubx->payload.payload[rx_count] = c; + if (++rx_count == ubx->header.len) { + proto_state = UBX_CHK1; + } + } else { + gpsRxStats->gpsRxOverflow++; + proto_state = START; + } + break; + case UBX_CHK1: + ubx->header.ck_a = c; + proto_state = UBX_CHK2; + break; + case UBX_CHK2: + ubx->header.ck_b = c; + if (checksum_ubx_message(ubx)) { // message complete and valid + parse_ubx_message(ubx, GpsData); + proto_state = FINISHED; + } else { + gpsRxStats->gpsRxChkSumError++; + proto_state = START; + } + break; + default: break; } - break; - case UBX_CHK1: - ubx->header.ck_a = c; - proto_state = UBX_CHK2; - break; - case UBX_CHK2: - ubx->header.ck_b = c; - if (checksum_ubx_message(ubx)) { // message complete and valid - parse_ubx_message(ubx, GpsData); - proto_state = FINISHED; - } else { - gpsRxStats->gpsRxChkSumError++; + + if (proto_state == START) { + ret = (ret != PARSER_COMPLETE) ? PARSER_ERROR : PARSER_COMPLETE; // parser couldn't use this byte + } else if (proto_state == FINISHED) { + gpsRxStats->gpsRxReceived++; proto_state = START; + ret = PARSER_COMPLETE; // message complete & processed } - break; - default: break; } - - if (proto_state == START) { - return PARSER_ERROR; // parser couldn't use this byte - } else if (proto_state == FINISHED) { - gpsRxStats->gpsRxReceived++; - proto_state = START; - return PARSER_COMPLETE; // message complete & processed - } - - return PARSER_INCOMPLETE; // message not (yet) complete + return ret; } @@ -464,10 +467,11 @@ static void parse_ubx_op_sys(struct UBXPacket *ubx, __attribute__((unused)) GPSP struct UBX_OP_SYSINFO *sysinfo = &ubx->payload.op_sysinfo; GPSExtendedStatusData data; - data.FlightTime = sysinfo->flightTime; - data.HeapRemaining = sysinfo->HeapRemaining; - data.IRQStackRemaining = sysinfo->IRQStackRemaining; - data.SysModStackRemaining = sysinfo->SystemModStackRemaining; + data.FlightTime = sysinfo->flightTime; + data.BoardType[0] = sysinfo->board_type; + data.BoardType[1] = sysinfo->board_revision; + memcpy(&data.FirmwareHash, &sysinfo->sha1sum, GPSEXTENDEDSTATUS_FIRMWAREHASH_NUMELEM); + memcpy(&data.FirmwareTag, &sysinfo->commit_tag_name, GPSEXTENDEDSTATUS_FIRMWARETAG_NUMELEM); data.Options = sysinfo->options; data.Status = GPSEXTENDEDSTATUS_STATUS_GPSV9; GPSExtendedStatusSet(&data); diff --git a/flight/modules/GPS/inc/NMEA.h b/flight/modules/GPS/inc/NMEA.h index 04a7dc4ce..c337abb07 100644 --- a/flight/modules/GPS/inc/NMEA.h +++ b/flight/modules/GPS/inc/NMEA.h @@ -39,6 +39,6 @@ extern bool NMEA_update_position(char *nmea_sentence, GPSPositionSensorData *GpsData); extern bool NMEA_checksum(char *nmea_sentence); -extern int parse_nmea_stream(uint8_t, char *, GPSPositionSensorData *, struct GPS_RX_STATS *); +extern int parse_nmea_stream(uint8_t *, uint8_t, char *, GPSPositionSensorData *, struct GPS_RX_STATS *); #endif /* NMEA_H */ diff --git a/flight/modules/GPS/inc/UBX.h b/flight/modules/GPS/inc/UBX.h index 1b1256e1f..6065f15d5 100644 --- a/flight/modules/GPS/inc/UBX.h +++ b/flight/modules/GPS/inc/UBX.h @@ -343,11 +343,12 @@ struct UBX_MON_VER { // OP custom messages struct UBX_OP_SYSINFO { uint32_t flightTime; - uint16_t HeapRemaining; - uint16_t IRQStackRemaining; - uint16_t SystemModStackRemaining; uint16_t options; -}; + uint8_t board_type; + uint8_t board_revision; + uint8_t commit_tag_name[26]; + uint8_t sha1sum[8]; +} __attribute__((packed)); // OP custom messages struct UBX_OP_MAG { @@ -400,7 +401,7 @@ extern struct UBX_ACK_NAK ubxLastNak; bool checksum_ubx_message(struct UBXPacket *); uint32_t parse_ubx_message(struct UBXPacket *, GPSPositionSensorData *); -int parse_ubx_stream(uint8_t, char *, GPSPositionSensorData *, struct GPS_RX_STATS *); +int parse_ubx_stream(uint8_t *rx, uint8_t len, char *, GPSPositionSensorData *, struct GPS_RX_STATS *); void load_mag_settings(); #endif /* UBX_H */ diff --git a/flight/modules/gpsp/gps9flashhandler.c b/flight/modules/gpsp/gps9flashhandler.c new file mode 100644 index 000000000..67111b5be --- /dev/null +++ b/flight/modules/gpsp/gps9flashhandler.c @@ -0,0 +1,35 @@ +/** + ****************************************************************************** + * + * @file gps9flashhandler.c + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief Flash handler for GPSV9. + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include "inc/gps9flashhandler.h" + +extern uintptr_t flash_id; +extern struct pios_flash_driver pios_jedec_flash_driver; +extern uintptr_t flash_id; + +bool flash_available() +{ + return flash_id > 0; +} diff --git a/flight/modules/gpsp/gps9gpshandler.c b/flight/modules/gpsp/gps9gpshandler.c new file mode 100644 index 000000000..13f64ede2 --- /dev/null +++ b/flight/modules/gpsp/gps9gpshandler.c @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * + * @file gps9gpshandler.c + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief handler for GPSV9 onboard ubx gps module. + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "gps9gpshandler.h" +#include "gps9protocol.h" + +uint32_t lastUnsentData = 0; +uint8_t buffer[BUFFER_SIZE]; + +void handleGPS() +{ + bool completeSentenceSent = false; + int8_t maxCount = 2; + + do { + int32_t datacounter = PIOS_UBX_DDC_GetAvailableBytes(PIOS_I2C_GPS); + if (datacounter > 0) { + uint8_t toRead = (uint32_t)datacounter > BUFFER_SIZE - lastUnsentData ? BUFFER_SIZE - lastUnsentData : (uint8_t)datacounter; + uint8_t toSend = toRead; + PIOS_UBX_DDC_ReadData(PIOS_I2C_GPS, buffer, toRead); + + uint8_t *lastSentence; + uint16_t lastSentenceLength; + completeSentenceSent = ubx_getLastSentence(buffer, toRead, &lastSentence, &lastSentenceLength); + if (completeSentenceSent) { + toSend = (uint8_t)(lastSentence - buffer + lastSentenceLength); + } else { + lastUnsentData = 0; + } + + PIOS_COM_SendBuffer(pios_com_main_id, buffer, toSend); + + if (toRead > toSend) { + // move unsent data at the beginning of buffer to be sent next time + lastUnsentData = toRead - toSend; + memcpy(buffer, (buffer + toSend), lastUnsentData); + } + } + + datacounter = PIOS_COM_ReceiveBuffer(pios_com_main_id, buffer, BUFFER_SIZE, 0); + if (datacounter > 0) { + PIOS_UBX_DDC_WriteData(PIOS_I2C_GPS, buffer, datacounter); + } + if (maxCount) { + // Note: this delay is needed as querying too quickly the UBX module's I2C(DDC) + // port causes a lot of weird issues (it stops sending nav sentences) + vTaskDelay(2 * configTICK_RATE_HZ / 1000); + } + } while (maxCount--); +} + +typedef struct { + uint8_t size; + const uint8_t *sentence; +} ubx_init_sentence; + + +void setupGPS() +{ + CfgPrtPkt cfgprt; + + cfgprt.fragments.data.portID = CFG_PRT_DATA_PORTID_DDC; + cfgprt.fragments.data.reserved0 = 0; + cfgprt.fragments.data.txReady = CFG_PRT_DATA_TXREADI_DISABLED; + cfgprt.fragments.data.mode = CFG_PRT_DATA_MODE_ADDR; + cfgprt.fragments.data.reserved3 = 0; + cfgprt.fragments.data.inProtoMask = CFG_PRT_DATA_PROTO_UBX | CFG_PRT_DATA_PROTO_NMEA | CFG_PRT_DATA_PROTO_RTCM; + cfgprt.fragments.data.outProtoMask = CFG_PRT_DATA_PROTO_UBX; + cfgprt.fragments.data.flags = 0; + cfgprt.fragments.data.reserved5 = 0; + + ubx_buildPacket(&cfgprt.packet, UBX_CFG_CLASS, UBX_CFG_PRT, sizeof(CfgPrtData)); + PIOS_UBX_DDC_WriteData(PIOS_I2C_GPS, cfgprt.packet.binarystream, sizeof(CfgPrtPkt)); +} diff --git a/flight/modules/gpsp/gps9maghandler.c b/flight/modules/gpsp/gps9maghandler.c new file mode 100644 index 000000000..5ef2e06d8 --- /dev/null +++ b/flight/modules/gpsp/gps9maghandler.c @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * + * @file gps9maghandler.c + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief handles GPSV9 onboard magnetometer and sends its data. + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include "inc/gps9protocol.h" +#define MAG_RATE_HZ 30 +extern pios_hmc5x83_dev_t onboard_mag; + +void handleMag() +{ +#ifdef PIOS_HMC5X83_HAS_GPIOS + if (!PIOS_HMC5x83_NewDataAvailable(onboard_mag)) { + return; + } +#else + static uint32_t lastUpdate = 0; + if (PIOS_DELAY_DiffuS(lastUpdate) < (1000000 / MAG_RATE_HZ)) { + return; + } + lastUpdate = PIOS_DELAY_GetRaw(); +#endif + static int16_t mag[3]; + + if (PIOS_HMC5x83_ReadMag(onboard_mag, mag) == 0) { + MagUbxPkt magPkt; + // swap axis so that if side with connector is aligned to revo side with connectors, mags data are aligned + magPkt.fragments.data.X = -mag[1]; + magPkt.fragments.data.Y = mag[0]; + magPkt.fragments.data.Z = mag[2]; + magPkt.fragments.data.status = 1; + ubx_buildPacket(&magPkt.packet, UBX_OP_CUST_CLASS, UBX_OP_MAG, sizeof(MagData)); + PIOS_COM_SendBuffer(pios_com_main_id, magPkt.packet.binarystream, sizeof(MagUbxPkt)); + return; + } +} diff --git a/flight/modules/gpsp/gpsdsysmod.c b/flight/modules/gpsp/gpsdsysmod.c new file mode 100644 index 000000000..41987db43 --- /dev/null +++ b/flight/modules/gpsp/gpsdsysmod.c @@ -0,0 +1,263 @@ +/** + ****************************************************************************** + * @addtogroup OpenPilotModules OpenPilot Modules + * @brief The OpenPilot Modules do the majority of the control in OpenPilot. The + * @ref SystemModule "System Module" starts all the other modules that then take care + * of all the telemetry and control algorithms and such. This is done through the @ref PIOS + * "PIOS Hardware abstraction layer" which then contains hardware specific implementations + * (currently only STM32 supported) + * + * @{ + * @addtogroup SystemModule GPSV9 System Module + * @brief Initializes PIOS and other modules runs monitoring, executes mag and gps handlers + * + * @{ + * + * @file gpsdsystemmod.c + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief GPS System module + * + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +// private includes +#include "inc/gpsdsysmod.h" +#include "inc/gps9maghandler.h" +#include "inc/gps9gpshandler.h" +#include "inc/gps9flashhandler.h" +#include "inc/gps9protocol.h" +#include "pios_board_info.h" + +extern uint32_t pios_com_main_id; + +// Private constants +#define SYSTEM_UPDATE_PERIOD_MS 1 +#define HB_LED_BLINK_ON_PERIOD_MS 100 +#define HB_LED_BLINK_OFF_PERIOD_MS 1900 +#define STACK_SIZE_BYTES 450 +#define STAT_UPDATE_PERIOD_MS 10000 +#define TASK_PRIORITY (tskIDLE_PRIORITY + 2) + +// Private types + +// Private variables +static xTaskHandle systemTaskHandle; +static enum { STACKOVERFLOW_NONE = 0, STACKOVERFLOW_WARNING = 1, STACKOVERFLOW_CRITICAL = 3 } stackOverflow; + + +static bool mallocFailed; +static SysUbxPkt sysPkt; + +// Private functions +static void updateStats(); +static void gpspSystemTask(void *parameters); +static void readFirmwareInfo(); +/** + * Create the module task. + * \returns 0 on success or -1 if initialization failed + */ +int32_t GPSPSystemModStart(void) +{ + // Initialize vars + stackOverflow = STACKOVERFLOW_NONE; + mallocFailed = false; + // Create system task + xTaskCreate(gpspSystemTask, (const char *)"G-Sys", STACK_SIZE_BYTES / 4, NULL, TASK_PRIORITY, &systemTaskHandle); +#ifdef PIOS_INCLUDE_WDG + PIOS_WDG_RegisterFlag(PIOS_WDG_SYSTEM); +#endif + return 0; +} + +/** + * Initialize the module, called on startup. + * \returns 0 on success or -1 if initialization failed + */ +int32_t GPSPSystemModInitialize(void) +{ + GPSPSystemModStart(); + + return 0; +} + +MODULE_INITCALL(GPSPSystemModInitialize, 0); +/** + * System task, periodically executes every SYSTEM_UPDATE_PERIOD_MS + */ +static void gpspSystemTask(__attribute__((unused)) void *parameters) +{ +#ifdef PIOS_INCLUDE_WDG + PIOS_WDG_UpdateFlag(PIOS_WDG_SYSTEM); +#endif + /* create all modules thread */ + MODULE_TASKCREATE_ALL; + + if (mallocFailed) { + // Nothing to do, this condition needs to be trapped during development. + while (true) { + ; + } + } + +#if defined(PIOS_INCLUDE_IAP) + PIOS_IAP_WriteBootCount(0); +#endif + /* Right now there is no configuration and uart speed is fixed at 57600. + * TODO: + * 1) add a tiny ubx parser on gps side to intercept CFG-RINV and use that for config storage; + * 2) second ubx parser on uart side that intercept custom configuration message and flash commands. + */ + PIOS_COM_ChangeBaud(pios_com_main_id, GPS_MODULE_DEFAULT_BAUDRATE); + setupGPS(); + uint32_t ledTimer = 0; + static TickType_t lastUpdate; + readFirmwareInfo(); + + while (1) { +#ifdef PIOS_INCLUDE_WDG + PIOS_WDG_UpdateFlag(PIOS_WDG_SYSTEM); +#endif + uint32_t ledPeriod = PIOS_DELAY_DiffuS(ledTimer) / 1000; + if (ledPeriod < HB_LED_BLINK_ON_PERIOD_MS) { + PIOS_LED_Off(PIOS_LED_HEARTBEAT); + } else { + PIOS_LED_On(PIOS_LED_HEARTBEAT); + } + if (ledPeriod > (HB_LED_BLINK_ON_PERIOD_MS + HB_LED_BLINK_OFF_PERIOD_MS)) { + ledTimer = PIOS_DELAY_GetRaw(); + } + + handleGPS(); + handleMag(); + updateStats(); + vTaskDelayUntil(&lastUpdate, SYSTEM_UPDATE_PERIOD_MS * configTICK_RATE_HZ / 1000); + } +} + + +/** + * Called periodically to update the system stats + */ +uint16_t GetFreeIrqStackSize(void) +{ + uint32_t i = 0x150; + +#if !defined(ARCH_POSIX) && !defined(ARCH_WIN32) && defined(CHECK_IRQ_STACK) + extern uint32_t _irq_stack_top; + extern uint32_t _irq_stack_end; + uint32_t pattern = 0x0000A5A5; + uint32_t *ptr = &_irq_stack_end; + +#if 1 /* the ugly way accurate but takes more time, useful for debugging */ + uint32_t stack_size = (((uint32_t)&_irq_stack_top - (uint32_t)&_irq_stack_end) & ~3) / 4; + + for (i = 0; i < stack_size; i++) { + if (ptr[i] != pattern) { + i = i * 4; + break; + } + } +#else /* faster way but not accurate */ + if (*(volatile uint32_t *)((uint32_t)ptr + IRQSTACK_LIMIT_CRITICAL) != pattern) { + i = IRQSTACK_LIMIT_CRITICAL - 1; + } else if (*(volatile uint32_t *)((uint32_t)ptr + IRQSTACK_LIMIT_WARNING) != pattern) { + i = IRQSTACK_LIMIT_WARNING - 1; + } else { + i = IRQSTACK_LIMIT_WARNING; + } +#endif +#endif /* if !defined(ARCH_POSIX) && !defined(ARCH_WIN32) && defined(CHECK_IRQ_STACK) */ + return i; +} + +/** + * Called periodically to update the system stats + */ +static void updateStats() +{ + static uint32_t lastUpdate; + + if (PIOS_DELAY_DiffuS(lastUpdate) < STAT_UPDATE_PERIOD_MS * 1000) { + return; + } + lastUpdate = PIOS_DELAY_GetRaw(); + + // Get stats and update + sysPkt.fragments.data.flightTime = xTaskGetTickCount() * portTICK_RATE_MS; + sysPkt.fragments.data.options = SYS_DATA_OPTIONS_MAG | (flash_available() ? SYS_DATA_OPTIONS_FLASH : 0); + ubx_buildPacket(&sysPkt.packet, UBX_OP_CUST_CLASS, UBX_OP_SYS, sizeof(SysData)); + PIOS_COM_SendBuffer(pios_com_main_id, sysPkt.packet.binarystream, sizeof(SysUbxPkt)); +} + +// retrieve firmware info and fill syspkt +static void readFirmwareInfo() +{ + const struct pios_board_info *bdinfo = &pios_board_info_blob; + + sysPkt.fragments.data.board_revision = bdinfo->board_rev; + sysPkt.fragments.data.board_type = bdinfo->board_type; + struct fw_version_info *fwinfo = (struct fw_version_info *)(bdinfo->fw_base + bdinfo->fw_size); + + memcpy(&sysPkt.fragments.data.commit_tag_name, &fwinfo->commit_tag_name, sizeof(sysPkt.fragments.data.commit_tag_name)); + memcpy(&sysPkt.fragments.data.sha1sum, &fwinfo->commit_tag_name, sizeof(sysPkt.fragments.data.sha1sum)); +} + +/** + * Called by the RTOS when the CPU is idle, + */ +void vApplicationIdleHook(void) +{} +/** + * Called by the RTOS when a stack overflow is detected. + */ +#define DEBUG_STACK_OVERFLOW 0 +void vApplicationStackOverflowHook(__attribute__((unused)) xTaskHandle *pxTask, + __attribute__((unused)) signed portCHAR *pcTaskName) +{ + stackOverflow = STACKOVERFLOW_CRITICAL; +#if DEBUG_STACK_OVERFLOW + static volatile bool wait_here = true; + while (wait_here) { + ; + } + wait_here = true; +#endif +} + +/** + * Called by the RTOS when a malloc call fails. + */ +#define DEBUG_MALLOC_FAILURES 0 +void vApplicationMallocFailedHook(void) +{ + mallocFailed = true; +#if DEBUG_MALLOC_FAILURES + static volatile bool wait_here = true; + while (wait_here) { + ; + } + wait_here = true; +#endif +} + +/** + * @} + * @} + */ diff --git a/flight/modules/gpsp/inc/gps9flashhandler.h b/flight/modules/gpsp/inc/gps9flashhandler.h new file mode 100644 index 000000000..a2ca13357 --- /dev/null +++ b/flight/modules/gpsp/inc/gps9flashhandler.h @@ -0,0 +1,33 @@ +/** + ****************************************************************************** + * + * @file gps9flashhandler.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief Flash handler for GPSV9 + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef GPS9FLASHHANDLER_H_ +#define GPS9FLASHHANDLER_H_ +#include + +bool flash_available(); + + +#endif /* GPS9FLASHHANDLER_H_ */ diff --git a/flight/modules/gpsp/inc/gps9gpshandler.h b/flight/modules/gpsp/inc/gps9gpshandler.h new file mode 100644 index 000000000..078c2d7d1 --- /dev/null +++ b/flight/modules/gpsp/inc/gps9gpshandler.h @@ -0,0 +1,34 @@ +/** + ****************************************************************************** + * + * @file gps9gpshandler.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief handler for GPSV9 onboard ubx gps module. + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef GPS9GPSHANDLER_H_ +#define GPS9GPSHANDLER_H_ + +#define BUFFER_SIZE 200 + +void handleGPS(); +void setupGPS(); + +#endif /* GPS9GPSHANDLER_H_ */ diff --git a/flight/modules/gpsp/inc/gps9maghandler.h b/flight/modules/gpsp/inc/gps9maghandler.h new file mode 100644 index 000000000..b85aef9d5 --- /dev/null +++ b/flight/modules/gpsp/inc/gps9maghandler.h @@ -0,0 +1,32 @@ +/**magPkt + ****************************************************************************** + * + * @file gps9maghandler.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief brief goes here. + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef GPS9MAGHANDLER_H +#define GPS9MAGHANDLER_H + +void handleMag(); + + +#endif diff --git a/flight/modules/gpsp/inc/gps9protocol.h b/flight/modules/gpsp/inc/gps9protocol.h new file mode 100644 index 000000000..59a5a23da --- /dev/null +++ b/flight/modules/gpsp/inc/gps9protocol.h @@ -0,0 +1,110 @@ +/** + ****************************************************************************** + * + * @file gpsv9protocol.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief brief goes here. + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef GPSV9PROTOCOL_H_ +#define GPSV9PROTOCOL_H_ + +#include +#include +#include +#include + +#define UBX_CFG_CLASS 0x06 +#define UBX_CFG_PRT 0x00 +#define UBX_OP_CUST_CLASS 0x99 +#define UBX_OP_SYS 0x01 +#define UBX_OP_MAG 0x02 + + +#define SYS_DATA_OPTIONS_FLASH 0x01 +#define SYS_DATA_OPTIONS_MAG 0x02 + +#define CFG_PRT_DATA_PORTID_DDC 0x00 +#define CFG_PRT_DATA_TXREADI_DISABLED 0x00 +#define CFG_PRT_DATA_PORTID_DDC 0x00 +#define CFG_PRT_DATA_MODE_ADDR (0x42 << 1) +#define CFG_PRT_DATA_PROTO_UBX 0x01 +#define CFG_PRT_DATA_PROTO_NMEA 0x02 +#define CFG_PRT_DATA_PROTO_RTCM 0x04 +#define CFG_PRT_DATA_FLAGS_EXTTIMEOUT 0x02 + + +typedef struct { + int16_t X; + int16_t Y; + int16_t Z; + uint16_t status; +} __attribute__((packed)) MagData; + +typedef union { + struct { + UBXHeader_t header; + MagData data; + UBXFooter_t footer; + } __attribute__((packed)) fragments; + UBXPacket_t packet; +} MagUbxPkt; + +typedef struct { + uint32_t flightTime; + uint16_t options; + uint8_t board_type; + uint8_t board_revision; + uint8_t commit_tag_name[26]; + uint8_t sha1sum[8]; +} __attribute__((packed)) SysData; + +typedef union { + struct { + UBXHeader_t header; + SysData data; + UBXFooter_t footer; + } fragments; + UBXPacket_t packet; +} SysUbxPkt; + + +typedef struct { + uint8_t portID; + uint8_t reserved0; + uint16_t txReady; + uint32_t mode; + uint32_t reserved3; + uint16_t inProtoMask; + uint16_t outProtoMask; + uint16_t flags; + uint16_t reserved5; +} __attribute__((packed)) CfgPrtData; + +typedef union { + struct { + UBXHeader_t header; + CfgPrtData data; + UBXFooter_t footer; + } fragments; + UBXPacket_t packet; +} CfgPrtPkt; + +#endif /* GPSV9PROTOCOL_H_ */ diff --git a/flight/modules/gpsp/inc/gpsdsysmod.h b/flight/modules/gpsp/inc/gpsdsysmod.h new file mode 100644 index 000000000..31e9847a9 --- /dev/null +++ b/flight/modules/gpsp/inc/gpsdsysmod.h @@ -0,0 +1,41 @@ +/** + ****************************************************************************** + * @addtogroup OpenPilotModules OpenPilot Modules + * @{ + * @addtogroup SystemModule GPSV9 System Module + * @{ + * + * @file gpsdsysmod.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010. + * @brief System module + * + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef GPSSYSTEMMOD_H +#define GPSSYSTEMMOD_H +#include +#include +#include +#include + +#define GPS_MODULE_DEFAULT_BAUDRATE 57600 + +int32_t GPSPSystemModInitialize(void); + +#endif // GPSSYSTEMMOD_H diff --git a/flight/pios/common/libraries/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/flight/pios/common/libraries/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h index bb8948222..0cd93b4d5 100644 --- a/flight/pios/common/libraries/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h +++ b/flight/pios/common/libraries/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h @@ -107,6 +107,12 @@ typedef unsigned long UBaseType_t; #define portSTACK_GROWTH ( -1 ) #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 8 +#define portBYTE_HEAP_ALIGNMENT 4 // this value is used to allocate heap + +// Following define allow to keep a 8 bytes alignment for stack and other RTOS structures +// while using 4 bytes alignment for the remaining heap allocations to save ram +extern void *pvPortMallocGeneric( size_t xWantedSize, size_t alignment); +#define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMallocGeneric( ( x ) , portBYTE_ALIGNMENT) ) : ( puxStackBuffer ) ) /*-----------------------------------------------------------*/ diff --git a/flight/pios/common/pios_com.c b/flight/pios/common/pios_com.c index fb6023696..07e703ba2 100644 --- a/flight/pios/common/pios_com.c +++ b/flight/pios/common/pios_com.c @@ -167,10 +167,11 @@ out_fail: return -1; } +#if defined(PIOS_INCLUDE_FREERTOS) static void PIOS_COM_UnblockRx(struct pios_com_dev *com_dev, bool *need_yield) { -#if defined(PIOS_INCLUDE_FREERTOS) static signed portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + xSemaphoreGiveFromISR(com_dev->rx_sem, &xHigherPriorityTaskWoken); if (xHigherPriorityTaskWoken != pdFALSE) { @@ -178,15 +179,19 @@ static void PIOS_COM_UnblockRx(struct pios_com_dev *com_dev, bool *need_yield) } else { *need_yield = false; } -#else - *need_yield = false; -#endif } +#else +static void PIOS_COM_UnblockRx(__attribute__((unused)) struct pios_com_dev *com_dev, bool *need_yield) +{ + *need_yield = false; +} +#endif +#if defined(PIOS_INCLUDE_FREERTOS) static void PIOS_COM_UnblockTx(struct pios_com_dev *com_dev, bool *need_yield) { -#if defined(PIOS_INCLUDE_FREERTOS) static signed portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + xSemaphoreGiveFromISR(com_dev->tx_sem, &xHigherPriorityTaskWoken); if (xHigherPriorityTaskWoken != pdFALSE) { @@ -194,10 +199,14 @@ static void PIOS_COM_UnblockTx(struct pios_com_dev *com_dev, bool *need_yield) } else { *need_yield = false; } -#else - *need_yield = false; -#endif } +#else +static void PIOS_COM_UnblockTx(__attribute__((unused)) struct pios_com_dev *com_dev, bool *need_yield) +{ + *need_yield = false; +} +#endif + static uint16_t PIOS_COM_RxInCallback(uint32_t context, uint8_t *buf, uint16_t buf_len, uint16_t *headroom, bool *need_yield) { @@ -207,9 +216,12 @@ static uint16_t PIOS_COM_RxInCallback(uint32_t context, uint8_t *buf, uint16_t b PIOS_Assert(valid); PIOS_Assert(com_dev->has_rx); - - uint16_t bytes_into_fifo = fifoBuf_putData(&com_dev->rx, buf, buf_len); - + uint16_t bytes_into_fifo; + if (buf_len == 1) { + bytes_into_fifo = fifoBuf_putByte(&com_dev->rx, buf[0]); + } else { + bytes_into_fifo = fifoBuf_putData(&com_dev->rx, buf, buf_len); + } if (bytes_into_fifo > 0) { /* Data has been added to the buffer */ PIOS_COM_UnblockRx(com_dev, need_yield); diff --git a/flight/pios/common/pios_com_msg.c b/flight/pios/common/pios_com_msg.c index 0bd40805c..3e109ce35 100644 --- a/flight/pios/common/pios_com_msg.c +++ b/flight/pios/common/pios_com_msg.c @@ -176,6 +176,30 @@ uint16_t PIOS_COM_MSG_Receive(uint32_t com_id, uint8_t *msg, uint16_t msg_len) return 0; } +/** + * Change the port speed without re-initializing + * \param[in] port COM port + * \param[in] baud Requested baud rate + * \return -1 if port not available + * \return 0 on success + */ +int32_t PIOS_COM_MSG_ChangeBaud(uint32_t com_id, uint32_t baud) +{ + struct pios_com_msg_dev *com_dev = (struct pios_com_msg_dev *)com_id; + + if (!com_dev) { + /* Undefined COM port for this board (see pios_board.c) */ + return -1; + } + + /* Invoke the driver function if it exists */ + if (com_dev->driver->set_baud) { + com_dev->driver->set_baud(com_dev->lower_id, baud); + } + + return 0; +} + #endif /* PIOS_INCLUDE_COM_MSG */ /** diff --git a/flight/pios/common/pios_hmc5x83.c b/flight/pios/common/pios_hmc5x83.c index 73b4902d9..ab9abc58d 100644 --- a/flight/pios/common/pios_hmc5x83.c +++ b/flight/pios/common/pios_hmc5x83.c @@ -401,6 +401,7 @@ static int32_t pios_hmc5x83_spi_claim_bus(pios_hmc5x83_dev_data_t *dev) if (PIOS_SPI_ClaimBus(dev->port_id) < 0) { return -1; } + PIOS_SPI_SetClockSpeed(dev->port_id, SPI_BaudRatePrescaler_16); PIOS_SPI_RC_PinSet(dev->port_id, dev->slave_num, 0); return 0; } diff --git a/flight/pios/common/pios_ubx_dcc.c b/flight/pios/common/pios_ubx_dcc.c new file mode 100644 index 000000000..fce4e0fff --- /dev/null +++ b/flight/pios/common/pios_ubx_dcc.c @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * + * @file pios_ubx_dcc.c + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief PIOS UBlox I2C(DDC) driver + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#define GPS_I2C_ADDRESS (0x42 << 1) +#define GPS_I2C_STREAM_REG 0xFF +#define GPS_I2C_STREAM_SIZE_HIGH_REG 0xFD +#define GPS_I2C_STREAM_SIZE_LOW_REG 0xFE + +int32_t PIOS_UBX_DDC_GetAvailableBytes(uint32_t i2c_id) +{ + uint8_t tmp[2]; + const uint8_t addr_buffer[1] = { GPS_I2C_STREAM_SIZE_HIGH_REG }; + struct pios_i2c_txn txn_list[] = { + { + .info = __func__, + .addr = GPS_I2C_ADDRESS, + .rw = PIOS_I2C_TXN_WRITE, + .len = 1, + .buf = (uint8_t *)addr_buffer, + } + , + { + .info = __func__, + .addr = GPS_I2C_ADDRESS, + .rw = PIOS_I2C_TXN_READ, + .len = 2, + .buf = tmp, + } + }; + + if (PIOS_I2C_Transfer(i2c_id, txn_list, NELEMENTS(txn_list)) != 0) { + return -1; + } + return (tmp[0] << 8) | tmp[1]; +} + +int32_t PIOS_UBX_DDC_ReadData(uint32_t i2c_id, uint8_t *buffer, uint8_t size) +{ + const uint8_t addr_buffer[1] = { GPS_I2C_STREAM_REG }; + const struct pios_i2c_txn txn_list[] = { + { + .info = __func__, + .addr = GPS_I2C_ADDRESS, + .rw = PIOS_I2C_TXN_WRITE, + .len = 1, + .buf = (uint8_t *)addr_buffer, + } + , + { + .info = __func__, + .addr = GPS_I2C_ADDRESS, + .rw = PIOS_I2C_TXN_READ, + .len = size, + .buf = buffer, + } + }; + + if (PIOS_I2C_Transfer(i2c_id, txn_list, NELEMENTS(txn_list)) != 0) { + return -1; + } + return 0; +} + +int32_t PIOS_UBX_DDC_WriteData(const uint32_t i2c_id, const uint8_t *buffer, const uint8_t size) +{ + const uint8_t addr_buffer[1] = { GPS_I2C_STREAM_REG }; + const struct pios_i2c_txn txn_list[] = { + { + .info = __func__, + .addr = GPS_I2C_ADDRESS, + .rw = PIOS_I2C_TXN_WRITE, + .len = 1, + .buf = (uint8_t *)addr_buffer, + } + , + { + .info = __func__, + .addr = GPS_I2C_ADDRESS, + .rw = PIOS_I2C_TXN_WRITE, + .len = size, + .buf = (uint8_t *)buffer, + } + }; + + if (PIOS_I2C_Transfer(i2c_id, txn_list, NELEMENTS(txn_list)) != 0) { + return -1; + } + return 0; +} diff --git a/flight/pios/inc/pios_board_info.h b/flight/pios/inc/pios_board_info.h index 2e549f090..596ec905a 100644 --- a/flight/pios/inc/pios_board_info.h +++ b/flight/pios/inc/pios_board_info.h @@ -21,4 +21,16 @@ struct pios_board_info { extern const struct pios_board_info pios_board_info_blob; +struct __attribute__((packed)) fw_version_info { + uint8_t magic[4]; + uint32_t commit_hash_prefix; + uint32_t timestamp; + uint8_t board_type; + uint8_t board_revision; + uint8_t commit_tag_name[26]; + uint8_t sha1sum[20]; + uint8_t uavosha1[20]; + uint8_t pad[20]; +}; + #endif /* PIOS_BOARD_INFO_H */ diff --git a/flight/pios/inc/pios_com_msg.h b/flight/pios/inc/pios_com_msg.h index f37bcb2c0..d8862e2f6 100644 --- a/flight/pios/inc/pios_com_msg.h +++ b/flight/pios/inc/pios_com_msg.h @@ -34,6 +34,7 @@ #include /* uint*_t */ /* Public Functions */ +extern int32_t PIOS_COM_MSG_ChangeBaud(uint32_t com_id, uint32_t baud); extern int32_t PIOS_COM_MSG_Send(uint32_t com_id, const uint8_t *msg, uint16_t msg_len); extern uint16_t PIOS_COM_MSG_Receive(uint32_t com_id, uint8_t *buf, uint16_t buf_len); diff --git a/flight/pios/inc/pios_i2c.h b/flight/pios/inc/pios_i2c.h index db6636f37..d3c7ceb67 100644 --- a/flight/pios/inc/pios_i2c.h +++ b/flight/pios/inc/pios_i2c.h @@ -68,6 +68,7 @@ extern int32_t PIOS_I2C_Transfer(uint32_t i2c_id, const struct pios_i2c_txn txn_ extern int32_t PIOS_I2C_Transfer_Callback(uint32_t i2c_id, const struct pios_i2c_txn txn_list[], uint32_t num_txns, void *callback); extern void PIOS_I2C_EV_IRQ_Handler(uint32_t i2c_id); extern void PIOS_I2C_ER_IRQ_Handler(uint32_t i2c_id); +extern void PIOS_I2C_IRQ_Handler(uint32_t i2c_id); extern void PIOS_I2C_GetDiagnostics(struct pios_i2c_fault_history *data, uint8_t *error_counts); #endif /* PIOS_I2C_H */ diff --git a/flight/pios/inc/pios_i2c_priv.h b/flight/pios/inc/pios_i2c_priv.h index 78c9cd0e7..ea4dbccdb 100644 --- a/flight/pios/inc/pios_i2c_priv.h +++ b/flight/pios/inc/pios_i2c_priv.h @@ -42,42 +42,6 @@ struct pios_i2c_adapter_cfg { struct stm32_irq error; }; -enum i2c_adapter_state { - I2C_STATE_FSM_FAULT = 0, /* Must be zero so undefined transitions land here */ - - I2C_STATE_BUS_ERROR, - - I2C_STATE_STOPPED, - I2C_STATE_STOPPING, - I2C_STATE_STARTING, - - I2C_STATE_R_MORE_TXN_ADDR, - I2C_STATE_R_MORE_TXN_PRE_ONE, - I2C_STATE_R_MORE_TXN_PRE_FIRST, - I2C_STATE_R_MORE_TXN_PRE_MIDDLE, - I2C_STATE_R_MORE_TXN_PRE_LAST, - I2C_STATE_R_MORE_TXN_POST_LAST, - - I2C_STATE_R_LAST_TXN_ADDR, - I2C_STATE_R_LAST_TXN_PRE_ONE, - I2C_STATE_R_LAST_TXN_PRE_FIRST, - I2C_STATE_R_LAST_TXN_PRE_MIDDLE, - I2C_STATE_R_LAST_TXN_PRE_LAST, - I2C_STATE_R_LAST_TXN_POST_LAST, - - I2C_STATE_W_MORE_TXN_ADDR, - I2C_STATE_W_MORE_TXN_MIDDLE, - I2C_STATE_W_MORE_TXN_LAST, - - I2C_STATE_W_LAST_TXN_ADDR, - I2C_STATE_W_LAST_TXN_MIDDLE, - I2C_STATE_W_LAST_TXN_LAST, - - I2C_STATE_NACK, - - I2C_STATE_NUM_STATES /* Must be last */ -}; - enum pios_i2c_adapter_magic { PIOS_I2C_DEV_MAGIC = 0xa9a9b8b8, }; @@ -99,7 +63,7 @@ struct pios_i2c_adapter { bool bus_error; bool nack; - volatile enum i2c_adapter_state curr_state; + volatile uint8_t curr_state; const struct pios_i2c_txn *first_txn; const struct pios_i2c_txn *active_txn; const struct pios_i2c_txn *last_txn; diff --git a/flight/pios/inc/pios_ubx_ddc.h b/flight/pios/inc/pios_ubx_ddc.h new file mode 100644 index 000000000..141fb2f53 --- /dev/null +++ b/flight/pios/inc/pios_ubx_ddc.h @@ -0,0 +1,33 @@ +/** + ****************************************************************************** + * + * @file pios_ubx_dcc.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2014. + * @brief PIOS UBlox I2C(DDC) driver + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef PIOS_UBX_DDC_H_ +#define PIOS_UBX_DDC_H_ + +int32_t PIOS_UBX_DDC_GetAvailableBytes(const uint32_t i2c_id); +int32_t PIOS_UBX_DDC_ReadData(const uint32_t i2c_id, uint8_t *buffer, uint8_t size); +int32_t PIOS_UBX_DDC_WriteData(const uint32_t i2c_id, const uint8_t *buffer, const uint8_t size); + +#endif /* PIOS_UBX_DDC_H_ */ diff --git a/flight/pios/inc/stm32f0xx_conf.h b/flight/pios/inc/stm32f0xx_conf.h new file mode 100644 index 000000000..0af02ca84 --- /dev/null +++ b/flight/pios/inc/stm32f0xx_conf.h @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CONF_H +#define __STM32F0XX_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Comment the line below to disable peripheral header file inclusion */ +#include "stm32f0xx_adc.h" +// #include "stm32f0xx_can.h" +// #include "stm32f0xx_cec.h" +#include "stm32f0xx_crc.h" +#include "stm32f0xx_crs.h" +// #include "stm32f0xx_comp.h" +// #include "stm32f0xx_dac.h" +#include "stm32f0xx_dbgmcu.h" +#include "stm32f0xx_dma.h" +#include "stm32f0xx_exti.h" +#include "stm32f0xx_flash.h" +#include "stm32f0xx_gpio.h" +#include "stm32f0xx_syscfg.h" +#include "stm32f0xx_i2c.h" +#include "stm32f0xx_iwdg.h" +#include "stm32f0xx_pwr.h" +#include "stm32f0xx_rcc.h" +#include "stm32f0xx_rtc.h" +#include "stm32f0xx_spi.h" +#include "stm32f0xx_tim.h" +#include "stm32f0xx_usart.h" +#include "stm32f0xx_wwdg.h" +#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F0XX_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/flight/pios/pios.h b/flight/pios/pios.h index 124dc1d8a..db25c274d 100644 --- a/flight/pios/pios.h +++ b/flight/pios/pios.h @@ -45,6 +45,7 @@ /* C Lib includes */ #include +#include #include #include #include @@ -56,6 +57,10 @@ #elif defined(STM32F4XX) #include #include +#elif defined(STM32F0) +#include +#else +#error "No Architecture defined" #endif /* PIOS board specific feature selection */ diff --git a/flight/pios/stm32f0x/inc/pios_architecture.h b/flight/pios/stm32f0x/inc/pios_architecture.h new file mode 100644 index 000000000..bf9dd7742 --- /dev/null +++ b/flight/pios/stm32f0x/inc/pios_architecture.h @@ -0,0 +1,39 @@ +/** + ****************************************************************************** + * + * @file pios_architecture.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2013. + * @brief Architecture specific macros and definitions + * -- + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef PIOS_ARCHITECTURE_H +#define PIOS_ARCHITECTURE_H + +// defines for adc +#define PIOS_ADC_VOLTAGE_SCALE 3.30f / 4096.0f + +// defines for Temp measurements +#define PIOS_ADC_STM32_TEMP_V25 1.43f /* V */ +#define PIOS_ADC_STM32_TEMP_AVG_SLOPE 4.3f /* mV/C */ +#define PIOS_CONVERT_VOLT_TO_CPU_TEMP(x) ((PIOS_ADC_STM32_TEMP_V25 - x) * 1000.0f / PIOS_ADC_STM32_TEMP_AVG_SLOPE + 25.0f) + + +#endif /* PIOS_ARCHITECTURE_H */ diff --git a/flight/pios/stm32f0x/libraries/.no-auto-format b/flight/pios/stm32f0x/libraries/.no-auto-format new file mode 100644 index 000000000..e69de29bb diff --git a/flight/pios/stm32f0x/libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/flight/pios/stm32f0x/libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf new file mode 100644 index 000000000..aabdddc5d Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h new file mode 100644 index 000000000..53c8c0111 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h @@ -0,0 +1,5111 @@ +/** + ****************************************************************************** + * @file stm32f0xx.h + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0XX_H +#define __STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32F0 device used in your + application + */ + +#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042) + /* #define STM32F030 */ + /* #define STM32F031 */ + /* #define STM32F051 */ + #define STM32F072 + /* #define STM32F042 */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +/* Old STM32F0XX definition, maintained for legacy purpose */ +#if defined(STM32F0XX) || defined(STM32F0XX_MD) + #define STM32F051 +#endif /* STM32F0XX */ + +/* Old STM32F0XX_LD definition, maintained for legacy purpose */ +#ifdef STM32F0XX_LD + #define STM32F031 +#endif /* STM32F0XX_LD */ + +/* Old STM32F0XX_HD definition, maintained for legacy purpose */ +#ifdef STM32F0XX_HD + #define STM32F072 +#endif /* STM32F0XX_HD */ + +/* Old STM32F030X6/X8 definition, maintained for legacy purpose */ +#if defined (STM32F030X8) || defined (STM32F030X6) + #define STM32F030 +#endif /* STM32F030X8 or STM32F030X6 */ + + +#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042) + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief STM32F0xx Standard Peripheral Library version number V1.3.1 + */ +#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F0XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +#if defined (STM32F051) +/****** STM32F051 specific Interrupt Numbers *************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TS_IRQn = 8, /*!< Touch sense controller Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + CEC_IRQn = 30 /*!< CEC Interrupt */ +#elif defined (STM32F031) +/****** STM32F031 specific Interrupt Numbers *************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + USART1_IRQn = 27 /*!< USART1 Interrupt */ +#elif defined (STM32F030) +/****** STM32F030 specific Interrupt Numbers *************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28 /*!< USART2 Interrupt */ +#elif defined (STM32F072) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 Interrupts */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ + USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ +#elif defined (STM32F042) + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ + USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ +#endif /* STM32F051 */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" +#include "system_stm32f0xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ +} COMP_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT 2014 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html new file mode 100644 index 000000000..5e260e58c --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html @@ -0,0 +1,228 @@ + + + + + + + + + + + + + +Release Notes for STM32F0xx CMSIS + + + + + +
+


+

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+

Release +Notes for STM32F0xx CMSIS

+

Copyright 2014 STMicroelectronics

+

+
+ + + + + + + +
+ +

Update History

V1.3.1 / 17-January-2014

+ + +

Main +Changes

+ + + +
  • TrueSTUDIO and gcc_ride7 startup files update for STM32F042 and STM32F072 devices.

V1.3.0 / 16-January-2014

+ + +

Main +Changes

+ + + +
  • Add the support of the STM32F072 and STM32F042 devices.
  • Update devices names definition to be in line with the new new STM32F0xx family devices names.
    • STM32F0XX_MD  replaced by STM32F051.
    • STM32F0XX_LD  replaced by STM32F031.
    • STM32F030x8 and STM32F030x6 replaced by STM32F030.
  • stm32f0xx.h
    • Upddate to support the new STM32F0xx family devices names.
      • STM32F0XX_MD  replaced by STM32F051
      • STM32F0XX_LD  replaced by STM32F031
    • Update IRQn enum to support the STM32F042 and STM32F072 devices.
    • Add define for HSI48_VALUE.
    • Add CAN peripheral registers declaration and bits definition.
    • Add CRS peripheral registers declaration and bits definition.
    • Update CRC_TypeDef  structure definition to add POL register.
    • Update DAC_TypeDef structure to add DAC Channel 2 configuration registers.
    • Update OB_TypeDef structure by adding DATA0, DATA1, WRP2 and WRP3 option bytes registers.
    • Rename CAL registers to CALR in the RTC_TypeDef structure.
    • Add the definition of the TIM7, USART3, USART4, CAN, CRS, DMA1_Channel6, DMA1_Channel7 and GPIOE.
    • Add bit definition for FLASH_OBR_nBOOT0, FLASH_OBR_RAM_PARITY_CHECK, FLASH_OBR_nBOOT0_SW, FLASH_OBR_DATA0 and FLASH_OBR_DATA1.
    • Add bit definition for OB_WRP2_WRP2, OB_WRP2_nWRP2, OB_WRP3_WRP3 and OB_WRP3_nWRP3.
    • Update almost bits definition to be in line with RM0091 reference manual.
  • system_stm32f0xx.c
    • SystemInit(): update to support STM32F042 and STM32F072 devices
  • Add new startup files for the STM32F042 and STM32F072 devices for the supported compilers
    • Replace startup_stm32f0xx_ld.s and startup_stm32f0xx.s by respectively startup_stm32f030.s and startup_stm32f051.s  files.
    • startup_stm32f0xx_ld.s and startup_stm32f0xx.s  files are maintained for legacy purpose.
+

V1.2.1 / 22-November-2013

+ + +

Main +Changes

+ + + +
  • stm32f0xx.h
    • Update STM32F030 devices definition:
      +
      • Remove the STM32F030X8 and STM32FO30X6 defines and replace them with the STM32F030 define
    • Update IRQn enum for STM32F030 devices
  • system_stm32f0xx.c
    • SystemInit(): update to support STM32F030 devices
  • Remove the startup files startup_stm32f030x8.s and startup_stm32f030x6.s and replace them by startup_stm32f030.s, for EWARM, MDK-ARM and Truestudio supported compilers
+

V1.2.0 / 01-August-2013

+ + +

Main +Changes

+ + + +
  • Add support of STM32F030  devices (STM32F030x8 and STM32F030x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)
  • stm32f0xx.h
    • Update STM32F0xx devices definition:
      +
      • Add new definition STM32F030X8 and STM32FO30X6 for STM32F030 devices
    • Update IRQn enum for STM32F030 devices
  • system_stm32f0xx.c
    • SystemInit(): update to support STM32F030 devices
  • Add new startup files, startup_stm32f030x8.s and startup_stm32f030x6.s, for EWARM, MDK-ARM and Truestudio supported compilers
+ + +

V1.1.1 / 31-July-2013

+ + +

Main +Changes

+ + + +
    +
  • stm32f0xx.h
    • Extend HSE_STARTUP_TIMEOUT and HSI_STARTUP_TIMEOUT values to 0x5000
    +
+ +

V1.1.0 / 10-May-2013

+

Main +Changes

+ +
    +
  • Add support of STM32F0xx Low-density devices (STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)
    • +
  • stm32f0xx.h
    • +
      +
    • Update STM32F0xx devices definition:
      +
      • +
        +
      • Define for STM32F0xx Medium-density devices changed from STM32F0XX to STM32F0XX_MD
        +
        • +
      • Add new definition STM32F0XX_LD for STM32F0xx Low-density devices
        • +
      +
    +
      +
    • Update IRQn enum for STM32F0XX_LD devices
      • +
    +
      +
    • Add new bits definition
      • +
        +
      • RCC_CFGR register: MCOPRE[0:2] and PLLNODIV
        • +
      • SYSCFG_CFGR1 register: FMP_I2C1, FMP_PA9 and FMP_PA10
        +
        • +
      +
    +
  • system_stm32f0xx.c
    • +
      +
    • SystemInit(): update to reset new bits added in RCC_CFGR register
      • +
    +
  • Add new startup files, startup_stm32f0xx_ld.s, for the supported compilers
    • +
+

V1.0.2 / 13-July-2012

Main +Changes

+
  • stm32f0xx.h
    • Fix issue with gcc_ride7 startup file

V1.0.1 / 20-April-2012

Main +Changes

+
  • stm32f0xx.h
    • Add reference to STM32F050xx (Flash memory up to 32 Kbytes) and STM32F051xx (Flash memory up to 64 Kbytes) devices
    • RTC register bits definition: remove reference to Tamper3

V1.0.0 / 23-March-2012

Main +Changes

+
  • First official release for STM32F0xx devices
  • All source files: license disclaimer text update and add link to the License file on ST Internet
  • stm32f0xx.h
    • change MCO bits value:
      • change RCC_CFGR_MCO_HSI14 value from 0x03000000 to 0x01000000
      • Add RCC_CFGR_MCO_LSI having value 0x02000000
      • Add RCC_CFGR_MCO_LSE having value 0x03000000
    • Add new bit RCC_CSR_V18PWRRSTF having value 0x00800000
    • TIM_OR bits definition values corrected
    • Rename ADC_ISR_EOS to ADC_ISR_EOSEQ
    • Rename ADC_IER_EOSIE to ADC_IER_EOSEQIE
    • Rename ADC_CFGR1_AUTDLY to ADC_CFGR1_WAIT
    • Rename option bit FLASH_OBR_BOOT1 to FLASH_OBR_nBOOT1
    • Rename FLASH_OBR_VDDA_ANALOG to FLASH_OBR_VDDA_MONITOR
    • Add Flash and OB keys (removed from Flash driver)
  • system_stm32f0xx.c
    • SetSysClock() function: code optimized 
    • Miscellaneous formatting
+

V1.0.0RC1 / 27-January-2012

+

Main +Changes

+ +
    +
  • Official version (V1.0.0) Release Candidate 1
    • +
  • All source +files: update disclaimer to add reference to the new license agreement
    • +
  • Update all peripherals bits definitions
    +
    • +
+ +
    +
+

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. + +
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s new file mode 100644 index 000000000..9bef3687a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s @@ -0,0 +1,280 @@ +/** + ****************************************************************************** + * @file startup_stm32f030.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F030 Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word 0 + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word 0 + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word 0 + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word 0 + .word 0 + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s new file mode 100644 index 000000000..f4454d0ad --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file startup_stm32f031.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F031 Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word 0 + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word 0 + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s new file mode 100644 index 000000000..0255c256b --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file startup_stm32f042.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F042 Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_VDDIO2_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_CRS_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TSC_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word 0 + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word 0 + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word CEC_CAN_IRQHandler + .word USB_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s new file mode 100644 index 000000000..d44725aa9 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s @@ -0,0 +1,295 @@ +/** + ****************************************************************************** + * @file startup_stm32f051.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F051 Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TS_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_COMP_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_DAC_IRQHandler + .word 0 + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word CEC_IRQHandler + .word 0 + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TS_IRQHandler + .thumb_set TS_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s new file mode 100644 index 000000000..2a270e50b --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file startup_stm32f072.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F072 Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_VDDIO2_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_CRS_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TSC_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_6_7_IRQHandler + .word ADC1_COMP_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_4_IRQHandler + .word CEC_CAN_IRQHandler + .word USB_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_6_7_IRQHandler + .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s new file mode 100644 index 000000000..36b18c70e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file startup_stm32f0xx.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F0xx Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TS_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_COMP_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_DAC_IRQHandler + .word 0 + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word CEC_IRQHandler + .word 0 + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TS_IRQHandler + .thumb_set TS_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s new file mode 100644 index 000000000..aa59dabc1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s @@ -0,0 +1,273 @@ +/** + ****************************************************************************** + * @file startup_stm32f0xx_ld.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F031 devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word 0 + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word 0 + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s new file mode 100644 index 000000000..187f5d774 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s @@ -0,0 +1,244 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f030.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F030 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + + +WWDG_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s new file mode 100644 index 000000000..d6b1e6ca1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s @@ -0,0 +1,239 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f031.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F031 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s new file mode 100644 index 000000000..ebf6eefef --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s @@ -0,0 +1,254 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f042.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F042 Devices vector table for +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4, Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s new file mode 100644 index 000000000..1e194f5d2 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s @@ -0,0 +1,257 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f051.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F051 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TS_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TS_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TS_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s new file mode 100644 index 000000000..f1a85a3b8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s @@ -0,0 +1,264 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f072.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F072 Devices vector table for +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_4_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_4_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s new file mode 100644 index 000000000..7e2bb2b11 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s @@ -0,0 +1,257 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f0xx.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F051 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TS_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TS_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TS_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s new file mode 100644 index 000000000..22a98073a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s @@ -0,0 +1,239 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f0xx_ld.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F0031 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s new file mode 100644 index 000000000..f15783405 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s @@ -0,0 +1,294 @@ +/** + ****************************************************************************** + * @file startup_stm32f0xx.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F030 Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word 0 + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word 0 + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word 0 + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F0xx devices. */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s new file mode 100644 index 000000000..7cca76391 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s @@ -0,0 +1,287 @@ +/** + ****************************************************************************** + * @file startup_stm32f0xx.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F031 Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word 0 + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word 0 + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F0xx devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s new file mode 100644 index 000000000..598290c51 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s @@ -0,0 +1,302 @@ +/** + ****************************************************************************** + * @file startup_stm32f042.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F042 Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_VDDIO2_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_CRS_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TSC_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word 0 + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word 0 + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word CEC_CAN_IRQHandler + .word USB_IRQHandler + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F0xx devices. */ + + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s new file mode 100644 index 000000000..b0bb312cd --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file startup_stm32f0xx.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F051 Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TS_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_COMP_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_DAC_IRQHandler + .word 0 + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word CEC_IRQHandler + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F0xx devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TS_IRQHandler + .thumb_set TS_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s new file mode 100644 index 000000000..21bb90cba --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file startup_stm32f0xx.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F072 Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + + .word WWDG_IRQHandler + .word PVD_VDDIO2_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_CRS_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TSC_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_6_7_IRQHandler + .word ADC1_COMP_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_4_IRQHandler + .word CEC_CAN_IRQHandler + .word USB_IRQHandler + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F0xx devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_6_7_IRQHandler + .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s new file mode 100644 index 000000000..3ed8d9d4c --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file startup_stm32f0xx.s + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief STM32F0xx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word TS_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Channel4_5_IRQHandler + .word ADC1_COMP_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_DAC_IRQHandler + .word 0 + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word CEC_IRQHandler + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F0xx devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TS_IRQHandler + .thumb_set TS_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s new file mode 100644 index 000000000..f2e56032d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s @@ -0,0 +1,300 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f030.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F030 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s new file mode 100644 index 000000000..a8718ca6d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s @@ -0,0 +1,288 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f031.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F031 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s new file mode 100644 index 000000000..1ebe0466a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s @@ -0,0 +1,318 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f042.s +;* Author : MCD Appl&ication Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F042 Devices Devices vector table for +;* EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK CEC_CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_CAN_IRQHandler + B CEC_CAN_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s new file mode 100644 index 000000000..29c1e7ae4 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s @@ -0,0 +1,333 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f051.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F051 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TS_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + DCD 0 ; Reserved + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK TS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TS_IRQHandler + B TS_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s new file mode 100644 index 000000000..c01281d93 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s @@ -0,0 +1,346 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f072.s +;* Author : MCD Appl&ication Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F072 Devices Devices vector table for +;* EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_6_7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_6_7_IRQHandler + B DMA1_Channel4_5_6_7_IRQHandler + + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_IRQHandler + B USART3_4_IRQHandler + + + PUBWEAK CEC_CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_CAN_IRQHandler + B CEC_CAN_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s new file mode 100644 index 000000000..27d799f02 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s @@ -0,0 +1,333 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f0xx.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F051 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TS_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + DCD 0 ; Reserved + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK TS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TS_IRQHandler + B TS_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s new file mode 100644 index 000000000..595fa8df1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s @@ -0,0 +1,288 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f0xx_ld.s +;* Author : MCD Application Team +;* Version : V1.3.1 +;* Date : 17-January-2014 +;* Description : STM32F031 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c new file mode 100644 index 000000000..e05ebe275 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c @@ -0,0 +1,358 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F0xx devices, + * and is generated by the clock configuration tool + * STM32F0xx_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * System Clock Configuration + *============================================================================= + * System Clock source | PLL(HSE) + *----------------------------------------------------------------------------- + * SYSCLK | 48000000 Hz + *----------------------------------------------------------------------------- + * HCLK | 48000000 Hz + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSE Frequency | 8000000 Hz + *----------------------------------------------------------------------------- + * PLL MUL | 6 + *----------------------------------------------------------------------------- + * VDD | 3.3 V + *----------------------------------------------------------------------------- + * Flash Latency | 1 WS + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 48000000; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + +#if defined (STM32F031) || defined (STM32F072) || defined (STM32F042) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80C; +#endif /* STM32F031*/ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; + + /* PLL configuration = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/system_stm32f0xx.c b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/system_stm32f0xx.c new file mode 100644 index 000000000..4f1bf94c4 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Device/ST/STM32F0xx/Source/system_stm32f0xx.c @@ -0,0 +1,356 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @version V1.0.1 + * @date 07-September-2014 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F0xx devices, + * and is generated by the clock configuration tool + * STM32f0xx_Clock_Configuration_V1.0.1.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 48000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 48000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 8000000 + *---------------------------------------------------------------------------- + * PLLMUL | 6 + *----------------------------------------------------------------------------- + * PREDIV | 1 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 1 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 48000000; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; + + /* HCLK = SYSCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK = HCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; + + /* PLL configuration */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png new file mode 100644 index 000000000..a542159e7 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png new file mode 100644 index 000000000..1cacaf20a Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png new file mode 100644 index 000000000..2056b7e74 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html new file mode 100644 index 000000000..204211f53 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html @@ -0,0 +1,141 @@ + + + + + +CMSIS-CORE: MISRA-C:2004 Compliance Exceptions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
MISRA-C:2004 Compliance Exceptions
+
+
+

CMSIS-CORE uses the common coding rules for CMSIS components that are documented under Introduction .

+

CMSIS-CORE violates the following MISRA-C:2004 rules:

+
    +
  • Required Rule 8.5, object/function definition in header file.
    + Violated since function definitions in header files are used to allow 'inlining'.
    • +
+
    +
  • Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Violated since unions are used for effective representation of core registers.
    • +
+
    +
  • Advisory Rule 19.7, Function-like macro defined.
    + Violated since function-like macros are used to allow more efficient code.
    • +
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html new file mode 100644 index 000000000..66724ef61 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html @@ -0,0 +1,302 @@ + + + + + +CMSIS-CORE: Register Mapping + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Register Mapping
+
+
+

The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CMSIS Register Name Cortex-M3 and Cortex-M4 Cortex-M0 and Cortex-M0+ Register Name
Nested Vectored Interrupt Controller (NVIC) Register Access
NVIC->ISER[] NVIC_ISER0..7 ISER Interrupt Set-Enable Registers
NVIC->ICER[] NVIC_ICER0..7 ICER Interrupt Clear-Enable Registers
NVIC->ISPR[] NVIC_ISPR0..7 ISPR Interrupt Set-Pending Registers
NVIC->ICPR[] NVIC_ICPR0..7 ICPR Interrupt Clear-Pending Registers
NVIC->IABR[] NVIC_IABR0..7 - Interrupt Active Bit Register
NVIC->IP[] NVIC_IPR0..59 IPR0..7 Interrupt Priority Register
NVIC->STIR STIR - Software Triggered Interrupt Register
System Control Block (SCB) Register Access
SCB->CPUID CPUID CPUID CPUID Base Register
SCB->ICSR ICSR ICSR Interrupt Control and State Register
SCB->VTOR VTOR - Vector Table Offset Register
SCB->AIRCR AIRCR AIRCR Application Interrupt and Reset Control Register
SCB->SCR SCR SCR System Control Register
SCB->CCR CCR CCR Configuration and Control Register
SCB->SHP[] SHPR1..3 SHPR2..3 System Handler Priority Registers
SCB->SHCSR SHCSR SHCSR System Handler Control and State Register
SCB->CFSR CFSR - Configurable Fault Status Registers
SCB->HFSR HFSR - HardFault Status Register
SCB->DFSR DFSR - Debug Fault Status Register
SCB->MMFAR MMFAR - MemManage Fault Address Register
SCB->BFAR BFAR - BusFault Address Register
SCB->AFSR AFSR - Auxiliary Fault Status Register
SCB->PFR[] ID_PFR0..1 - Processor Feature Registers
SCB->DFR ID_DFR0 - Debug Feature Register
SCB->ADR ID_AFR0 - Auxiliary Feature Register
SCB->MMFR[] ID_MMFR0..3 - Memory Model Feature Registers
SCB->ISAR[] ID_ISAR0..4 - Instruction Set Attributes Registers
SCB->CPACR CPACR - Coprocessor Access Control Register
System Control and ID Registers not in the SCB (SCnSCB) Register Access
SCnSCB->ICTR ICTR - Interrupt Controller Type Register
SCnSCB->ACTLR ACTLR - Auxiliary Control Register
System Timer (SysTick) Control and Status Register Access
SysTick->CTRL STCSR SYST_CSR SysTick Control and Status Register
SysTick->LOAD STRVR SYST_RVR SysTick Reload Value Register
SysTick->VAL STCVR SYST_CVR SysTick Current Value Register
SysTick->CALIB STCR SYST_CALIB SysTick Calibaration Value Register
Data Watchpoint and Trace (DWT) Register Access
DWT->CTRL DWT_CTRL - Control Register
DWT->CYCCNT DWT_CYCCNT - Cycle Count Register
DWT->CPICNT DWT_CPICNT - CPI Count Register
DWT->EXCCNT DWT_EXCCNT - Exception Overhead Count Register
DWT->SLEEPCNT DWT_SLEEPCNT - Sleep Count Register
DWT->LSUCNT DWT_LSUCNT - LSU Count Register
DWT->FOLDCNT DWT_FOLDCNT - Folded-instruction Count Register
DWT->PCSR DWT_PCSR - Program Counter Sample Register
DWT->COMP0..3 DWT_COMP0..3 - Comparator Register 0..3
DWT->MASK0..3 DWT_MASK0..3 - Mask Register 0..3
DWT->FUNCTION0..3 DWT_FUNCTION0..3 - Function Register 0..3
Instrumentation Trace Macrocell (ITM) Register Access
ITM->PORT[] ITM_STIM0..31 - Stimulus Port Registers
ITM->TER ITM_TER - Trace Enable Register
ITM->TPR ITM_TPR - ITM Trace Privilege Register
ITM->TCR ITM_TCR - Trace Control Register
Trace Port Interface (TPIU) Register Access
TPI->SSPSR TPIU_SSPR - Supported Parallel Port Size Register
TPI->CSPSR TPIU_CSPSR - Current Parallel Port Size Register
TPI->ACPR TPIU_ACPR - Asynchronous Clock Prescaler Register
TPI->SPPR TPIU_SPPR - Selected Pin Protocol Register
TPI->FFSR TPIU_FFSR - Formatter and Flush Status Register
TPI->FFCR TPIU_FFCR - Formatter and Flush Control Register
TPI->FSCR TPIU_FSCR - Formatter Synchronization Counter Register
TPI->TRIGGER TRIGGER - TRIGGER
TPI->FIFO0 FIFO data 0 - Integration ETM Data
TPI->ITATBCTR2 ITATBCTR2 - ITATBCTR2
TPI->ITATBCTR0 ITATBCTR0 - ITATBCTR0
TPI->FIFO1 FIFO data 1 - Integration ITM Data
TPI->ITCTRL TPIU_ITCTRL - Integration Mode Control
TPI->CLAIMSET CLAIMSET - Claim tag set
TPI->CLAIMCLR CLAIMCLR - Claim tag clear
TPI->DEVID TPIU_DEVID - TPIU_DEVID
TPI->DEVTYPE TPIU_DEVTYPE - TPIU_DEVTYPE
Memory Protection Unit (MPU) Register Access
MPU->TYPE MPU_TYPE - MPU Type Register
MPU->CTRL MPU_CTRL - MPU Control Register
MPU->RNR MPU_RNR - MPU Region Number Register
MPU->RBAR MPU_RBAR - MPU Region Base Address Register
MPU->RASR MPU_RASR - MPU Region Attribute and Size Register
MPU->RBAR_A1..3 MPU_RBAR_A1..3 - MPU alias Register
MPU->RSAR_A1..3 MPU_RSAR_A1..3 - MPU alias Register
Floating Point Unit (FPU) Register Access [only Cortex-M4 with FPU]
FPU->FPCCR FPCCR - FP Context Control Register
FPU->FPCAR FPCAR - FP Context Address Register
FPU->FPDSCR FPDSCR - FP Default Status Control Register
FPU->MVFR0..1 MVFR0..1 - Media and VFP Feature Registers
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_templates_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_templates_pg.html new file mode 100644 index 000000000..e49ed606f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_templates_pg.html @@ -0,0 +1,212 @@ + + + + + +CMSIS-CORE: Template Files + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Template Files
+
+
+

ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliancy. These template files include the following:

+
    +
  • Register names of the Core Peripherals and names of the Core Exception Vectors.
    • +
  • Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4)
    • +
  • Generic startup code and system configuration code.
    • +
+

The detailed file structure of the CMSIS-CORE is shown in the following picture.

+
+CMSIS_CORE_Files.png +
+CMSIS-CORE File Structure
+

+Template Files

+

The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:

+
    +
  • Device Peripheral Access Layer that provides definitions for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals.
    • +
  • Interrupt vectors in the startup file that are device specific.
    • +
+ + + + + + + + + + + + + + + + + +
Template File Description
".\Device_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s" Startup file template for ARM C/C++ Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s" Startup file template for GNU GCC ARM Embedded Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\G++\startup_Device.s" Startup file template for GNU Sourcery G++ Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s" Startup file template for IAR C/C++ Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\system_Device.c" Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).
".\Device_Template_Vendor\Vendor\Device\Include\Device.h" Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.
".\Device_Template_Vendor\Vendor\Device\Include\system_Device.h" Generic system device configuration include file.
+

In addition ARM provides the following core header files that do not need any modifications.

+ + + + + + + + + + + +
Core Header Files Description
core_<cpu>.h Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:
    +
  • core_cm0.h: for the Cortex-M0 processor
    • +
  • core_cm0plus.h: for the Cortex-M0+ processor
    • +
  • core_cm3.h: for the Cortex-M0 processor
    • +
  • core_cm4.h: for the Cortex-M0 processor
    • +
  • core_sc000.h: for the SecurCore SC000 processor
    • +
  • core_sc300.h: for the SecurCore SC300 processor
    • +
+
core_cmInstr.h Defines intrinsic functions to access special Cortex-M instructions.
core_cmFunc.h Defines functions to access the Cortex-M core peripherals.
core_cm4_simd.h Defines intrinsic functions to access the Cortex-M4 SIMD instructions.
+

+Adaption of Template Files to Devices

+

Copy the complete folder including files and replace:

+
    +
  • folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
    • +
  • folder name 'Device' with the specific device name e.g.: LPC17xx.
    • +
  • in the filenames 'Device' with the specific device name e.g.: LPC17xx.
    • +
+

Each template file contains comments that start with ToDo: that describe a required modification. The template files contain placeholders:

+ + + + + + + + + + + +
Placeholder Replaced with
<Device> the specific device name or device family name; i.e. LPC17xx.
<DeviceInterrupt> a specific interrupt name of the device; i.e. TIM1 for Timer 1.
<DeviceAbbreviation> short name or abbreviation of the device family; i.e. LPC.
Cortex-M# the specific Cortex-M processor name; i.e. Cortex-M3.
+

The adaption of the template files is described in detail on the following pages:

+ +
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_templates_pg.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_templates_pg.js new file mode 100644 index 000000000..972e1a105 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_templates_pg.js @@ -0,0 +1,19 @@ +var _templates_pg = +[ + [ "Template Files", "_templates_pg.html#template_files_sec", null ], + [ "Adaption of Template Files to Devices", "_templates_pg.html#adapt_template_files_sec", null ], + [ "Startup File startup_.s", "startup_s_pg.html", [ + [ "startup_Device.s Template File", "startup_s_pg.html#startup_s_sec", null ] + ] ], + [ "System Configuration Files system_.c and system_.h", "system_c_pg.html", [ + [ "system_Device.c Template File", "system_c_pg.html#system_Device_sec", null ], + [ "system_Device.h Template File", "system_c_pg.html#system_Device_h_sec", null ] + ] ], + [ "Device Header File ", "device_h_pg.html", [ + [ "Interrupt Number Definition", "device_h_pg.html#interrupt_number_sec", null ], + [ "Configuration of the Processor and Core Peripherals", "device_h_pg.html#core_config_sect", null ], + [ "CMSIS Version and Processor Information", "device_h_pg.html#core_version_sect", null ], + [ "Device Peripheral Access Layer", "device_h_pg.html#device_access", null ], + [ "Device.h Template File", "device_h_pg.html#device_h_sec", null ] + ] ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html new file mode 100644 index 000000000..d4271fcc5 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html @@ -0,0 +1,164 @@ + + + + + +CMSIS-CORE: Using CMSIS with generic ARM Processors + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Using CMSIS with generic ARM Processors
+
+
+

ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.

+ + + + + + + + + + + + + + + +
Folder Processor Description
".\Device\ARM\ARMCM0" Cortex-M0 Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>.
".\Device\ARM\ARMCM0plus" Cortex-M0+ Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>.
".\Device\ARM\ARMCM3" Cortex-M3 Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>.
".\Device\ARM\ARMCM4" Cortex-M4 Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>.
".\Device\ARM\ARMSC000" SecurCore SC000 Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>.
".\Device\ARM\ARMSC300" SecurCore SC300 Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>.
+

+Create generic Libraries with CMSIS

+

The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The CMSIS-DSP Libraries are an example for such a generic library.

+

To build a generic Library set the define __CMSIS_GENERIC and include the relevant core_<cpu>.h CMSIS CPU & Core Access header file for the processor. The define __CMSIS_GENERIC disables device-dependent features such as the SysTick timer and the Interrupt System. Refer to Configuration of the Processor and Core Peripherals for a list of the available core_<cpu>.h header files.

+

Example:

+

The following code section shows the usage of the core_<cpu>.h header files to build a generic library for Cortex-M0, Cortex-M3, or Cortex-M4. To select the processor the source code uses the define CORTEX_M4, CORTEX_M3, or CORTEX_M0. By using this header file, the source code can access the functions for Core Register Access, Intrinsic Functions for CPU Instructions, Intrinsic Functions for SIMD Instructions [only Cortex-M4], and Debug Access.

+
#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+
#if defined (CORTEX_M4)
+
#include "core_cm4.h"
+
#elif defined (CORTEX_M3)
+
#include "core_cm3.h"
+
#elif defined (CORTEX_M0)
+
#include "core_cm0.h"
+
#elif defined (CORTEX_M0PLUS)
+
#include "core_cm0plus.h"
+
#else
+
#error "Processor not specified or unsupported."
+
#endif
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using_pg.html new file mode 100644 index 000000000..c302e2692 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using_pg.html @@ -0,0 +1,213 @@ + + + + + +CMSIS-CORE: Using CMSIS in Embedded Applications + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Using CMSIS in Embedded Applications
+
+
+

To use the CMSIS-CORE the following files are added to the embedded application:

+ +
Note
The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.
+

The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.

+

The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.

+

The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:

+ +
+CMSIS_CORE_Files_user.png +
+CMSIS-CORE User Files
+

The CMSIS-CORE are device specific. In addition, the Startup File startup_<device>.s is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device. Using CMSIS with generic ARM Processors explains how to use CMSIS-CORE for ARM processors.

+

For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:

+ + + + + + + + + + + +
File Description
".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants.
".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families.
".\ARM\INC\ST\STM32F10x\stm32f10x.h" Device Header File <device.h> for the STM32F10x device families.
".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" system_Device.h Template File for the STM32F10x device families.
+
Note
The silicon vendors create these device-specific CMSIS-CORE files based on Template Files provide by ARM.
+

Thereafter, the functions described under Reference can be used in the application.

+

A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.

+
#include <stm32f10x.h> // File name depends on device used
+
+
uint32_t volatile msTicks; // Counter for millisecond Interval
+
+
void SysTick_Handler (void) { // SysTick Interrupt Handler
+
msTicks++; // Increment Counter
+
}
+
+
void WaitForTick (void) {
+
uint32_t curTicks;
+
+
curTicks = msTicks; // Save Current SysTick Value
+
while (msTicks == curTicks) { // Wait for next SysTick Interrupt
+
__WFE (); // Power-Down until next Event/Interrupt
+
}
+
}
+
+
void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler
+
; // Add user code here
+
}
+
+
void timer1_init(int frequency) { // Set up Timer (device specific)
+
NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority
+
NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt
+
}
+
+
+
void Device_Initialization (void) { // Configure & Initialize MCU
+
if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec
+
: // Handle Error
+
}
+
timer1_init (); // setup device-specific timer
+
}
+
+
+
// The processor clock is initialized by CMSIS startup + system file
+
void main (void) { // user application starts here
+
Device_Initialization (); // Configure & Initialize MCU
+
while (1) { // Endless Loop (the Super-Loop)
+
__disable_irq (); // Disable all interrupts
+
Get_InputValues (); // Read Values
+
__enable_irq (); // Enable all interrupts
+
Calculation_Response (); // Calculate Results
+
Output_Response (); // Output Results
+
WaitForTick (); // Synchronize to SysTick Timer
+
}
+
}
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using_pg.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using_pg.js new file mode 100644 index 000000000..1cfa69eed --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/_using_pg.js @@ -0,0 +1,6 @@ +var _using_pg = +[ + [ "Using CMSIS with generic ARM Processors", "_using__a_r_m_pg.html", [ + [ "Create generic Libraries with CMSIS", "_using__a_r_m_pg.html#Using_ARM_Lib_sec", null ] + ] ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/annotated.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/annotated.html new file mode 100644 index 000000000..0589939f9 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/annotated.html @@ -0,0 +1,151 @@ + + + + + +CMSIS-CORE: Data Structures + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Data Structures
+
+
+
Here are the data structures with brief descriptions:
+ + + + + + + + + + + + + + + +
oCAPSR_TypeUnion type to access the Application Program Status Register (APSR)
oCCONTROL_TypeUnion type to access the Control Registers (CONTROL)
oCCoreDebug_TypeStructure type to access the Core Debug Register (CoreDebug)
oCDWT_TypeStructure type to access the Data Watchpoint and Trace Register (DWT)
oCFPU_TypeStructure type to access the Floating Point Unit (FPU)
oCIPSR_TypeUnion type to access the Interrupt Program Status Register (IPSR)
oCITM_TypeStructure type to access the Instrumentation Trace Macrocell Register (ITM)
oCMPU_TypeStructure type to access the Memory Protection Unit (MPU)
oCNVIC_TypeStructure type to access the Nested Vectored Interrupt Controller (NVIC)
oCSCB_TypeStructure type to access the System Control Block (SCB)
oCSCnSCB_TypeStructure type to access the System Control and ID Register not in the SCB
oCSysTick_TypeStructure type to access the System Timer (SysTick)
oCTPI_TypeStructure type to access the Trace Port Interface Register (TPI)
\CxPSR_TypeUnion type to access the Special-Purpose Program Status Registers (xPSR)
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/annotated.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/annotated.js new file mode 100644 index 000000000..fa4ad8710 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/annotated.js @@ -0,0 +1,17 @@ +var annotated = +[ + [ "APSR_Type", "union_a_p_s_r___type.html", "union_a_p_s_r___type" ], + [ "CONTROL_Type", "union_c_o_n_t_r_o_l___type.html", "union_c_o_n_t_r_o_l___type" ], + [ "CoreDebug_Type", "struct_core_debug___type.html", "struct_core_debug___type" ], + [ "DWT_Type", "struct_d_w_t___type.html", "struct_d_w_t___type" ], + [ "FPU_Type", "struct_f_p_u___type.html", "struct_f_p_u___type" ], + [ "IPSR_Type", "union_i_p_s_r___type.html", "union_i_p_s_r___type" ], + [ "ITM_Type", "struct_i_t_m___type.html", "struct_i_t_m___type" ], + [ "MPU_Type", "struct_m_p_u___type.html", "struct_m_p_u___type" ], + [ "NVIC_Type", "struct_n_v_i_c___type.html", "struct_n_v_i_c___type" ], + [ "SCB_Type", "struct_s_c_b___type.html", "struct_s_c_b___type" ], + [ "SCnSCB_Type", "struct_s_cn_s_c_b___type.html", "struct_s_cn_s_c_b___type" ], + [ "SysTick_Type", "struct_sys_tick___type.html", "struct_sys_tick___type" ], + [ "TPI_Type", "struct_t_p_i___type.html", "struct_t_p_i___type" ], + [ "xPSR_Type", "unionx_p_s_r___type.html", "unionx_p_s_r___type" ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/bc_s.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/bc_s.png new file mode 100644 index 000000000..66f8e9a20 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/bc_s.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/bdwn.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/bdwn.png new file mode 100644 index 000000000..d400769b5 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/bdwn.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/check.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/check.png new file mode 100644 index 000000000..094e59cf5 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/check.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/classes.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/classes.html new file mode 100644 index 000000000..0f13db4c6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/classes.html @@ -0,0 +1,157 @@ + + + + + +CMSIS-CORE: Data Structure Index + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Data Structure Index
+
+
+
A | C | D | F | I | M | N | S | T | X
+ + + + + + + + + + + +
  A  
+
  D  
+		ITM_Type   
  S  
+
  X  
+
  M  
+
APSR_Type   DWT_Type   SCB_Type   xPSR_Type   
  C  
+
  F  
+		MPU_Type   SCnSCB_Type   
  N  
+		SysTick_Type   
CONTROL_Type   FPU_Type   
  T  
+
CoreDebug_Type   
  I  
+		NVIC_Type   
TPI_Type   
IPSR_Type   
+
A | C | D | F | I | M | N | S | T | X
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/closed.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/closed.png new file mode 100644 index 000000000..ccbcf6292 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/closed.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/cmsis.css b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/cmsis.css new file mode 100644 index 000000000..a9ec718c0 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/cmsis.css @@ -0,0 +1,1256 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 13px; + line-height: 1.3; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + border: 1px solid #2D4068; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + height: 28px; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + + + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; +} + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #354E81; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + width: 100%; + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + width: 100%; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + margin-left: 5px; + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 7px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/device_h_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/device_h_pg.html new file mode 100644 index 000000000..8e0a50b61 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/device_h_pg.html @@ -0,0 +1,526 @@ + + + + + +CMSIS-CORE: Device Header File <device.h> + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Device Header File <device.h>
+
+
+

The Device Header File <device.h> contains the following sections that are device specific:

+
    +
  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • +
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
    • +
  • Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
    • +
+

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

+

+Interrupt Number Definition

+

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

+
    +
  • Negative IRQn values represent processor core exceptions (internal interrupts).
    • +
  • Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.
    • +
+

Example:

+

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

+
typedef enum IRQn
+
{
+
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+
NonMaskableInt_IRQn = -14,
+
HardFault_IRQn = -13,
+
SVCall_IRQn = -5,
+
PendSV_IRQn = -2,
+
SysTick_IRQn = -1,
+
/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
+
WAKEUP0_IRQn = 0,
+
WAKEUP1_IRQn = 1,
+
WAKEUP2_IRQn = 2,
+
: :
+
: :
+
EINT1_IRQn = 30,
+
EINT0_IRQn = 31,
+
} IRQn_Type;
+

+Configuration of the Processor and Core Peripherals

+

The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

+

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

+

core_cm0.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm0plus.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0PLUS_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm3.h

+ + + + + + + + + + + +
#define Value Range Default Description
__CM3_REV 0x0101 | 0x0200 0x0200 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm4.h

+ + + + + + + + + + + + + +
#define Value Range Default Description
__CM4_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_sc000.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC000_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_sc300.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC300_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

Example

+

The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

+
#define __CM4_REV 0x0001 /* Core revision r0p1 */
+
#define __MPU_PRESENT 1 /* MPU present or not */
+
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
#define __FPU_PRESENT 1 /* FPU present or not */
+
.
+
.
+
#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
+

+CMSIS Version and Processor Information

+

Defines in the core_cpu.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

+

core_cm0.h

+
#define __CM0_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __CM0_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+
__CM0_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x00) /* Cortex-M Core */
+

core_cm0plus.h

+
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16) | \
+
__CM0P_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x00) /* Cortex-M Core */
+

core_cm3.h

+
#define __CM3_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __CM3_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+
__CM3_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x03) /* Cortex-M Core */
+

core_cm4.h

+
#define __CM4_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __CM4_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+
__CM4_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x04) /* Cortex-M Core */
+

core_sc000.h

+
#define __SC000_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __SC000_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+
__SC000_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_SC (0) /* Cortex secure core */
+

core_sc300.h

+
#define __SC300_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __SC300_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+
__SC300_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_SC (300) /* Cortex secure core */
+

+Device Peripheral Access Layer

+

The Device Header File <device.h> contains for each peripheral:

+
    +
  • Register Layout Typedef
    • +
  • Base Address
    • +
  • Access Definitions
    • +
+

The section Peripheral Access shows examples for peripheral definitions.

+

+Device.h Template File

+

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

+
/**************************************************************************//**
+ * @file     <Device>.h
+ * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* ToDo: replace '<Device>' with your device name; add your doxyGen comment   */
+/** @addtogroup <Device>_Definitions <Device> Definitions
+  This file defines all structures and symbols for <Device>:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - Peripheral definitions
+  @{
+*/
+
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
+  Configuration of the Cortex-M# Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M# Processor Exceptions Numbers ***************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  HardFault_IRQn                = -13,      /*!<  3 Hard Fault Interrupt                          */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+  BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+  UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/******  Device Specific Interrupt Numbers ********************************************************/
+/* ToDo: add here your device specific external interrupt numbers
+         according the interrupt handlers defined in startup_Device.s
+         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */
+  <DeviceInterrupt>_IRQn        = 0,        /*!< Device Interrupt                                 */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+/* ToDo: set the defines according your Device                                                    */
+/* ToDo: define the correct core revision
+         __CM0_REV if your device is a CORTEX-M0 device
+         __CM3_REV if your device is a CORTEX-M3 device
+         __CM4_REV if your device is a CORTEX-M4 device                                           */
+#define __CM#_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             0         /*!< MPU present or not                               */
+/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
+#define __FPU_PRESENT             0        /*!< FPU present or not                                */
+
+/*@}*/ /* end of group <Device>_CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+         core_cm0.h if your device is a CORTEX-M0 device
+         core_cm3.h if your device is a CORTEX-M3 device
+         core_cm4.h if your device is a CORTEX-M4 device                                          */
+#include <core_cm#.h>                       /* Cortex-M# processor and core peripherals           */
+/* ToDo: include your system_<Device>.h file
+         replace '<Device>' with your device name                                                 */
+#include "system_<Device>.h"                /* <Device> System  include file                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+/** @addtogroup <Device>_Peripherals <Device> Peripherals
+  <Device> Device Specific Peripheral registers structures
+  @{
+*/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer                                  */
+
+/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
+/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t EN;                         /*!< Offset: 0x0000   Timer Enable Register           */
+  __IO uint32_t RUN;                        /*!< Offset: 0x0004   Timer RUN Register              */
+  __IO uint32_t CR;                         /*!< Offset: 0x0008   Timer Control Register          */
+  __IO uint32_t MOD;                        /*!< Offset: 0x000C   Timer Mode Register             */
+       uint32_t RESERVED0[1];
+  __IO uint32_t ST;                         /*!< Offset: 0x0014   Timer Status Register           */
+  __IO uint32_t IM;                         /*!< Offset: 0x0018   Interrupt Mask Register         */
+  __IO uint32_t UC;                         /*!< Offset: 0x001C   Timer Up Counter Register       */
+  __IO uint32_t RG0                         /*!< Offset: 0x0020   Timer Register                  */
+       uint32_t RESERVED1[2];
+  __IO uint32_t CP;                         /*!< Offset: 0x002C   Capture register                */
+} <DeviceAbbreviation>_TMR_TypeDef;
+/*@}*/ /* end of group <Device>_TMR */
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* ToDo: add here your device peripherals base addresses
+         following is an example for timer                                    */
+/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
+  @{
+*/
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+/*@}*/ /* end of group <Device>_MemoryMap */
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+/* ToDo: add here your device peripherals pointer definitions
+         following is an example for timer                                    */
+
+/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
+  @{
+*/
+
+#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+/*@}*/ /* end of group <Device>_PeripheralDecl */
+
+/*@}*/ /* end of group <Device>_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* <Device>_H */
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/doxygen.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/doxygen.png new file mode 100644 index 000000000..7765a3381 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/doxygen.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/dynsections.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/dynsections.js new file mode 100644 index 000000000..ed092c7f6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + +CMSIS-CORE: Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
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+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/functions_vars.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/functions_vars.html new file mode 100644 index 000000000..4265fd8ac --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/functions_vars.html @@ -0,0 +1,626 @@ + + + + + +CMSIS-CORE: Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
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+
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+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
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+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
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+
+ +
+
+
+ +
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+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/globals_eval.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/globals_eval.html new file mode 100644 index 000000000..0bf20201a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/globals_eval.html @@ -0,0 +1,167 @@ + + + + + +CMSIS-CORE: Globals + + + + + + + + + + + + + + +
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CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
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CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
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+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
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+
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+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html new file mode 100644 index 000000000..440ea5016 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html @@ -0,0 +1,1143 @@ + + + + + +CMSIS-CORE: Core Register Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
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+Functions
+
+
Core Register Access
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __get_CONTROL (void)
 Read the CONTROL register. More...
 
void __set_CONTROL (uint32_t control)
 Set the CONTROL Register. More...
 
uint32_t __get_IPSR (void)
 Read the IPSR register. More...
 
uint32_t __get_APSR (void)
 Read the APSR register. More...
 
uint32_t __get_xPSR (void)
 Read the xPSR register. More...
 
uint32_t __get_PSP (void)
 Read the PSP register. More...
 
void __set_PSP (uint32_t topOfProcStack)
 Set the PSP register. More...
 
uint32_t __get_MSP (void)
 Read the MSP register. More...
 
void __set_MSP (uint32_t topOfMainStack)
 Set the MSP register. More...
 
uint32_t __get_PRIMASK (void)
 Read the PRIMASK register bit. More...
 
void __set_PRIMASK (uint32_t priMask)
 Set the Priority Mask bit. More...
 
uint32_t __get_BASEPRI (void)
 Read the BASEPRI register [not for Cortex-M0 variants]. More...
 
void __set_BASEPRI (uint32_t basePri)
 Set the BASEPRI register [not for Cortex-M0 variants]. More...
 
uint32_t __get_FAULTMASK (void)
 Read the FAULTMASK register [not for Cortex-M0 variants]. More...
 
void __set_FAULTMASK (uint32_t faultMask)
 Set the FAULTMASK register [not for Cortex-M0 variants]. More...
 
uint32_t __get_FPSCR (void)
 Read the FPSCR register [only for Cortex-M4]. More...
 
void __set_FPSCR (uint32_t fpscr)
 Set the FPSC register [only for Cortex-M4]. More...
 
void __enable_irq (void)
 Globally enables interrupts and configurable fault handlers. More...
 
void __disable_irq (void)
 Globally disables interrupts and configurable fault handlers. More...
 
void __enable_fault_irq (void)
 Enables interrupts and all fault handlers [not for Cortex-M0 variants]. More...
 
void __disable_fault_irq (void)
 Disables interrupts and all fault handlers [not for Cortex-M0 variants]. More...
 
+

Description

+

The following functions provide access to Cortex-M core registers.

+

Function Documentation

+ +
+
+ + + + + + + + +
void __disable_fault_irq (void )
+
+

The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction CPSID f.

+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • Can be executed in privileged mode only.
    • +
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __disable_irq (void )
+
+

The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction CPSID i.

+
Remarks
    +
  • Can be executed in privileged mode only.
    • +
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __enable_fault_irq (void )
+
+

The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction CPSIE f.

+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • Can be executed in privileged mode only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __enable_irq (void )
+
+

The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction CPSIE i.

+
Remarks
    +
  • Can be executed in privileged mode only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_APSR (void )
+
+

The function reads the Application Program Status Register (APSR) using the instruction MRS.
+
+ The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:

+
    +
  • N (APSR[31]) (Negative flag)
      +
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • +
    • =0 The instruction result has a positive value or equal zero.
      +
      +
      • +
    +
    • +
  • Z (APSR[30]) (Zero flag)
      +
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
      +
      +
      • +
    +
    • +
  • C (APSR[29]) (Carry or borrow flag)
      +
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • +
    • =inverse of borrow output status For unsigned subtract operations.
      +
      +
      • +
    +
    • +
  • V (APSR[28]) (Overflow flag)
      +
    • =1 A signed overflow occurred (for signed additions or subtractions).
      +
      +
      • +
    +
    • +
  • Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
      +
    • This flag is a sticky flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.
      • +
    • =1 When saturation or an overflow occurred.
      +
      +
      • +
    +
    • +
  • GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
      +
    • Can be set by the parallel add and subtract instructions.
      • +
    • Are used by the SEL instruction to perform byte-based selection from two registers.
      • +
    +
    • +
+
Returns
APSR register value
+
Remarks
    +
  • Some instructions update all flags; some instructions update a subset of the flags.
    • +
  • If a flag is not updated, the original value is preserved.
    • +
  • Conditional instructions that are not executed have no effect on the flags.
    • +
  • The CMSIS does not provide a function to update this register.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_BASEPRI (void )
+
+

The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS.
+
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Returns
BASEPRI register value
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_CONTROL (void )
+
+

The function reads the CONTROL register value using the instruction MRS.
+
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+

+
    +
  • CONTROL[2] [only Cortex-M4]
      +
    • =0 FPU not active
      • +
    • =1 FPU active
      +
      +
      • +
    +
    • +
  • CONTROL[1]
      +
    • =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
      • +
    • =0 In thread mode - Default stack pointer MSP is used.
      • +
    • =1 In thread mode - Alternate stack pointer PSP is used.
      +
      +
      • +
    +
    • +
  • CONTROL[0] [not Cortex-M0]
      +
    • =0 In thread mode and privileged state.
      • +
    • =1 In thread mode and user state.
      • +
    +
    • +
+
Returns
CONTROL register value
+
Remarks
    +
  • The processor can be in user state or privileged state when running in thread mode.
    • +
  • Exception handlers always run in privileged state.
    • +
  • On reset, the processor is in thread mode with privileged access rights.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_FAULTMASK (void )
+
+

The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS.
+
+ FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).

+
Returns
FAULTMASK register value
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_FPSCR (void )
+
+

The function reads the Floating-Point Status Control Register (FPSCR) value.
+
+ FPSCR provides all necessary User level controls of the floating-point system.

+
Returns
    +
  • FPSCR register value, when __FPU_PRESENT=1
    • +
  • =0, when __FPU_PRESENT=0
    • +
+
+
Remarks
    +
  • Only for Cortex-M4.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_IPSR (void )
+
+

The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS.
+
+ The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:

+
    +
  • ISR_NUMBER (IPSR[8:0])
      +
    • =0 Thread mode
      • +
    • =1 Reserved
      • +
    • =2 NMI
      • +
    • =3 HardFault
      • +
    • =4 MemManage
      • +
    • =5 BusFault
      • +
    • =6 UsageFault
      • +
    • =7-10 Reserved
      • +
    • =11 SVCall
      • +
    • =12 Reserved for Debug
      • +
    • =13 Reserved
      • +
    • =14 PendSV
      • +
    • =15 SysTick
      • +
    • =16 IRQ0
      • +
    • ...
      • +
    • =n+15 IRQ(n-1)
      • +
    +
    • +
+
Returns
ISPR register value
+
Remarks
    +
  • This register is read-only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_MSP (void )
+
+

The function reads the Main Status Pointer (MSP) value using the instruction MRS.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Returns
MSP Register value
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_PRIMASK (void )
+
+

The function reads the Priority Mask register (PRIMASK) value using the instruction MRS.
+
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Returns
PRIMASK register value
    +
  • =0 no effect
    • +
  • =1 prevents the activation of all exceptions with configurable priority
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_PSP (void )
+
+

The function reads the Program Status Pointer (PSP) value using the instruction MRS.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Returns
PSP register value
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_xPSR (void )
+
+

The function reads the combined Program Status Register (xPSR) using the instruction MRS.
+
+ xPSR provides information about program execution and the APSR flags. It consists of the following PSRs:

+
    +
  • Application Program Status Register (APSR)
    • +
  • Interrupt Program Status Register (IPSR)
    • +
  • Execution Program Status Register (EPSR)
    • +
+

In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:

+
    +
  • IT (xPSR[26:25]) (If-Then condition instruction)
      +
    • Contains up to four instructions following an IT instruction.
      • +
    • Each instruction in the block is conditional.
      • +
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      +
      +
      • +
    +
    • +
  • T (xPSR[24]) (Thumb bit)
      +
    • =1 Indicates that that the processor is in Thumb state.
      • +
    • =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
      • +
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      • +
    +
    • +
+
Returns
xPSR register value
+
Remarks
    +
  • The CMSIS does not provide functions that access EPSR.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_BASEPRI (uint32_t basePri)
+
+

The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR.
+
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Parameters
+ + +
[in]basePriBASEPRI value to set
+
+
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • Cannot be set in user state.
    • +
  • Useful for changing the masking level or disabling the masking.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_CONTROL (uint32_t control)
+
+

The function sets the CONTROL register value using the instruction MSR.
+
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+

+
    +
  • CONTROL[2] [only Cortex-M4]
      +
    • =0 FPU not active
      • +
    • =1 FPU active
      +
      +
      • +
    +
    • +
  • CONTROL[1]
      +
    • Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
      • +
    • =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
      • +
    • =0 In thread mode - Default stack pointer MSP is used.
      • +
    • =1 In thread mode - Alternate stack pointer PSP is used.
      +
      +
      • +
    +
    • +
  • CONTROL[0] [not writeable for Cortex-M0]
      +
    • Writeable only when the processor is in privileged state.
      • +
    • Can be used to switch the processor to user state (thread mode).
      • +
    • Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).
      • +
    • =0 In thread mode and privileged state.
      • +
    • =1 In thread mode and user state.
      • +
    +
    • +
+
Parameters
+ + +
[in]controlCONTROL register value to set
+
+
+
Remarks
    +
  • The processor can be in user state or privileged state when running in thread mode.
    • +
  • Exception handlers always run in privileged state.
    • +
  • On reset, the processor is in thread mode with privileged access rights.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_FAULTMASK (uint32_t faultMask)
+
+

The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR.
+
+ FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:

+
    +
  1. Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.
    2. +
  2. Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.
    3. +
+
Parameters
+ + +
[in]faultMaskFAULTMASK register value to set
+
+
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • +
  • When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.
    • +
  • Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).
    • +
  • When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_FPSCR (uint32_t fpscr)
+
+

The function sets the Floating-Point Status Control Register (FPSCR) value.
+
+ FPSCR provides all necessary User level control of the floating-point system.
+

+
    +
  • N (FPSC[31]) (Negative flag)
      +
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • +
    • =0 The instruction result has a positive value or equal zero.
      +
      +
      • +
    +
    • +
  • Z (FPSC[30]) (Zero flag)
      +
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
      +
      +
      • +
    +
    • +
  • C (FPSC[29]) (Carry or borrow flag)
      +
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • +
    • =inverse of borrow output status For unsigned subtract operations.
      +
      +
      • +
    +
    • +
  • V (FPSC[28]) (Overflow flag)
      +
    • =1 A signed overflow occurred (for signed additions or subtractions).
      +
      +
      • +
    +
    • +
  • AHP (FPSC[26]) (Alternative half-precision flag)
      +
    • =1 Alternative half-precision format selected.
      • +
    • =0 IEEE half-precision format selected.
      +
      +
      • +
    +
    • +
  • DN (FPSC[25]) (Default NaN mode control flag)
      +
    • =1 Any operation involving one or more NaNs returns the Default NaN.
      • +
    • =0 NaN operands propagate through to the output of a floating-point operation.
      +
      +
      • +
    +
    • +
  • FZ (FPSC[24]) (Flush-to-zero mode control flag)
      +
    • =1 Flush-to-zero mode enabled.
      • +
    • =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
      +
      +
      • +
    +
    • +
  • RMode (FPSC[23:22]) (Rounding Mode control flags)
      +
    • =0b00 Round to Nearest (RN) mode.
      • +
    • =0b01 Round towards Plus Infinity (RP) mode.
      • +
    • =0b10 Round towards Minus Infinity (RM) mode.
      • +
    • =0b11 Round towards Zero (RZ) mode.
      • +
    • The specified rounding mode is used by almost all floating-point instructions.
      +
      +
      • +
    +
    • +
  • IDC (FPSC[7]) (Input Denormal cumulative exception flags)
      +
    • See Cumulative exception bits (FPSC[4:0]).
      +
      +
      • +
    +
    • +
  • IXC (FPSC[4]) (Inexact cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • UFC (FPSC[3]) (Underflow cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • OFC (FPSC[2]) (Overflow cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • DZC (FPSC[1]) (Division by Zero cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      • +
    +
    • +
+
Parameters
+ + +
[in]fpscrFPSCR value to set
+
+
+
Remarks
    +
  • Only for Cortex-M4.
    • +
  • The variable __FPU_PRESENT has to be set to 1.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_MSP (uint32_t topOfMainStack)
+
+

The function sets the Main Status Pointer (MSP) value using the instruction MSR.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Parameters
+ + +
[in]topOfMainStackMSP value to set
+
+
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_PRIMASK (uint32_t priMask)
+
+

The function sets the Priority Mask register (PRIMASK) value using the instruction MSR.
+
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Parameters
+ + +
[in]priMaskPriority Mask
    +
  • =0 no effect
    • +
  • =1 prevents the activation of all exceptions with configurable priority
    • +
+
+
+
+
Remarks
    +
  • When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.
    • +
  • When set and a fault occurs, the hard fault handler will be executed.
    • +
  • Useful for temprorarily disabling all interrupts for timing critical tasks.
    • +
  • Does not have the ability to mask BusFault or bypass MPU.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_PSP (uint32_t topOfProcStack)
+
+

The function sets the Program Status Pointer (PSP) value using the instruction MSR.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Parameters
+ + +
[in]topOfProcStackPSP value to set
+
+
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___core___register__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___core___register__gr.js new file mode 100644 index 000000000..db578a03b --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___core___register__gr.js @@ -0,0 +1,24 @@ +var group___core___register__gr = +[ + [ "__disable_fault_irq", "group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939", null ], + [ "__disable_irq", "group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013", null ], + [ "__enable_fault_irq", "group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf", null ], + [ "__enable_irq", "group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27", null ], + [ "__get_APSR", "group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7", null ], + [ "__get_BASEPRI", "group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667", null ], + [ "__get_CONTROL", "group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7", null ], + [ "__get_FAULTMASK", "group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8", null ], + [ "__get_FPSCR", "group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905", null ], + [ "__get_IPSR", "group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8", null ], + [ "__get_MSP", "group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2", null ], + [ "__get_PRIMASK", "group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02", null ], + [ "__get_PSP", "group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9", null ], + [ "__get_xPSR", "group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd", null ], + [ "__set_BASEPRI", "group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882", null ], + [ "__set_CONTROL", "group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c", null ], + [ "__set_FAULTMASK", "group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a", null ], + [ "__set_FPSCR", "group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b", null ], + [ "__set_MSP", "group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4", null ], + [ "__set_PRIMASK", "group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f", null ], + [ "__set_PSP", "group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html new file mode 100644 index 000000000..2d5ec4dd6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html @@ -0,0 +1,276 @@ + + + + + +CMSIS-CORE: Debug Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
Debug Access
+
+
+ + + + + + + + + + + +

+Functions

uint32_t ITM_SendChar (uint32_t ch)
 Transmits a character via channel 0. More...
 
int32_t ITM_ReceiveChar (void)
 ITM Receive Character. More...
 
int32_t ITM_CheckChar (void)
 ITM Check Character. More...
 
+ + + + +

+Variables

volatile int32_t ITM_RxBuffer
 external variable to receive characters More...
 
+

Description

+

CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

+

The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

+
    +
  • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
    • +
+
    +
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
    • +
+
Remarks
    +
  • ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.
    • +
  • The ITM channel 0 can be enabled for the user task.
    • +
  • ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.
    • +
+
+
+

+ITM Debug Support in uVision

+

In a debug session, uVision uses the Debug (printf) Viewer window to display data.

+

Direction: Microcontroller –> uVision:

+
    +
  • Characters received via ITM communication channel 0 are written in a printf-style to the Debug (printf) Viewer window.
    • +
+

Direction: uVision –> Microcontroller:

+
    +
  • Check if ITM_RxBuffer variable is available (only performed once).
    • +
  • Read the character from the Debug (printf) Viewer window.
    • +
  • If ITM_RxBuffer is empty, write character to ITM_RxBuffer.
    • +
+
Note
The current solution does not use a buffer mechanism for transmitting the characters.
+
+

+Example:

+

Example for the usage of the ITM Channel 31 for RTOS Kernels:

+
// check if debugger connected and ITM channel enabled for tracing
+
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+
(ITM->TCR & ITM_TCR_ITMENA) &&
+
(ITM->TER & (1UL >> 31))) {
+
+
// transmit trace data
+
while (ITM->PORT31_U32 == 0);
+
ITM->PORT[31].u8 = task_id; // id of next task
+
while (ITM->PORT[31].u32 == 0);
+
ITM->PORT[31].u32 = task_status; // status information
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
int32_t ITM_CheckChar (void )
+
+

This function reads the external variable ITM_RxBuffer and checks whether a character is available or not.

+
Returns
    +
  • =0 - No character available
    • +
  • =1 - Character available
    • +
+
+ +
+
+ +
+
+ + + + + + + + +
int32_t ITM_ReceiveChar (void )
+
+

This function inputs a character via the external variable ITM_RxBuffer. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Returns
    +
  • Received character
    • +
  • =1 - No character received
    • +
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t ITM_SendChar (uint32_t ch)
+
+

This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Parameters
+ + +
[in]chCharacter to transmit
+
+
+
Returns
Character to transmit
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
volatile int32_t ITM_RxBuffer
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.js new file mode 100644 index 000000000..eb2297746 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.js @@ -0,0 +1,7 @@ +var group___i_t_m___debug__gr = +[ + [ "ITM_CheckChar", "group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535", null ], + [ "ITM_ReceiveChar", "group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c", null ], + [ "ITM_SendChar", "group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1", null ], + [ "ITM_RxBuffer", "group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html new file mode 100644 index 000000000..2169f3679 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html @@ -0,0 +1,1031 @@ + + + + + +CMSIS-CORE: Interrupts and Exceptions (NVIC) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Enumerations | +Functions
+
+
Interrupts and Exceptions (NVIC)
+
+
+ +

Describes programming of interrupts and exception functions. +More...

+ + + + + +

+Enumerations

enum  IRQn_Type {
+  NonMaskableInt_IRQn = -14, +
+  HardFault_IRQn = -13, +
+  MemoryManagement_IRQn = -12, +
+  BusFault_IRQn = -11, +
+  UsageFault_IRQn = -10, +
+  SVCall_IRQn = -5, +
+  DebugMonitor_IRQn = -4, +
+  PendSV_IRQn = -2, +
+  SysTick_IRQn = -1, +
+  WWDG_STM_IRQn = 0, +
+  PVD_STM_IRQn = 1 +
+ }
 Definition of IRQn numbers. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set priority grouping [not for Cortex-M0 variants]. More...
 
uint32_t NVIC_GetPriorityGrouping (void)
 Read the priority grouping [not for Cortex-M0 variants]. More...
 
void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable an external interrupt. More...
 
void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable an external interrupt. More...
 
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get the pending interrupt. More...
 
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set an interrupt to pending. More...
 
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear an interrupt from pending. More...
 
uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get the interrupt active status [not for Cortex-M0 variants]. More...
 
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for an interrupt. More...
 
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get the priority of an interrupt. More...
 
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encodes Priority [not for Cortex-M0 variants]. More...
 
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode the interrupt priority [not for Cortex-M0 variants]. More...
 
void NVIC_SystemReset (void)
 Reset the system. More...
 
+

Description

+

ARM provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.

+

The table below describes the core exception names and their availability in various Cortex-M cores.

+ + + + + + + + + + + + + + + + + + + + + +
Core Exception Name IRQn Value M0 M0p M3 M4 SC000 SC300 Description
NonMaskableInt_IRQn -14
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Non Maskable Interrupt
HardFault_IRQn -13
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Hard Fault Interrupt
MemoryManagement_IRQn -12    
+available +
+
+available +
+ 		 
+available +
+ 		Memory Management Interrupt
BusFault_IRQn -11    
+available +
+
+available +
+ 		 
+available +
+ 		Bus Fault Interrupt
UsageFault_IRQn -10    
+available +
+
+available +
+ 		 
+available +
+ 		Usage Fault Interrupt
SVCall_IRQn -5
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		SV Call Interrupt
DebugMonitor_IRQn -4    
+available +
+
+available +
+ 		 
+available +
+ 		Debug Monitor Interrupt
PendSV_IRQn -2
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Pend SV Interrupt
SysTick_IRQn -1
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		System Tick Interrupt
+

+For Cortex-M0 and Cortex-M0+

+

The following exception names are fixed and define the start of the vector table for Cortex-M0 variants:

+
__Vectors DCD __initial_sp ; Top of Stack
+
DCD Reset_Handler ; Reset Handler
+
DCD NMI_Handler ; NMI Handler
+
DCD HardFault_Handler ; Hard Fault Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD SVC_Handler ; SVCall Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD PendSV_Handler ; PendSV Handler
+
DCD SysTick_Handler ; SysTick Handler
+

+For Cortex-M3

+

The following exception names are fixed and define the start of the vector table for a Cortex-M3:

+
__Vectors DCD __initial_sp ; Top of Stack
+
DCD Reset_Handler ; Reset Handler
+
DCD NMI_Handler ; NMI Handler
+
DCD HardFault_Handler ; Hard Fault Handler
+
DCD MemManage_Handler ; MPU Fault Handler
+
DCD BusFault_Handler ; Bus Fault Handler
+
DCD UsageFault_Handler ; Usage Fault Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD SVC_Handler ; SVCall Handler
+
DCD DebugMon_Handler ; Debug Monitor Handler
+
DCD 0 ; Reserved
+
DCD PendSV_Handler ; PendSV Handler
+
DCD SysTick_Handler ; SysTick Handler
+

+Example

+

The following is an examples for device-specific interrupts:

+
; External Interrupts
+
DCD WWDG_IRQHandler ; Window Watchdog
+
DCD PVD_IRQHandler ; PVD through EXTI Line detect
+
DCD TAMPER_IRQHandler ; Tamper
+

Device-specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.

+
Default_Handler PROC
+
EXPORT WWDG_IRQHandler [WEAK]
+
EXPORT PVD_IRQHandler [WEAK]
+
EXPORT TAMPER_IRQHandler [WEAK]
+
:
+
:
+
WWDG_IRQHandler
+
PVD_IRQHandler
+
TAMPER_IRQHandler
+
:
+
:
+
B .
+
ENDP
+

The user application may simply define an interrupt handler function by using the handler name as shown below.

+
void WWDG_IRQHandler(void)
+
{
+
...
+
}
+

+Code Example 1

+

The code below shows the usage of the CMSIS NVIC functions NVIC_SetPriorityGrouping(), NVIC_GetPriorityGrouping(), NVIC_SetPriority(), NVIC_GetPriority(), NVIC_EncodePriority(), and NVIC_DecodePriority() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t priorityGroup; /* Variables to store priority group and priority */
+
uint32_t priority;
+
uint32_t preemptPriority;
+
uint32_t subPriority;
+
+
+
int main (void) {
+
+
NVIC_SetPriorityGrouping(5); /* Set priority group to 5:
+
Bit[7..6] preempt priority Bits,
+
Bit[5..3] subpriority Bits
+
(valid for five priority bits) */
+
+
priorityGroup = NVIC_GetPriorityGrouping(); /* Get used priority grouping */
+
+
priority = NVIC_EncodePriority(priorityGroup, 1, 6); /* Encode priority with 6 for subpriority and 1 for preempt priority
+
Note: priority depends on the used priority grouping */
+
+
NVIC_SetPriority(UART0_IRQn, priority); /* Set new priority */
+
+
priority = NVIC_GetPriority(UART0_IRQn); /* Retrieve priority again */
+
+
NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
+
+
while(1);
+
}
+

+Code Example 2

+

The code below shows the usage of the CMSIS NVIC functions NVIC_EnableIRQ(), NVIC_GetActive() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t active; /* Variable to store interrupt active state */
+
+
+
void TIMER0_IRQHandler(void) { /* Timer 0 interrupt handler */
+
+
if (LPC_TIM0->IR & (1 << 0)) { /* Check if interrupt for match channel 0 occured */
+
LPC_TIM0->IR |= (1 << 0); /* Acknowledge interrupt for match channel 0 occured */
+
}
+
active = NVIC_GetActive(TIMER0_IRQn); /* Get interrupt active state of timer 0 */
+
}
+
+
+
int main (void) {
+
/* Set match channel register MR0 to 1 millisecond */
+
LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1); /* 1 ms? */
+
+
LPC_TIM0->MCR = (3 << 0); /* Enable interrupt and reset for match channel MR0 */
+
+
NVIC_EnableIRQ(TIMER0_IRQn); /* Enable NVIC interrupt for timer 0 */
+
+
LPC_TIM0->TCR = (1 << 0); /* Enable timer 0 */
+
+
while(1);
+
}
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum IRQn_Type
+
+

The core exception enumeration names for IRQn values are defined in the file device.h.

+
Negative IRQn values represent processor core exceptions (internal interrupts).
+Positive IRQn values represent device-specific exceptions (external interrupts). 
+The first device-specific interrupt has the IRQn value 0.
+

The table below describes the core exception names and their availability in various Cortex-M cores.

+ + + + + + + + + + + + +
Enumerator
NonMaskableInt_IRQn  +

Exception 2: Non Maskable Interrupt.

+
HardFault_IRQn  +

Exception 3: Hard Fault Interrupt.

+
MemoryManagement_IRQn  +

Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].

+
BusFault_IRQn  +

Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].

+
UsageFault_IRQn  +

Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].

+
SVCall_IRQn  +

Exception 11: SV Call Interrupt.

+
DebugMonitor_IRQn  +

Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].

+
PendSV_IRQn  +

Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].

+
SysTick_IRQn  +

Exception 15: System Tick Interrupt.

+
WWDG_STM_IRQn  +

Device Interrupt 0: Window WatchDog Interrupt.

+
PVD_STM_IRQn  +

Device Interrupt 1: PVD through EXTI Line detection Interrupt.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
+
+

This function removes the pending state of the specified interrupt IRQn. IRQn cannot be a negative number.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
  • An interrupt can have the status pending though it is not active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void NVIC_DecodePriority (uint32_t Priority,
uint32_t PriorityGroup,
uint32_t * pPreemptPriority,
uint32_t * pSubPriority 
)
+
+

This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + + +
[in]PriorityPriority
[in]PriorityGroupPriority group
[out]*pPreemptPriorityPreemptive priority value (starting from 0)
[out]*pSubPrioritySubpriority value (starting from 0)
+
+
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_DisableIRQ (IRQn_Type IRQn)
+
+

This function disables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnNumber of the external interrupt to disable
+
+
+
Remarks
    +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_EnableIRQ (IRQn_Type IRQn)
+
+

This function enables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
  • The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32:
    + ICTR[4:0]
      +
    • =0 - 32 interrupts supported
      • +
    • =1 - 64 interrupts supported
      • +
    • ...
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup,
uint32_t PreemptPriority,
uint32_t SubPriority 
)
+
+

This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + +
[in]PriorityGroupPriority group
[in]PreemptPriorityPreemptive priority value (starting from 0)
[in]SubPrioritySubpriority value (starting from 0)
+
+
+
Returns
Encoded priority for the interrupt
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetActive (IRQn_Type IRQn)
+
+

This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • =0 Interrupt is not active
    • +
  • =1 Interrupt is active, or active and pending
    • +
+
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.
    • +
  • When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
+
+

This function returns the pending status of the specified interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • =0 Interrupt is not pending
    • +
  • =1 Interrupt is pending
    • +
+
+
Remarks
    +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
+
+

This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt.

+

The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
Interrupt priority
+
Remarks
    +
  • Each external interrupt has an associated priority-level register.
    • +
  • Unimplemented bits are read as zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriorityGrouping (void )
+
+

This functuion returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).

+
Returns
Priority grouping field
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • By default, priority group setting is zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
+
+

This function sets the pending bit for the specified interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SetPriority (IRQn_Type IRQn,
uint32_t priority 
)
+
+

Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.

+

The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.

+
Parameters
+ + + +
[in]IRQnInterrupt Number
[in]priorityPriority to set
+
+
+
Remarks
    +
  • The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0.
    • +
  • Writes to unimplemented bits are ignored.
    • +
  • For Cortex-M0:
      +
    • Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.
      • +
    • Supports 0 to 192 priority levels.
      • +
    • Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.
      • +
    +
    • +
  • For Cortex-M3 and Cortex-M4:
      +
    • Dynamic switching of interrupt priority levels is supported.
      • +
    • Supports 0 to 255 priority levels.
      • +
    • Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
+
+

The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+
Parameters
+ + +
[in]PriorityGroupPriority group
+
+
+
Remarks
    +
  • not for Cortex-M0 variants.
    • +
  • By default, priority group setting is zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SystemReset (void )
+
+

This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.

+
Remarks
    +
  • In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.
    • +
+
+
See Also
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.js new file mode 100644 index 000000000..e7db41ef6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.js @@ -0,0 +1,29 @@ +var group___n_v_i_c__gr = +[ + [ "IRQn_Type", "group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8", [ + [ "NonMaskableInt_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30", null ], + [ "HardFault_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85", null ], + [ "MemoryManagement_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa", null ], + [ "BusFault_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af", null ], + [ "UsageFault_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf", null ], + [ "SVCall_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237", null ], + [ "DebugMonitor_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c", null ], + [ "PendSV_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2", null ], + [ "SysTick_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7", null ], + [ "WWDG_STM_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2", null ], + [ "PVD_STM_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86", null ] + ] ], + [ "NVIC_ClearPendingIRQ", "group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a", null ], + [ "NVIC_DecodePriority", "group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377", null ], + [ "NVIC_DisableIRQ", "group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c", null ], + [ "NVIC_EnableIRQ", "group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f", null ], + [ "NVIC_EncodePriority", "group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5", null ], + [ "NVIC_GetActive", "group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892", null ], + [ "NVIC_GetPendingIRQ", "group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662", null ], + [ "NVIC_GetPriority", "group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395", null ], + [ "NVIC_GetPriorityGrouping", "group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78", null ], + [ "NVIC_SetPendingIRQ", "group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2", null ], + [ "NVIC_SetPriority", "group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798", null ], + [ "NVIC_SetPriorityGrouping", "group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354", null ], + [ "NVIC_SystemReset", "group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html new file mode 100644 index 000000000..03883fda8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html @@ -0,0 +1,196 @@ + + + + + +CMSIS-CORE: Systick Timer (SYSTICK) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Systick Timer (SYSTICK)
+
+
+ +

Initialize and start the SysTick timer. +More...

+ + + + + +

+Functions

uint32_t SysTick_Config (uint32_t ticks)
 System Tick Timer Configuration. More...
 
+

Description

+
The System Tick Time (SysTick) generates interrupt requests on a regular basis.
+This allows an OS to carry out context switching to support multiple tasking. For applications
+that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an 
+interrupt source for tasks that need to be executed regularly.
+

+Code Example

+

The code below shows the usage of the function SysTick_Config() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t msTicks = 0; /* Variable to store millisecond ticks */
+
+
+
void SysTick_Handler(void) { /* SysTick interrupt Handler.
+
msTicks++; See startup file startup_LPC17xx.s for SysTick vector */
+
}
+
+
+
int main (void) {
+
uint32_t returnCode;
+
+
returnCode = SysTick_Config(SystemCoreClock / 1000); /* Configure SysTick to generate an interrupt every millisecond */
+
+
if (returnCode != 0) { /* Check return code for errors */
+
// Error Handling
+
}
+
+
while(1);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t SysTick_Config (uint32_t ticks)
+
+

Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.

+
Parameters
+ + +
[in]ticksNumber of ticks between two interrupts
+
+
+
Returns
0 - success
+
+1 - failure
+
Note
When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.js new file mode 100644 index 000000000..99c530434 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.js @@ -0,0 +1,4 @@ +var group___sys_tick__gr = +[ + [ "SysTick_Config", "group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html new file mode 100644 index 000000000..f21ff23aa --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html @@ -0,0 +1,797 @@ + + + + + +CMSIS-CORE: Intrinsic Functions for CPU Instructions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Intrinsic Functions for CPU Instructions
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void __NOP (void)
 No Operation. More...
 
void __WFI (void)
 Wait For Interrupt. More...
 
void __WFE (void)
 Wait For Event. More...
 
void __SEV (void)
 Send Event. More...
 
void __BKPT (uint8_t value)
 Set Breakpoint. More...
 
void __ISB (void)
 Instruction Synchronization Barrier. More...
 
void __DSB (void)
 Data Synchronization Barrier. More...
 
void __DMB (void)
 Data Memory Barrier. More...
 
uint32_t __REV (uint32_t value)
 Reverse byte order (32 bit) More...
 
uint32_t __REV16 (uint32_t value)
 Reverse byte order (16 bit) More...
 
int32_t __REVSH (int32_t value)
 Reverse byte order in signed short value. More...
 
uint32_t __RBIT (uint32_t value)
 Reverse bit order of value [not for Cortex-M0 variants]. More...
 
uint32_t __ROR (uint32_t value, uint32_t shift)
 Rotate a value right by a number of bits. More...
 
uint8_t __LDREXB (volatile uint8_t *addr)
 LDR Exclusive (8 bit) [not for Cortex-M0 variants]. More...
 
uint16_t __LDREXH (volatile uint16_t *addr)
 LDR Exclusive (16 bit) [not for Cortex-M0 variants]. More...
 
uint32_t __LDREXW (volatile uint32_t *addr)
 LDR Exclusive (32 bit) [not for Cortex-M0 variants]. More...
 
uint32_t __STREXB (uint8_t value, volatile uint8_t *addr)
 STR Exclusive (8 bit) [not for Cortex-M0 variants]. More...
 
uint32_t __STREXH (uint16_t value, volatile uint16_t *addr)
 STR Exclusive (16 bit) [not for Cortex-M0 variants]. More...
 
uint32_t __STREXW (uint32_t value, volatile uint32_t *addr)
 STR Exclusive (32 bit) [not for Cortex-M0 variants]. More...
 
void __CLREX (void)
 Remove the exclusive lock [not for Cortex-M0 variants]. More...
 
uint32_t __SSAT (unint32_t value, uint32_t sat)
 Signed Saturate [not for Cortex-M0 variants]. More...
 
uint32_t __USAT (uint32_t value, uint32_t sat)
 Unsigned Saturate [not for Cortex-M0 variants]. More...
 
uint8_t __CLZ (uint32_t value)
 Count leading zeros [not for Cortex-M0 variants]. More...
 
+

Description

+

The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.

+

Function Documentation

+ +
+
+ + + + + + + + +
void __BKPT (uint8_t value)
+
+

This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+
Parameters
+ + +
[in]valueis ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void __CLREX (void )
+
+

This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants].

+ +
+
+ +
+
+ + + + + + + + +
uint8_t __CLZ (uint32_t value)
+
+

This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].

+
Parameters
+ + +
[in]valueValue to count the leading zeros
+
+
+
Returns
number of leading zeros in value
+ +
+
+ +
+
+ + + + + + + + +
void __DMB (void )
+
+

This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

+ +
+
+ +
+
+ + + + + + + + +
void __DSB (void )
+
+

This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

+ +
+
+ +
+
+ + + + + + + + +
void __ISB (void )
+
+

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

+ +
+
+ +
+
+ + + + + + + + +
uint8_t __LDREXB (volatile uint8_t * addr)
+
+

This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].

+
Parameters
+ + +
[in]*addrPointer to data
+
+
+
Returns
value of type uint8_t at (*addr)
+ +
+
+ +
+
+ + + + + + + + +
uint16_t __LDREXH (volatile uint16_t * addr)
+
+

This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].

+
Parameters
+ + +
[in]*addrPointer to data
+
+
+
Returns
value of type uint16_t at (*addr)
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __LDREXW (volatile uint32_t * addr)
+
+

This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].

+
Parameters
+ + +
[in]*addrPointer to data
+
+
+
Returns
value of type uint32_t at (*addr)
+ +
+
+ +
+
+ + + + + + + + +
void __NOP (void )
+
+

This function does nothing. This instruction can be used for code alignment purposes.

+ +
+
+ +
+
+ + + + + + + + +
uint32_t __RBIT (uint32_t value)
+
+

This function reverses the bit order of the given value [not for Cortex-M0 variants].

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __REV (uint32_t value)
+
+

This function reverses the byte order in integer value.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __REV16 (uint32_t value)
+
+
This function reverses the byte order in two unsigned short values.
+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+
Note
The function can be disabled by defining the compile time flag __NO_EMBEDDED_ASM. This rule applies to the ARM toolchain. For example:
#ifndef __NO_EMBEDDED_ASM
+
__REV16(0x1);
+
#endif
+
+ +
+
+ +
+
+ + + + + + + + +
int32_t __REVSH (int32_t value)
+
+
This function reverses the byte order in a signed short value with sign extension to integer.
+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+
Note
The function can be disabled by defining the compile time flag __NO_EMBEDDED_ASM. This rule applies to the ARM toolchain. For example:
#ifndef __NO_EMBEDDED_ASM
+
__REVSH(0x1);
+
#endif
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __ROR (uint32_t value,
uint32_t shift 
)
+
+

This function rotates a value right by a specified number of bits.

+
Parameters
+ + + +
[in]valueValue to be shifted right
[in]shiftNumber of bits in the range [1..31]
+
+
+
Returns
Rotated value
+ +
+
+ +
+
+ + + + + + + + +
void __SEV (void )
+
+

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAT (unint32_t value,
uint32_t sat 
)
+
+

This function saturates a signed value [not for Cortex-M0 variants].

+
Parameters
+ + + +
[in]valueValue to be saturated
[in]satBit position to saturate to [1..32]
+
+
+
Returns
Saturated value
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __STREXB (uint8_t value,
volatile uint8_t * addr 
)
+
+

This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].

+
Parameters
+ + + +
[in]valueValue to store
[in]*addrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __STREXH (uint16_t value,
volatile uint16_t * addr 
)
+
+

This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].

+
Parameters
+ + + +
[in]valueValue to store
[in]*addrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __STREXW (uint32_t value,
volatile uint32_t * addr 
)
+
+

This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].

+
Parameters
+ + + +
[in]valueValue to store
[in]*addrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAT (uint32_t value,
uint32_t sat 
)
+
+

This function saturates an unsigned value [not for Cortex-M0 variants].

+
Parameters
+ + + +
[in]valueValue to be saturated
[in]satBit position to saturate to [0..31]
+
+
+
Returns
Saturated value
+ +
+
+ +
+
+ + + + + + + + +
void __WFE (void )
+
+

Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs:

+
    +
  • If the event register is 0, then WFE suspends execution until one of the following events occurs:
      +
    • An exception, unless masked by the exception mask registers or the current priority level.
      • +
    • An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
      • +
    • A Debug Entry request, if Debug is enabled.
      • +
    • An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.
      • +
    +
    • +
+
    +
  • If the event register is 1, then WFE clears it to 0 and returns immediately.
    • +
+ +
+
+ +
+
+ + + + + + + + +
void __WFI (void )
+
+

WFI is a hint instruction that suspends execution until one of the following events occurs:

+
    +
  • A non-masked interrupt occurs and is taken.
    • +
  • An interrupt masked by PRIMASK becomes pending.
    • +
  • A Debug Entry request.
    • +
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.js new file mode 100644 index 000000000..eb725255e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.js @@ -0,0 +1,26 @@ +var group__intrinsic___c_p_u__gr = +[ + [ "__BKPT", "group__intrinsic___c_p_u__gr.html#ga92f5621626711931da71eaa8bf301af7", null ], + [ "__CLREX", "group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412", null ], + [ "__CLZ", "group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02", null ], + [ "__DMB", "group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96", null ], + [ "__DSB", "group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199", null ], + [ "__ISB", "group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5", null ], + [ "__LDREXB", "group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e", null ], + [ "__LDREXH", "group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15", null ], + [ "__LDREXW", "group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c", null ], + [ "__NOP", "group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e", null ], + [ "__RBIT", "group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863", null ], + [ "__REV", "group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8", null ], + [ "__REV16", "group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26", null ], + [ "__REVSH", "group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe", null ], + [ "__ROR", "group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024", null ], + [ "__SEV", "group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7", null ], + [ "__SSAT", "group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1", null ], + [ "__STREXB", "group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99", null ], + [ "__STREXH", "group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a", null ], + [ "__STREXW", "group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197", null ], + [ "__USAT", "group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a", null ], + [ "__WFE", "group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563", null ], + [ "__WFI", "group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html new file mode 100644 index 000000000..2424b271d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html @@ -0,0 +1,3125 @@ + + + + + +CMSIS-CORE: Intrinsic Functions for SIMD Instructions [only Cortex-M4] + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Intrinsic Functions for SIMD Instructions [only Cortex-M4]
+
+
+ +

Access to dedicated SIMD instructions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __SADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed addition. More...
 
uint32_t __QADD8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating addition. More...
 
uint32_t __SHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed addition with halved results. More...
 
uint32_t __UADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned addition. More...
 
uint32_t __UQADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating addition. More...
 
uint32_t __UHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned addition with halved results. More...
 
uint32_t __SSUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed subtraction. More...
 
uint32_t __QSUB8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating subtract. More...
 
uint32_t __SHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed subtraction with halved results. More...
 
uint32_t __USUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned subtract. More...
 
uint32_t __UQSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating subtraction. More...
 
uint32_t __UHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned subtraction with halved results. More...
 
uint32_t __SADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed addition. More...
 
uint32_t __QADD16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating addition. More...
 
uint32_t __SHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition with halved results. More...
 
uint32_t __UADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition. More...
 
uint32_t __UQADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition. More...
 
uint32_t __UHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition with halved results. More...
 
uint32_t __SSUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction. More...
 
uint32_t __QSUB16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating subtract. More...
 
uint32_t __SHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction with halved results. More...
 
uint32_t __USUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract. More...
 
uint32_t __UQSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction. More...
 
uint32_t __UHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction with halved results. More...
 
uint32_t __SASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit addition and subtraction with exchange. More...
 
uint32_t __QASX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit add and subtract with exchange. More...
 
uint32_t __SHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition and subtraction with halved results. More...
 
uint32_t __UASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition and subtraction with exchange. More...
 
uint32_t __UQASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition and subtraction with exchange. More...
 
uint32_t __UHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition and subtraction with halved results and exchange. More...
 
uint32_t __SSAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction and addition with exchange. More...
 
uint32_t __QSAX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit subtract and add with exchange. More...
 
uint32_t __SHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction and addition with halved results. More...
 
uint32_t __USAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract and add with exchange. More...
 
uint32_t __UQSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction and addition with exchange. More...
 
uint32_t __UHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction and addition with halved results and exchange. More...
 
uint32_t __USAD8 (uint32_t val1, uint32_t val2)
 Unsigned sum of quad 8-bit unsigned absolute difference. More...
 
uint32_t __USADA8 (uint32_t val1, uint32_t val2, uint32_t val3)
 Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. More...
 
uint32_t __SSAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit saturate. More...
 
uint32_t __USAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit unsigned saturate. More...
 
uint32_t __UXTB16 (uint32_t val)
 Dual extract 8-bits and zero-extend to 16-bits. More...
 
uint32_t __UXTAB16 (uint32_t val1, uint32_t val2)
 Extracted 16-bit to 32-bit unsigned addition. More...
 
uint32_t __SXTB16 (uint32_t val)
 Dual extract 8-bits and sign extend each to 16-bits. More...
 
uint32_t __SXTAB16 (uint32_t val1, uint32_t val2)
 Dual extracted 8-bit to 16-bit signed addition. More...
 
uint32_t __SMUAD (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply. More...
 
uint32_t __SMUADX (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply with exchange. More...
 
uint32_t __SMMLA (int32_t val1, int32_t val2, int32_t val3)
 32-bit signed multiply with 32-bit truncated accumulator. More...
 
uint32_t __SMLAD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with single 32-bit accumulator. More...
 
uint32_t __SMLADX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. More...
 
uint64_t __SMLALD (uint32_t val1, uint32_t val2, uint64_t val3)
 Dual 16-bit signed multiply with single 64-bit accumulator. More...
 
unsigned long long __SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Dual 16-bit signed multiply with exchange with single 64-bit accumulator. More...
 
uint32_t __SMUSD (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply returning difference. More...
 
uint32_t __SMUSDX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply with exchange returning difference. More...
 
uint32_t __SMLSD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. More...
 
uint32_t __SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. More...
 
uint64_t __SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3)
 Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. More...
 
unsigned long long __SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. More...
 
uint32_t __SEL (uint32_t val1, uint32_t val2)
 Select bytes based on GE bits. More...
 
uint32_t __QADD (uint32_t val1, uint32_t val2)
 Q setting saturating add. More...
 
uint32_t __QSUB (uint32_t val1, uint32_t val2)
 Q setting saturating subtract. More...
 
uint32_t __PKHBT (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. More...
 
uint32_t __PKHTB (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. More...
 
+

Description

+

Single Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 cores to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.

+

SIMD Features:

+
    +
  • Simultaneous computation of 2x16-bit or 4x8-bit operands
    • +
  • Fractional arithmetic
    • +
  • User definable saturation modes (arbitrary word-width)
    • +
  • Dual 16x16 multiply-add/subtract 32x32 fractional MAC
    • +
  • Simultaneous 8/16-bit select operations
    • +
  • Performance up to 3.2 GOPS at 800MHz
    • +
  • Performance is achieved with a "near zero" increase in power consumption on a typical implementation
    • +
+

Examples:

+

Addition: Add two values using SIMD function

+
uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+
{
+
return __SADD16(val1, val2);
+
}
+

Subtraction: Subtract two values using SIMD function

+
uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+
{
+
return __SSUB16(val1, val2);
+
}
+

Multiplication: Performing a multiplication using SIMD function

+
uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+
{
+
return __SMUAD(val1, val2);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __PKHBT (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters
+ + + + +
val1first 16-bit operands
val2second 16-bit operands
val3value for left-shifting val2. Value range [0..31].
+
+
+
Returns
the combination of halfwords.
+
Operation:
res[15:0] = val1[15:0]
+
res[31:16] = val2[31:16]<<val3
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __PKHTB (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters
+ + + + +
val1second 16-bit operands
val2first 16-bit operands
val3value for right-shifting val2. Value range [1..32].
+
+
+
Returns
the combination of halfwords.
+
Operation:
res[15:0] = val2[15:0]>>val3
+
res[31:16] = val1[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to obtain the saturating add of two integers.
+ The Q bit is set if the operation saturates.

+
Parameters
+ + + +
val1first summand of the saturating add operation.
val2second summand of the saturating add operation.
+
+
+
Returns
the saturating addition of val1 and val2.
+
Operation:
res[31:0] = SAT(val1 + SAT(val2 * 2))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the saturated addition of the low halfwords, in the low halfword of the return value.
    • +
  • the saturated addition of the high halfwords, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the saturated addition of the first byte of each operand in the first byte of the return value.
    • +
  • the saturated addition of the second byte of each operand in the second byte of the return value.
    • +
  • the saturated addition of the third byte of each operand in the third byte of the return value.
    • +
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -27 <= x <= 27 - 1.
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value.
    • +
  • the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to obtain the saturating subtraction of two integers.
+ The Q bit is set if the operation saturates.

+
Parameters
+ + + +
val1minuend of the saturating subtraction operation.
val2subtrahend of the saturating subtraction operation.
+
+
+
Returns
the saturating subtraction of val1 and val2.
+
Operation:
res[31:0] = SAT(val1 - SAT(val2 * 2))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
    • +
  • the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
The returned results are saturated to the 8-bit signed integer range -27 <= x <= 27 - 1.
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed integer additions.
+ The GE bits in the APSR are set according to the results of the additions.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the addition of the low halfwords in the low halfword of the return value.
    • +
  • the addition of the high halfwords in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the addition of the second bytes of each operand, in the second byte of the return value.
    • +
  • the addition of the third bytes of each operand, in the third byte of the return value.
    • +
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[7:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SASX (uint32_t val1,
uint32_t val2 
)
+
+

This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APRS are set according to the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SEL (uint32_t val1,
uint32_t val2 
)
+
+

This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.

+
Parameters
+ + + +
val1four selectable 8-bit values.
val2four selectable 8-bit values.
+
+
+
Returns
The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria:
    +
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
    • +
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
    • +
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
    • +
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]
    • +
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two signed 16-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the halved addition of the low halfwords, in the low halfword of the return value.
    • +
  • the halved addition of the high halfwords, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1
+
res[31:16] = val1[31:16] + val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four signed 8-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes from each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1
+
res[15:8] = val1[15:8] + val2[15:8] >> 1
+
res[23:16] = val1[23:16] + val2[23:16] >> 1
+
res[31:24] = val1[31:24] + val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.

+
Parameters
+ + + +
val1first 16-bit operands.
val2second 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.

+
Parameters
+ + + +
val1first 16-bit operands.
val2second 16-bit operands.
+
+
+
Returns
    +
  • the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two signed 16-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
    • +
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1
+
res[31:16] = val1[31:16] - val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four signed 8-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1
+
res[15:8] = val1[15:8] - val2[15:8] >> 1
+
res[23:16] = val1[23:16] - val2[23:16] >> 1
+
res[31:24] = val1[31:24] - val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLAD (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value, as a 32-bit integer.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 + p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLADX (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 + p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint64_t __SMLALD (uint32_t val1,
uint32_t val2,
uint64_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
sum = p1 + p2 + val3[63:32][31:0]
+
res[63:32] = sum[63:32]
+
res[31:0] = sum[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
unsigned long long __SMLALDX (uint32_t val1,
uint32_t val2,
unsigned long long val3 
)
+
+

This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
sum = p1 + p2 + val3[63:32][31:0]
+
res[63:32] = sum[63:32]
+
res[31:0] = sum[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLSD (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.
+ The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 - p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLSDX (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 - p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint64_t __SMLSLD (uint32_t val1,
uint32_t val2,
uint64_t val3 
)
+
+

This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[63:0] = p1 - p2 + val3[63:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
unsigned long long __SMLSLDX (uint32_t val1,
uint32_t val2,
unsigned long long val3 
)
+
+

This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[63:0] = p1 - p2 + val3[63:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMMLA (int32_t val1,
int32_t val2,
int32_t val3 
)
+
+

This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
+

+
Parameters
+ + + + +
val1first operand for multiplication.
val2second operand for multiplication.
val3accumulate value.
+
+
+
Returns
the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
+
Operation:
p = val1 * val2
+
res[31:0] = p[61:32] + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUAD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, adding the products together.
+ The Q bit is set if the addition overflows.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the sum of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 + p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUADX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.
+ The Q bit is set if the addition overflows.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 + p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUSD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the difference of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 - p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUSDX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the difference of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 - p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAT16 (uint32_t val1,
const uint32_t val2 
)
+
+

This function enables you to saturate two signed 16-bit values to a selected signed range.
+ The Q bit is set if either operation saturates.

+
Parameters
+ + + +
val1two signed 16-bit values to be saturated.
val2bit position for saturation, an integral constant expression in the range 1 to 16.
+
+
+
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value:
    +
  • the signed saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
    • +
  • the signed saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • +
+
+
Operation:
Saturate halfwords in val1 to the signed range specified by the bit position in val2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit operands of each subtraction.
val2second two 16-bit operands of each subtraction.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If
    +
  • res is the return value, then:
    • +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit operands of each subtraction.
val2second four 8-bit operands of each subtraction.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
the results of the operation.
+
If res is the return value, then:
    +
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SXTAB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.

+
Parameters
+ + + +
val1values added to the zero-extended to 16-bit values.
val2two 8-bit values to be extracted and zero-extended.
+
+
+
Returns
the addition of val1 and val2, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.
+
Operation:
res[15:0] = val1[15:0] + SignExtended(val2[7:0])
+
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __SXTB16 (uint32_t val)
+
+

This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.

+
Parameters
+ + +
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
+
+
Returns
the 8-bit values sign-extended to 16-bit values.
    +
  • sign-extended value of val[7:0] in the low halfword of the return value.
    • +
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = SignExtended(val[7:0]
+
res[31:16] = SignExtended(val[23:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit unsigned integer additions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit summands for each addition.
val2second two 16-bit summands for each addition.
+
+
+
Returns
    +
  • the addition of the low halfwords in each operand, in the low halfword of the return value.
    • +
  • the addition of the high halfwords in each operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00
    • +
  • if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit summands for each addition.
val2second four 8-bit summands for each addition.
+
+
+
Returns
    +
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes from each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the halved addition of the low halfwords in each operand, in the low halfword of the return value.
    • +
  • the halved addition of the high halfwords in each operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1
+
res[31:16] = val1[31:16] + val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1
+
res[15:8] = val1[15:8] + val2[15:8] >> 1
+
res[23:16] = val1[23:16] + val2[23:16] >> 1
+
res[31:24] = val1[31:24] + val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand.
    • +
  • the halved addition of the high halfword in the first operand and the low halfword in the second operand.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] + val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1
+
res[31:16] = val1[31:16] - val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1
+
res[15:8] = val1[15:8] - val2[15:8] >> 1
+
res[23:16] = val1[23:16] - val2[23:16] >> 1
+
res[31:24] = val1[31:24] - val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+
+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters
+ + + +
val1first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword.
val2second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands for each subtraction.
val2second two 16-bit operands for each subtraction.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.

+
Parameters
+ + + +
val1first four 8-bit operands for the subtractions.
val2second four 8-bit operands for the subtractions.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • +
+
+
The sum is returned as a single unsigned integer.
+
Operation:
absdiff1 = val1[7:0] - val2[7:0]
+
absdiff2 = val1[15:8] - val2[15:8]
+
absdiff3 = val1[23:16] - val2[23:16]
+
absdiff4 = val1[31:24] - val2[31:24]
+
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __USADA8 (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.

+
Parameters
+ + + + +
val1first four 8-bit operands for the subtractions.
val2second four 8-bit operands for the subtractions.
val3accumulation value.
+
+
+
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value:
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • +
+
+
Operation:
absdiff1 = val1[7:0] - val2[7:0]
+
absdiff2 = val1[15:8] - val2[15:8]
+
absdiff3 = val1[23:16] - val2[23:16]
+
absdiff4 = val1[31:24] - val2[31:24]
+
sum = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
res[31:0] = sum[31:0] + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAT16 (uint32_t val1,
const uint32_t val2 
)
+
+

This function enables you to saturate two signed 16-bit values to a selected unsigned range.
+ The Q bit is set if either operation saturates.

+
Parameters
+ + + +
val1two 16-bit values that are to be saturated.
val2bit position for saturation, and must be an integral constant expression in the range 0 to 15.
+
+
+
Returns
the saturation of the two signed 16-bit values, as non-negative values.
    +
  • the saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
    • +
  • the saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • +
+
+
Operation:
Saturate halfwords in val1 to the unsigned range specified by the bit position in val2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit unsigned integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UXTAB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.

+
Parameters
+ + + +
val1value added to the zero-extended to 16-bit values.
val2two 8-bit values to be extracted and zero-extended.
+
+
+
Returns
the 8-bit values in val2, zero-extended to 16-bit values and added to val1.
+
Operation:
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0]
+
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __UXTB16 (uint32_t val)
+
+

This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.

+
Parameters
+ + +
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
+
+
Returns
the 8-bit values zero-extended to 16-bit values.
    +
  • zero-extended value of val[7:0] in the low halfword of the return value.
    • +
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = ZeroExtended(val[7:0] )
+
res[31:16] = ZeroExtended(val[23:16])
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.js new file mode 100644 index 000000000..ef0bb50f3 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.js @@ -0,0 +1,65 @@ +var group__intrinsic___s_i_m_d__gr = +[ + [ "__PKHBT", "group__intrinsic___s_i_m_d__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5", null ], + [ "__PKHTB", "group__intrinsic___s_i_m_d__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666", null ], + [ "__QADD", "group__intrinsic___s_i_m_d__gr.html#ga17b873f246c9f5e9355760ffef3dad4a", null ], + [ "__QADD16", "group__intrinsic___s_i_m_d__gr.html#gae83a53ec04b496304bed6d9fe8f7461b", null ], + [ "__QADD8", "group__intrinsic___s_i_m_d__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713", null ], + [ "__QASX", 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b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html @@ -0,0 +1,228 @@ + + + + + +CMSIS-CORE: Peripheral Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Peripheral Access
+
+
+ +

Describes naming conventions, requirements, and optional features for accessing peripherals. +More...

+

Each peripheral provides a data type definition with a name that is composed of a prefix <device abbreviation>_ and the <peripheral name>_, for example LPC_UART for the device LPC and the peripheral UART. The intention is to avoid name collisions caused by short names. If more peripherals exist of the same type, identifiers have a postfix consisting of a digit or letter, for example LPC_UART0, LPC_UART1.

+
    +
  • The data type definition uses the standard C data types from the ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers and are defined as shown below:
    +
    #define __I volatile const
    +
    #define __O volatile
    +
    #define __IO volatile
    +
    • +
+
    +
  • The following typedef is an example for a UART. <device abbreviation>_UART_TypeDef: defines the generic register layout for all UART channels in a device.
    +
    typedef struct
    +
    {
    +
    union {
    +
    __I uint8_t RBR; /* Offset: 0x000 (R/ ) Receiver Buffer Register */
    +
    __O uint8_t THR; /* Offset: 0x000 ( /W) Transmit Holding Register */
    +
    __IO uint8_t DLL; /* Offset: 0x000 (R/W) Divisor Latch LSB */
    +
    uint32_t RESERVED0;
    +
    };
    +
    union {
    +
    __IO uint8_t DLM; /* Offset: 0x004 (R/W) Divisor Latch MSB */
    +
    __IO uint32_t IER; /* Offset: 0x004 (R/W) Interrupt Enable Register */
    +
    };
    +
    union {
    +
    __I uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt ID Register */
    +
    __O uint8_t FCR; /* Offset: 0x008 ( /W) FIFO Control Register */
    +
    };
    +
    __IO uint8_t LCR; /* Offset: 0x00C (R/W) Line Control Register */
    +
    uint8_t RESERVED1[7];
    +
    __I uint8_t LSR; /* Offset: 0x014 (R/ ) Line Status Register */
    +
    uint8_t RESERVED2[7];
    +
    __IO uint8_t SCR; /* Offset: 0x01C (R/W) Scratch Pad Register */
    +
    uint8_t RESERVED3[3];
    +
    __IO uint32_t ACR; /* Offset: 0x020 (R/W) Autobaud Control Register */
    +
    __IO uint8_t ICR; /* Offset: 0x024 (R/W) IrDA Control Register */
    +
    uint8_t RESERVED4[3];
    +
    __IO uint8_t FDR; /* Offset: 0x028 (R/W) Fractional Divider Register */
    +
    uint8_t RESERVED5[7];
    +
    __IO uint8_t TER; /* Offset: 0x030 (R/W) Transmit Enable Register */
    +
    uint8_t RESERVED6[39];
    +
    __I uint8_t FIFOLVL; /* Offset: 0x058 (R/ ) FIFO Level Register */
    +
    } LPC_UART_TypeDef;
    +
    • +
+
    +
  • To access the registers of the UART defined above, pointers to a register structure are defined. In this example <device abbreviation>_UART# are two pointers to UARTs defined with above register structure.
    +
    #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
    +
    #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
    +
    • +
+
    +
  • The registers in the various UARTs can now be referred in the user code as shown below:
    +
    LPC_UART1->DR // is the data register of UART1.
    +
    • +
+
+

+Minimal Requirements

+

To access the peripheral registers and related function in a device, the files device.h and core_cm#.h define as a minimum:
+
+

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers.
    +
    + Example:
    typedef struct
    +
    {
    +
    __IO uint32_t CTRL; /* Offset: 0x000 (R/W) SysTick Control and Status Register */
    +
    __IO uint32_t LOAD; /* Offset: 0x004 (R/W) SysTick Reload Value Register */
    +
    __IO uint32_t VAL; /* Offset: 0x008 (R/W) SysTick Current Value Register */
    +
    __I uint32_t CALIB; /* Offset: 0x00C (R/ ) SysTick Calibration Register */
    +
    } SysTick_Type;
    +
    • +
+
    +
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined).
    +
    + Example:
    #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */
    +
    • +
+
    +
  • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typdef, multiple access definitions exist (LPC_UART0, LPC_UART2).
    +
    + Example:
    #define SysTick ((SysTick_Type *) Systick_BASE) /* SysTick access definition */
    +
    • +
+

These definitions allow accessing peripheral registers with simple assignments.

+

Example:
+

+
SysTick->CTRL = 0;
+
+

+Optional Features

+

Optionally, the file device.h may define:

+
    +
  • #define constants, which simplify access to peripheral registers. These constants define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants.
    • +
+
    +
  • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_.
    • +
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html new file mode 100644 index 000000000..47694bb18 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html @@ -0,0 +1,229 @@ + + + + + +CMSIS-CORE: System and Clock Configuration + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
System and Clock Configuration
+
+
+ + + + + + + + +

+Functions

void SystemInit (void)
 Function to Initialize the system. More...
 
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock. More...
 
+ + + + +

+Variables

uint32_t SystemCoreClock
 Variable to hold the system core clock value. More...
 
+

Description

+
ARM provides a template file <b>system_<i>device</i>.c</b> that must be adapted by 
+the silicon vendor to match their actual device. As a <b>minimum requirement</b>, 
+this file must provide:
+-  A device-specific system configuration function, \ref SystemInit().
+-  A global variable that contains the system frequency, \ref SystemCoreClock. 
+
+The file configures the device and, typically, initializes the oscillator (PLL) that is part 
+of the microcontroller device. This file might export other functions or variables that provide 
+a more flexible configuration of the microcontroller system.
+

+Code Example

+

The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t coreClock_1 = 0; /* Variables to store core clock values */
+
uint32_t coreClock_2 = 0;
+
+
+
int main (void) {
+
+
coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */
+
+
SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */
+
+
coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */
+
+
if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */
+
// Error Handling
+
}
+
+
while(1);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
void SystemCoreClockUpdate (void )
+
+

Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.

+ +
+
+ +
+
+ + + + + + + + +
void SystemInit (void )
+
+

Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.

+ +
+
+

Variable Documentation

+ +
+
+ + + + +
uint32_t SystemCoreClock
+
+

Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

+
Attention
Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__system__init__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__system__init__gr.js new file mode 100644 index 000000000..1ed21ea5e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/group__system__init__gr.js @@ -0,0 +1,6 @@ +var group__system__init__gr = +[ + [ "SystemCoreClockUpdate", "group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f", null ], + [ "SystemInit", "group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2", null ], + [ "SystemCoreClock", "group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/index.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/index.html new file mode 100644 index 000000000..8cf0d4b40 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/index.html @@ -0,0 +1,210 @@ + + + + + +CMSIS-CORE: Overview + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • +
+
+

This chapter provides details about the CMSIS-CORE and contains the following sections:

+ +
+

+Cortex-M Reference Manuals

+

The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

+ +
+

+Tested and Verified Toolchains

+

The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

+
    +
  • ARM: MDK-ARM Version 4.70 (or greater)
    • +
  • GNU: GNU Tools ARM Embedded 4.7 2012.q4 (or greater)
    • +
  • GNU: Sourcery G++ Lite Edition for ARM 2011.03-42 (or greater)
    • +
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10 (or greater)
    • +
+
+

Revision History of CMSIS-CORE

+ + + + + + + + + + + + + + + + + + + + + +
Version Description
V3.20 Added: __BKPT instruction intrinsic.
+ Added: __SMMLA instruction intrinsic for Cortex-M4.
+ Corrected: ITM_SendChar.
+ Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
+ Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.
+
V3.01 Added support for Cortex-M0+ processor.
+ Integration of CMSIS DSP Library version 1.1.0
+
V3.00 Added support for GNU GCC ARM Embedded Compiler.
+ Added function __ROR.
+ Added Register Mapping for TPIU, DWT.
+ Added support for SC000 and SC300 processors.
+ Corrected ITM_SendChar function.
+ Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
+ Documentation restructured.
V2.10 Updated documentation.
+ Updated CMSIS core include files.
+ Changed CMSIS/Device folder structure.
+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
+ Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
+ Added additional Debug Functionality.
+ Changed folder structure.
+ Added doxygen comments.
+ Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/jquery.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/jquery.js new file mode 100644 index 000000000..78ad0bdff --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/jquery.js @@ -0,0 +1,77 @@ +/*! jQuery v1.7.1 jquery.com | jquery.org/license */ +(function(a,b){function cy(a){return f.isWindow(a)?a:a.nodeType===9?a.defaultView||a.parentWindow:!1}function cv(a){if(!ck[a]){var b=c.body,d=f("<"+a+">").appendTo(b),e=d.css("display");d.remove();if(e==="none"||e===""){cl||(cl=c.createElement("iframe"),cl.frameBorder=cl.width=cl.height=0),b.appendChild(cl);if(!cm||!cl.createElement)cm=(cl.contentWindow||cl.contentDocument).document,cm.write((c.compatMode==="CSS1Compat"?"":"")+""),cm.close();d=cm.createElement(a),cm.body.appendChild(d),e=f.css(d,"display"),b.removeChild(cl)}ck[a]=e}return ck[a]}function cu(a,b){var c={};f.each(cq.concat.apply([],cq.slice(0,b)),function(){c[this]=a});return c}function ct(){cr=b}function cs(){setTimeout(ct,0);return cr=f.now()}function cj(){try{return new a.ActiveXObject("Microsoft.XMLHTTP")}catch(b){}}function ci(){try{return new a.XMLHttpRequest}catch(b){}}function cc(a,c){a.dataFilter&&(c=a.dataFilter(c,a.dataType));var d=a.dataTypes,e={},g,h,i=d.length,j,k=d[0],l,m,n,o,p;for(g=1;g0){if(c!=="border")for(;g=0===c})}function S(a){return!a||!a.parentNode||a.parentNode.nodeType===11}function K(){return!0}function J(){return!1}function n(a,b,c){var d=b+"defer",e=b+"queue",g=b+"mark",h=f._data(a,d);h&&(c==="queue"||!f._data(a,e))&&(c==="mark"||!f._data(a,g))&&setTimeout(function(){!f._data(a,e)&&!f._data(a,g)&&(f.removeData(a,d,!0),h.fire())},0)}function m(a){for(var b in a){if(b==="data"&&f.isEmptyObject(a[b]))continue;if(b!=="toJSON")return!1}return!0}function l(a,c,d){if(d===b&&a.nodeType===1){var e="data-"+c.replace(k,"-$1").toLowerCase();d=a.getAttribute(e);if(typeof d=="string"){try{d=d==="true"?!0:d==="false"?!1:d==="null"?null:f.isNumeric(d)?parseFloat(d):j.test(d)?f.parseJSON(d):d}catch(g){}f.data(a,c,d)}else d=b}return d}function h(a){var b=g[a]={},c,d;a=a.split(/\s+/);for(c=0,d=a.length;c)[^>]*$|#([\w\-]*)$)/,j=/\S/,k=/^\s+/,l=/\s+$/,m=/^<(\w+)\s*\/?>(?:<\/\1>)?$/,n=/^[\],:{}\s]*$/,o=/\\(?:["\\\/bfnrt]|u[0-9a-fA-F]{4})/g,p=/"[^"\\\n\r]*"|true|false|null|-?\d+(?:\.\d*)?(?:[eE][+\-]?\d+)?/g,q=/(?:^|:|,)(?:\s*\[)+/g,r=/(webkit)[ \/]([\w.]+)/,s=/(opera)(?:.*version)?[ \/]([\w.]+)/,t=/(msie) ([\w.]+)/,u=/(mozilla)(?:.*? rv:([\w.]+))?/,v=/-([a-z]|[0-9])/ig,w=/^-ms-/,x=function(a,b){return(b+"").toUpperCase()},y=d.userAgent,z,A,B,C=Object.prototype.toString,D=Object.prototype.hasOwnProperty,E=Array.prototype.push,F=Array.prototype.slice,G=String.prototype.trim,H=Array.prototype.indexOf,I={};e.fn=e.prototype={constructor:e,init:function(a,d,f){var g,h,j,k;if(!a)return this;if(a.nodeType){this.context=this[0]=a,this.length=1;return this}if(a==="body"&&!d&&c.body){this.context=c,this[0]=c.body,this.selector=a,this.length=1;return this}if(typeof a=="string"){a.charAt(0)!=="<"||a.charAt(a.length-1)!==">"||a.length<3?g=i.exec(a):g=[null,a,null];if(g&&(g[1]||!d)){if(g[1]){d=d instanceof e?d[0]:d,k=d?d.ownerDocument||d:c,j=m.exec(a),j?e.isPlainObject(d)?(a=[c.createElement(j[1])],e.fn.attr.call(a,d,!0)):a=[k.createElement(j[1])]:(j=e.buildFragment([g[1]],[k]),a=(j.cacheable?e.clone(j.fragment):j.fragment).childNodes);return e.merge(this,a)}h=c.getElementById(g[2]);if(h&&h.parentNode){if(h.id!==g[2])return f.find(a);this.length=1,this[0]=h}this.context=c,this.selector=a;return this}return!d||d.jquery?(d||f).find(a):this.constructor(d).find(a)}if(e.isFunction(a))return f.ready(a);a.selector!==b&&(this.selector=a.selector,this.context=a.context);return e.makeArray(a,this)},selector:"",jquery:"1.7.1",length:0,size:function(){return this.length},toArray:function(){return F.call(this,0)},get:function(a){return a==null?this.toArray():a<0?this[this.length+a]:this[a]},pushStack:function(a,b,c){var d=this.constructor();e.isArray(a)?E.apply(d,a):e.merge(d,a),d.prevObject=this,d.context=this.context,b==="find"?d.selector=this.selector+(this.selector?" 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a(j){j=j||location.href;return"#"+j.replace(/^[^#]*#?(.*)$/,"$1")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,"")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$(' + + +
+
+
Reference
+
+
+
Here is a list of all modules:
+
+ + + + + + + + +
oPeripheral AccessDescribes naming conventions, requirements, and optional features for accessing peripherals
oSystem and Clock Configuration
oInterrupts and Exceptions (NVIC)Describes programming of interrupts and exception functions
oCore Register Access
oIntrinsic Functions for CPU Instructions
oIntrinsic Functions for SIMD Instructions [only Cortex-M4]Access to dedicated SIMD instructions
oSystick Timer (SYSTICK)Initialize and start the SysTick timer
\Debug Access
+ + + + + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/modules.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/modules.js new file mode 100644 index 000000000..70bfdfa27 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/modules.js @@ -0,0 +1,11 @@ +var modules = +[ + [ "Peripheral Access", "group__peripheral__gr.html", null ], + [ "System and Clock Configuration", "group__system__init__gr.html", "group__system__init__gr" ], + [ "Interrupts and Exceptions (NVIC)", "group___n_v_i_c__gr.html", "group___n_v_i_c__gr" ], + [ "Core Register Access", "group___core___register__gr.html", "group___core___register__gr" ], + [ "Intrinsic Functions for CPU Instructions", "group__intrinsic___c_p_u__gr.html", "group__intrinsic___c_p_u__gr" ], + [ "Intrinsic Functions for SIMD Instructions [only Cortex-M4]", "group__intrinsic___s_i_m_d__gr.html", "group__intrinsic___s_i_m_d__gr" ], + [ "Systick Timer (SYSTICK)", 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docContent.height()-docContent.scrollTop())); + animationInProgress=true; + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + if (updateLocation) window.location.href=aname; + animationInProgress=false; + }); + } +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + node.expanded = false; + a.appendChild(node.label); + if (link) { + var url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + link = url; + } else { + url = node.relpath+link; + } + a.className = stripPath(link.replace('#',':')); + if (link.indexOf('#')!=-1) { + var aname = '#'+link.split('#')[1]; + var srcPage = stripPath($(location).attr('pathname')); + var targetPage = stripPath(link.split('#')[0]); + a.href = srcPage!=targetPage ? url : "javascript:void(0)"; + a.onclick = function(){ + storeLink(link); + if (!$(a).parent().parent().hasClass('selected')) + { + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + $(a).parent().parent().addClass('selected'); + $(a).parent().parent().attr('id','selected'); + } + var anchor = $(aname); + gotoAnchor(anchor,aname,true); + }; + } else { + a.href = url; + a.onclick = function() { storeLink(link); } + } + } else { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() { + if (!node.childrenUL) { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } if (imm || ($.browser.msie && $.browser.version>8)) { + // somehow slideDown jumps to the start of tree for IE9 :-( + $(node.getChildrenUL()).show(); + } else { + $(node.getChildrenUL()).slideDown("fast"); + } + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var aname = $(location).attr('hash'); + var anchor = $(aname); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+ + window.location.hash.substring(1)+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parents().slice(2).prop('tagName')=='TR') { + glowEffect(anchor.parents('div.memitem'),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if (anchor.parent().is(":header")) { + glowEffect(anchor.parent(),1000); // section header + } else { + glowEffect(anchor.next(),1000); // normal member + } + gotoAnchor(anchor,aname,false); +} + +function selectAndHighlight(hash,n) +{ + var a; + if (hash) { + var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1); + a=$('.item a[class$="'+link+'"]'); + } + if (a && a.length) { + a.parent().parent().addClass('selected'); + a.parent().parent().attr('id','selected'); + highlightAnchor(); + } else if (n) { + $(n.itemDiv).addClass('selected'); + $(n.itemDiv).attr('id','selected'); + } + if ($('#nav-tree-contents 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b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/pages.html @@ -0,0 +1,139 @@ + + + + + +CMSIS-CORE: Usage and Description + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Usage and Description
+
+
+
Here is a list of all related documentation pages:
+
[detail level 12]
+ + + + + + + + +
oUsing CMSIS in Embedded Applications
|\Using CMSIS with generic ARM Processors
oTemplate Files
|oStartup File startup_<device>.s
|oSystem Configuration Files system_<device>.c and system_<device>.h
|\Device Header File <device.h>
oMISRA-C:2004 Compliance Exceptions
\Register Mapping
+
+
+
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+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_63.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_63.js new file mode 100644 index 000000000..e3d96d37f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_63.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['core_20register_20access',['Core Register Access',['../group___core___register__gr.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_64.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_64.html new file mode 100644 index 000000000..2e42c7eaf --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_64.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_64.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_64.js new file mode 100644 index 000000000..3088d63c2 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_64.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['debug_20access',['Debug Access',['../group___i_t_m___debug__gr.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_69.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_69.html new file mode 100644 index 000000000..9a24ad43f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_69.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_69.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_69.js new file mode 100644 index 000000000..fd2b1316f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_69.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['intrinsic_20functions_20for_20cpu_20instructions',['Intrinsic Functions for CPU Instructions',['../group__intrinsic___c_p_u__gr.html',1,'']]], + ['intrinsic_20functions_20for_20simd_20instructions_20_5bonly_20cortex_2dm4_5d',['Intrinsic Functions for SIMD Instructions [only Cortex-M4]',['../group__intrinsic___s_i_m_d__gr.html',1,'']]], + ['interrupts_20and_20exceptions_20_28nvic_29',['Interrupts and Exceptions (NVIC)',['../group___n_v_i_c__gr.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_70.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_70.html new file mode 100644 index 000000000..3f108b52a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_70.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_70.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_70.js new file mode 100644 index 000000000..46a72501a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_70.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['peripheral_20access',['Peripheral Access',['../group__peripheral__gr.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_73.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_73.html new file mode 100644 index 000000000..d77ec54c8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_73.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_73.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_73.js new file mode 100644 index 000000000..e5758abe8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/groups_73.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['system_20and_20clock_20configuration',['System and Clock Configuration',['../group__system__init__gr.html',1,'']]], + ['systick_20timer_20_28systick_29',['Systick Timer (SYSTICK)',['../group___sys_tick__gr.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/mag_sel.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/mag_sel.png new file mode 100644 index 000000000..81f6040a2 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/mag_sel.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/nomatches.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/nomatches.html new file mode 100644 index 000000000..b1ded27e9 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/nomatches.html @@ -0,0 +1,12 @@ + + + + + + + +
+
No Matches
+
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_64.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_64.html new file mode 100644 index 000000000..e404fbfc2 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_64.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_64.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_64.js new file mode 100644 index 000000000..538e9d387 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_64.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['device_20header_20file_20_3cdevice_2eh_3e',['Device Header File <device.h>',['../device_h_pg.html',1,'Templates_pg']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6d.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6d.html new file mode 100644 index 000000000..9737d8158 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6d.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6d.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6d.js new file mode 100644 index 000000000..84ebce34a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6d.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['misra_2dc_3a2004_20compliance_20exceptions',['MISRA-C:2004 Compliance Exceptions',['../_c_o_r_e__m_i_s_r_a__exceptions_pg.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6f.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6f.html new file mode 100644 index 000000000..e22842bf0 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6f.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6f.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6f.js new file mode 100644 index 000000000..277cca084 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_6f.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['overview',['Overview',['../index.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_72.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_72.html new file mode 100644 index 000000000..5e9722171 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_72.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_72.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_72.js new file mode 100644 index 000000000..5d0682824 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_72.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['register_20mapping',['Register Mapping',['../_reg_map_pg.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_73.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_73.html new file mode 100644 index 000000000..4f6f00297 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_73.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_73.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_73.js new file mode 100644 index 000000000..85147d5a1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_73.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['startup_20file_20startup_5f_3cdevice_3e_2es',['Startup File startup_<device>.s',['../startup_s_pg.html',1,'Templates_pg']]], + ['system_20configuration_20files_20system_5f_3cdevice_3e_2ec_20and_20system_5f_3cdevice_3e_2eh',['System Configuration Files system_<device>.c and system_<device>.h',['../system_c_pg.html',1,'Templates_pg']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_74.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_74.html new file mode 100644 index 000000000..90a80a10e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_74.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_74.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_74.js new file mode 100644 index 000000000..abdc31ddc --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_74.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['template_20files',['Template Files',['../_templates_pg.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_75.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_75.html new file mode 100644 index 000000000..71718e39e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_75.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_75.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_75.js new file mode 100644 index 000000000..9165f4b67 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/pages_75.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['using_20cmsis_20with_20generic_20arm_20processors',['Using CMSIS with generic ARM Processors',['../_using__a_r_m_pg.html',1,'Using_pg']]], + ['using_20cmsis_20in_20embedded_20applications',['Using CMSIS in Embedded Applications',['../_using_pg.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/search.css b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/search.css new file mode 100644 index 000000000..1746d13fd --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/search.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/search.js new file mode 100644 index 000000000..d77e18d18 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/search.js @@ -0,0 +1,811 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101001000110000110001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000001000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001110111111110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100010000110100101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100001000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000101001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "enums", + 6: "enumvalues", + 7: "groups", + 8: "pages" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var hexCode; + if (code<16) + { + hexCode="0"+code.toString(16); + } + else + { + hexCode=code.toString(16); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1') + { + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_5f.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_5f.js new file mode 100644 index 000000000..208e0d981 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_5f.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['_5freserved0',['_reserved0',['../union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728',1,'APSR_Type::_reserved0()'],['../union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa',1,'IPSR_Type::_reserved0()'],['../unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5',1,'xPSR_Type::_reserved0()'],['../union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50',1,'CONTROL_Type::_reserved0()']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_61.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_61.html new file mode 100644 index 000000000..a0de7a473 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_61.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_61.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_61.js new file mode 100644 index 000000000..ac0cd14e9 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_61.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['acpr',['ACPR',['../struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab',1,'TPI_Type']]], + ['actlr',['ACTLR',['../struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d',1,'SCnSCB_Type']]], + ['adr',['ADR',['../struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2',1,'SCB_Type']]], + ['afsr',['AFSR',['../struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef',1,'SCB_Type']]], + ['aircr',['AIRCR',['../struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d',1,'SCB_Type']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_62.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_62.html new file mode 100644 index 000000000..ff4152508 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_62.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_62.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_62.js new file mode 100644 index 000000000..ee25e5777 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_62.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['b',['b',['../union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14',1,'APSR_Type::b()'],['../union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50',1,'IPSR_Type::b()'],['../unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70',1,'xPSR_Type::b()'],['../union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9',1,'CONTROL_Type::b()']]], + ['bfar',['BFAR',['../struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a',1,'SCB_Type']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_63.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_63.html new file mode 100644 index 000000000..422085c12 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_63.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_63.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_63.js new file mode 100644 index 000000000..69c4547e7 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_63.js @@ -0,0 +1,19 @@ +var searchData= +[ + ['c',['C',['../union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6',1,'APSR_Type::C()'],['../unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d',1,'xPSR_Type::C()']]], + ['calib',['CALIB',['../struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238',1,'SysTick_Type']]], + ['ccr',['CCR',['../struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8',1,'SCB_Type']]], + ['cfsr',['CFSR',['../struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4',1,'SCB_Type']]], + ['claimclr',['CLAIMCLR',['../struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad',1,'TPI_Type']]], + ['claimset',['CLAIMSET',['../struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84',1,'TPI_Type']]], + ['comp0',['COMP0',['../struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904',1,'DWT_Type']]], + ['comp1',['COMP1',['../struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c',1,'DWT_Type']]], + ['comp2',['COMP2',['../struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332',1,'DWT_Type']]], + ['comp3',['COMP3',['../struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f',1,'DWT_Type']]], + ['cpacr',['CPACR',['../struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85',1,'SCB_Type']]], + ['cpicnt',['CPICNT',['../struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc',1,'DWT_Type']]], + ['cpuid',['CPUID',['../struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032',1,'SCB_Type']]], + ['cspsr',['CSPSR',['../struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a',1,'TPI_Type']]], + ['ctrl',['CTRL',['../struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f',1,'SysTick_Type::CTRL()'],['../struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328',1,'MPU_Type::CTRL()'],['../struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d',1,'DWT_Type::CTRL()']]], + ['cyccnt',['CYCCNT',['../struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4',1,'DWT_Type']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_64.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_64.html new file mode 100644 index 000000000..df4414b92 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_64.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_64.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_64.js new file mode 100644 index 000000000..4b62d2b1f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_64.js @@ -0,0 +1,11 @@ +var searchData= +[ + ['dcrdr',['DCRDR',['../struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9',1,'CoreDebug_Type']]], + ['dcrsr',['DCRSR',['../struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983',1,'CoreDebug_Type']]], + ['demcr',['DEMCR',['../struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d',1,'CoreDebug_Type']]], + ['devid',['DEVID',['../struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d',1,'TPI_Type']]], + ['devtype',['DEVTYPE',['../struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35',1,'TPI_Type']]], + ['dfr',['DFR',['../struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86',1,'SCB_Type']]], + ['dfsr',['DFSR',['../struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d',1,'SCB_Type']]], + ['dhcsr',['DHCSR',['../struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d',1,'CoreDebug_Type']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_65.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_65.html new file mode 100644 index 000000000..38eb9f67f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_65.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
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+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_65.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_65.js new file mode 100644 index 000000000..3e9c2376e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_65.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['exccnt',['EXCCNT',['../struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82',1,'DWT_Type']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_66.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_66.html new file mode 100644 index 000000000..6e1863868 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_66.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_66.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_66.js new file mode 100644 index 000000000..5b83ef5ec --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_66.js @@ -0,0 +1,17 @@ +var searchData= +[ + ['ffcr',['FFCR',['../struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880',1,'TPI_Type']]], + ['ffsr',['FFSR',['../struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd',1,'TPI_Type']]], + ['fifo0',['FIFO0',['../struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10',1,'TPI_Type']]], + ['fifo1',['FIFO1',['../struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e',1,'TPI_Type']]], + ['foldcnt',['FOLDCNT',['../struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab',1,'DWT_Type']]], + ['fpca',['FPCA',['../union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd',1,'CONTROL_Type']]], + ['fpcar',['FPCAR',['../struct_f_p_u___type.html#aa48253f088dc524de80c42fbc995f66b',1,'FPU_Type']]], + ['fpccr',['FPCCR',['../struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8',1,'FPU_Type']]], + ['fpdscr',['FPDSCR',['../struct_f_p_u___type.html#a4d58ef3ebea69a5ec5acd8c90a9941b6',1,'FPU_Type']]], + ['fscr',['FSCR',['../struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef',1,'TPI_Type']]], + ['function0',['FUNCTION0',['../struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729',1,'DWT_Type']]], + ['function1',['FUNCTION1',['../struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747',1,'DWT_Type']]], + ['function2',['FUNCTION2',['../struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b',1,'DWT_Type']]], + ['function3',['FUNCTION3',['../struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890',1,'DWT_Type']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_68.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_68.html new file mode 100644 index 000000000..2f0a862b9 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_68.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
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+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_76.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_76.js new file mode 100644 index 000000000..57cd49968 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_76.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['v',['V',['../union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e',1,'APSR_Type::V()'],['../unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a',1,'xPSR_Type::V()']]], + ['val',['VAL',['../struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4',1,'SysTick_Type']]], + ['vtor',['VTOR',['../struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f',1,'SCB_Type']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_77.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_77.html new file mode 100644 index 000000000..434c6df9e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_77.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
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+
+ +
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+
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+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_77.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_77.js new file mode 100644 index 000000000..7681c0fc8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_77.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['w',['w',['../union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94',1,'APSR_Type::w()'],['../union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879',1,'IPSR_Type::w()'],['../unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2',1,'xPSR_Type::w()'],['../union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f',1,'CONTROL_Type::w()']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_7a.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_7a.html new file mode 100644 index 000000000..8a5710483 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_7a.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
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+
+ +
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+
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+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_7a.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_7a.js new file mode 100644 index 000000000..ed348a5b6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/search/variables_7a.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['z',['Z',['../union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5',1,'APSR_Type::Z()'],['../unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562',1,'xPSR_Type::Z()']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/startup_s_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/startup_s_pg.html new file mode 100644 index 000000000..63f5b2d86 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/startup_s_pg.html @@ -0,0 +1,369 @@ + + + + + +CMSIS-CORE: Startup File startup_<device>.s + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Startup File startup_<device>.s
+
+
+

The Startup File startup_<device>.s contains:

+
    +
  • The reset handler which is executed after CPU reset and typically calls the SystemInit function.
    • +
  • The setup values for the Main Stack Pointer (MSP).
    • +
  • Exception vectors of the Cortex-M Processor with weak functions that implement default routines.
    • +
  • Interrupt vectors that are device specific with weak functions that implement default routines.
    • +
+

The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.

+

To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with IRQn_Type that defines all the IRQ numbers for each interrupt.

+

Example:

+

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

+
; External Interrupts
+
DCD WAKEUP0_IRQHandler ; 16+ 0: Wakeup PIO0.0
+
DCD WAKEUP1_IRQHandler ; 16+ 1: Wakeup PIO0.1
+
DCD WAKEUP2_IRQHandler ; 16+ 2: Wakeup PIO0.2
+
: :
+
: :
+
DCD EINT1_IRQHandler ; 16+30: PIO INT1
+
DCD EINT0_IRQHandler ; 16+31: PIO INT0
+
:
+
:
+
EXPORT WAKEUP0_IRQHandler [WEAK]
+
EXPORT WAKEUP1_IRQHandler [WEAK]
+
EXPORT WAKEUP2_IRQHandler [WEAK]
+
: :
+
: :
+
EXPORT EINT1_IRQHandler [WEAK]
+
EXPORT EINT0_IRQHandler [WEAK]
+
+
WAKEUP0_IRQHandler
+
WAKEUP1_IRQHandler
+
WAKEUP1_IRQHandler
+
:
+
:
+
EINT1_IRQHandler
+
EINT0_IRQHandler
+
B .
+

+startup_Device.s Template File

+

The startup_Device.s Template File for the Cortex-M3 and the ARMCC compiler is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.

+
;/**************************************************************************//**
+; * @file     startup_<Device>.s
+; * @brief    CMSIS Cortex-M# Core Device Startup File for
+; *           Device <Device>
+; * @version  V3.10
+; * @date     23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2012 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+; ToDo:  Add here the vectors for the device specific external interrupts handler
+                DCD     <DeviceInterrupt>_IRQHandler       ;  0: Default
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; ToDo:  Add here the export definition for the device specific external interrupts handler
+                EXPORT  <DeviceInterrupt>_IRQHandler         [WEAK]
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+<DeviceInterrupt>_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html new file mode 100644 index 000000000..425fe2d6c --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html @@ -0,0 +1,204 @@ + + + + + +CMSIS-CORE: CoreDebug_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
CoreDebug_Type Struct Reference
+
+
+ +

Structure type to access the Core Debug Register (CoreDebug). +

+ + + + + + + + + + + + + + +

+Data Fields

__IO uint32_t DHCSR
 Offset: 0x000 (R/W) Debug Halting Control and Status Register. More...
 
__O uint32_t DCRSR
 Offset: 0x004 ( /W) Debug Core Register Selector Register. More...
 
__IO uint32_t DCRDR
 Offset: 0x008 (R/W) Debug Core Register Data Register. More...
 
__IO uint32_t DEMCR
 Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IO uint32_t CoreDebug_Type::DCRDR
+
+ +
+
+ +
+
+ + + + +
__O uint32_t CoreDebug_Type::DCRSR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t CoreDebug_Type::DEMCR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t CoreDebug_Type::DHCSR
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.js new file mode 100644 index 000000000..d82bc5331 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.js @@ -0,0 +1,7 @@ +var struct_core_debug___type = +[ + [ "DCRDR", "struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9", null ], + [ "DCRSR", "struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983", null ], + [ "DEMCR", "struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d", null ], + [ "DHCSR", "struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html new file mode 100644 index 000000000..aaf7af1d3 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html @@ -0,0 +1,489 @@ + + + + + +CMSIS-CORE: DWT_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
DWT_Type Struct Reference
+
+
+ +

Structure type to access the Data Watchpoint and Trace Register (DWT). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

__IO uint32_t CTRL
 Offset: 0x000 (R/W) Control Register. More...
 
__IO uint32_t CYCCNT
 Offset: 0x004 (R/W) Cycle Count Register. More...
 
__IO uint32_t CPICNT
 Offset: 0x008 (R/W) CPI Count Register. More...
 
__IO uint32_t EXCCNT
 Offset: 0x00C (R/W) Exception Overhead Count Register. More...
 
__IO uint32_t SLEEPCNT
 Offset: 0x010 (R/W) Sleep Count Register. More...
 
__IO uint32_t LSUCNT
 Offset: 0x014 (R/W) LSU Count Register. More...
 
__IO uint32_t FOLDCNT
 Offset: 0x018 (R/W) Folded-instruction Count Register. More...
 
__I uint32_t PCSR
 Offset: 0x01C (R/ ) Program Counter Sample Register. More...
 
__IO uint32_t COMP0
 Offset: 0x020 (R/W) Comparator Register 0. More...
 
__IO uint32_t MASK0
 Offset: 0x024 (R/W) Mask Register 0. More...
 
__IO uint32_t FUNCTION0
 Offset: 0x028 (R/W) Function Register 0. More...
 
uint32_t RESERVED0 [1]
 Reserved. More...
 
__IO uint32_t COMP1
 Offset: 0x030 (R/W) Comparator Register 1. More...
 
__IO uint32_t MASK1
 Offset: 0x034 (R/W) Mask Register 1. More...
 
__IO uint32_t FUNCTION1
 Offset: 0x038 (R/W) Function Register 1. More...
 
uint32_t RESERVED1 [1]
 Reserved. More...
 
__IO uint32_t COMP2
 Offset: 0x040 (R/W) Comparator Register 2. More...
 
__IO uint32_t MASK2
 Offset: 0x044 (R/W) Mask Register 2. More...
 
__IO uint32_t FUNCTION2
 Offset: 0x048 (R/W) Function Register 2. More...
 
uint32_t RESERVED2 [1]
 Reserved. More...
 
__IO uint32_t COMP3
 Offset: 0x050 (R/W) Comparator Register 3. More...
 
__IO uint32_t MASK3
 Offset: 0x054 (R/W) Mask Register 3. More...
 
__IO uint32_t FUNCTION3
 Offset: 0x058 (R/W) Function Register 3. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP0
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP1
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP2
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP3
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::CPICNT
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::CTRL
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::CYCCNT
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::EXCCNT
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FOLDCNT
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION0
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION1
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION2
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION3
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::LSUCNT
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK0
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK1
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK2
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK3
+
+ +
+
+ +
+
+ + + + +
__I uint32_t DWT_Type::PCSR
+
+ +
+
+ +
+
+ + + + +
uint32_t DWT_Type::RESERVED0[1]
+
+ +
+
+ +
+
+ + + + +
uint32_t DWT_Type::RESERVED1[1]
+
+ +
+
+ +
+
+ + + + +
uint32_t DWT_Type::RESERVED2[1]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::SLEEPCNT
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.js new file mode 100644 index 000000000..d5847ecc7 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.js @@ -0,0 +1,26 @@ +var struct_d_w_t___type = +[ + [ "COMP0", "struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904", null ], + [ "COMP1", "struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c", null ], + [ "COMP2", "struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332", null ], + [ "COMP3", "struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f", null ], + [ "CPICNT", "struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc", null ], + [ "CTRL", "struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d", null ], + [ "CYCCNT", "struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4", null ], + [ "EXCCNT", "struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82", null ], + [ "FOLDCNT", "struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab", null ], + [ "FUNCTION0", "struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729", null ], + [ "FUNCTION1", "struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747", null ], + [ "FUNCTION2", "struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b", null ], + [ "FUNCTION3", "struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890", null ], + [ "LSUCNT", "struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35", null ], + [ "MASK0", "struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f", null ], + [ "MASK1", "struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef", null ], + [ "MASK2", "struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e", null ], + [ "MASK3", "struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba", null ], + [ "PCSR", "struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5", null ], + [ "RESERVED0", "struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59", null ], + [ "RESERVED1", "struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4", null ], + [ "RESERVED2", "struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738", null ], + [ "SLEEPCNT", "struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html new file mode 100644 index 000000000..343fa46b6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html @@ -0,0 +1,234 @@ + + + + + +CMSIS-CORE: FPU_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
FPU_Type Struct Reference
+
+
+ +

Structure type to access the Floating Point Unit (FPU). +

+ + + + + + + + + + + + + + + + + + + + +

+Data Fields

uint32_t RESERVED0 [1]
 Reserved. More...
 
__IO uint32_t FPCCR
 Offset: 0x004 (R/W) Floating-Point Context Control Register. More...
 
__IO uint32_t FPCAR
 Offset: 0x008 (R/W) Floating-Point Context Address Register. More...
 
__IO uint32_t FPDSCR
 Offset: 0x00C (R/W) Floating-Point Default Status Control Register. More...
 
__I uint32_t MVFR0
 Offset: 0x010 (R/ ) Media and FP Feature Register 0. More...
 
__I uint32_t MVFR1
 Offset: 0x014 (R/ ) Media and FP Feature Register 1. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IO uint32_t FPU_Type::FPCAR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t FPU_Type::FPCCR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t FPU_Type::FPDSCR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t FPU_Type::MVFR0
+
+ +
+
+ +
+
+ + + + +
__I uint32_t FPU_Type::MVFR1
+
+ +
+
+ +
+
+ + + + +
uint32_t FPU_Type::RESERVED0[1]
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.js new file mode 100644 index 000000000..054e14996 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.js @@ -0,0 +1,9 @@ +var struct_f_p_u___type = +[ + [ "FPCAR", "struct_f_p_u___type.html#aa48253f088dc524de80c42fbc995f66b", null ], + [ "FPCCR", "struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8", null ], + [ "FPDSCR", "struct_f_p_u___type.html#a4d58ef3ebea69a5ec5acd8c90a9941b6", null ], + [ "MVFR0", "struct_f_p_u___type.html#a135577b0a76bd3164be2a02f29ca46f1", null ], + [ "MVFR1", "struct_f_p_u___type.html#a776e8625853e1413c4e8330ec85c256d", null ], + [ "RESERVED0", "struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.html new file mode 100644 index 000000000..58ec0a93f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.html @@ -0,0 +1,295 @@ + + + + + +CMSIS-CORE: ITM_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
ITM_Type Struct Reference
+
+
+ +

Structure type to access the Instrumentation Trace Macrocell Register (ITM). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

union {
   __O uint8_t   u8
 Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
 
   __O uint16_t   u16
 Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
 
   __O uint32_t   u32
 Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
 
} PORT [32]
 Offset: 0x000 ( /W) ITM Stimulus Port Registers. More...
 
uint32_t RESERVED0 [864]
 Reserved. More...
 
__IO uint32_t TER
 Offset: 0xE00 (R/W) ITM Trace Enable Register. More...
 
uint32_t RESERVED1 [15]
 Reserved. More...
 
__IO uint32_t TPR
 Offset: 0xE40 (R/W) ITM Trace Privilege Register. More...
 
uint32_t RESERVED2 [15]
 Reserved. More...
 
__IO uint32_t TCR
 Offset: 0xE80 (R/W) ITM Trace Control Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__O { ... } ITM_Type::PORT[32]
+
+ +
+
+ +
+
+ + + + +
uint32_t ITM_Type::RESERVED0[864]
+
+ +
+
+ +
+
+ + + + +
uint32_t ITM_Type::RESERVED1[15]
+
+ +
+
+ +
+
+ + + + +
uint32_t ITM_Type::RESERVED2[15]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t ITM_Type::TCR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t ITM_Type::TER
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t ITM_Type::TPR
+
+ +
+
+ +
+
+ + + + +
__O uint16_t ITM_Type::u16
+
+ +
+
+ +
+
+ + + + +
__O uint32_t ITM_Type::u32
+
+ +
+
+ +
+
+ + + + +
__O uint8_t ITM_Type::u8
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.js new file mode 100644 index 000000000..f99521672 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.js @@ -0,0 +1,13 @@ +var struct_i_t_m___type = +[ + [ "PORT", "struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46", null ], + [ "RESERVED0", "struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e", null ], + [ "RESERVED1", "struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce", null ], + [ "RESERVED2", "struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b", null ], + [ "TCR", "struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45", null ], + [ "TER", "struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589", null ], + [ "TPR", "struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa", null ], + [ "u16", "struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4", null ], + [ "u32", "struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df", null ], + [ "u8", "struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html new file mode 100644 index 000000000..5c4873753 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html @@ -0,0 +1,309 @@ + + + + + +CMSIS-CORE: MPU_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
MPU_Type Struct Reference
+
+
+ +

Structure type to access the Memory Protection Unit (MPU). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

__I uint32_t TYPE
 Offset: 0x000 (R/ ) MPU Type Register. More...
 
__IO uint32_t CTRL
 Offset: 0x004 (R/W) MPU Control Register. More...
 
__IO uint32_t RNR
 Offset: 0x008 (R/W) MPU Region RNRber Register. More...
 
__IO uint32_t RBAR
 Offset: 0x00C (R/W) MPU Region Base Address Register. More...
 
__IO uint32_t RASR
 Offset: 0x010 (R/W) MPU Region Attribute and Size Register. More...
 
__IO uint32_t RBAR_A1
 Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. More...
 
__IO uint32_t RASR_A1
 Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. More...
 
__IO uint32_t RBAR_A2
 Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. More...
 
__IO uint32_t RASR_A2
 Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. More...
 
__IO uint32_t RBAR_A3
 Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. More...
 
__IO uint32_t RASR_A3
 Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IO uint32_t MPU_Type::CTRL
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RASR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RASR_A1
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RASR_A2
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RASR_A3
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RBAR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RBAR_A1
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RBAR_A2
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RBAR_A3
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t MPU_Type::RNR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t MPU_Type::TYPE
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.js new file mode 100644 index 000000000..e72c3486d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.js @@ -0,0 +1,14 @@ +var struct_m_p_u___type = +[ + [ "CTRL", "struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328", null ], + [ "RASR", "struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03", null ], + [ "RASR_A1", "struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185", null ], + [ "RASR_A2", "struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014", null ], + [ "RASR_A3", "struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d", null ], + [ "RBAR", "struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9", null ], + [ "RBAR_A1", "struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639", null ], + [ "RBAR_A2", "struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395", null ], + [ "RBAR_A3", "struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804", null ], + [ "RNR", "struct_m_p_u___type.html#afd8de96a5d574c3953e2106e782f9833", null ], + [ "TYPE", "struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html new file mode 100644 index 000000000..8828345e6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html @@ -0,0 +1,339 @@ + + + + + +CMSIS-CORE: NVIC_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
NVIC_Type Struct Reference
+
+
+ +

Structure type to access the Nested Vectored Interrupt Controller (NVIC). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

__IO uint32_t ISER [8]
 Offset: 0x000 (R/W) Interrupt Set Enable Register. More...
 
uint32_t RESERVED0 [24]
 Reserved. More...
 
__IO uint32_t ICER [8]
 Offset: 0x080 (R/W) Interrupt Clear Enable Register. More...
 
uint32_t RSERVED1 [24]
 Reserved. More...
 
__IO uint32_t ISPR [8]
 Offset: 0x100 (R/W) Interrupt Set Pending Register. More...
 
uint32_t RESERVED2 [24]
 Reserved. More...
 
__IO uint32_t ICPR [8]
 Offset: 0x180 (R/W) Interrupt Clear Pending Register. More...
 
uint32_t RESERVED3 [24]
 Reserved. More...
 
__IO uint32_t IABR [8]
 Offset: 0x200 (R/W) Interrupt Active bit Register. More...
 
uint32_t RESERVED4 [56]
 Reserved. More...
 
__IO uint8_t IP [240]
 Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) More...
 
uint32_t RESERVED5 [644]
 Reserved. More...
 
__O uint32_t STIR
 Offset: 0xE00 ( /W) Software Trigger Interrupt Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IO uint32_t NVIC_Type::IABR[8]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ICER[8]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ICPR[8]
+
+ +
+
+ +
+
+ + + + +
__IO uint8_t NVIC_Type::IP[240]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ISER[8]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ISPR[8]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED0[24]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED2[24]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED3[24]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED4[56]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED5[644]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RSERVED1[24]
+
+ +
+
+ +
+
+ + + + +
__O uint32_t NVIC_Type::STIR
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.js new file mode 100644 index 000000000..2f8795040 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.js @@ -0,0 +1,16 @@ +var struct_n_v_i_c___type = +[ + [ "IABR", "struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11", null ], + [ "ICER", "struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5", null ], + [ "ICPR", "struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5", null ], + [ "IP", "struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c", null ], + [ "ISER", "struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f", null ], + [ "ISPR", "struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90", null ], + [ "RESERVED0", "struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80", null ], + [ "RESERVED2", "struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72", null ], + [ "RESERVED3", "struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab", null ], + [ "RESERVED4", "struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790", null ], + [ "RESERVED5", "struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8", null ], + [ "RSERVED1", "struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe", null ], + [ "STIR", "struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html new file mode 100644 index 000000000..416b7a687 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html @@ -0,0 +1,459 @@ + + + + + +CMSIS-CORE: SCB_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
SCB_Type Struct Reference
+
+
+ +

Structure type to access the System Control Block (SCB). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

__I uint32_t CPUID
 Offset: 0x000 (R/ ) CPUID Base Register. More...
 
__IO uint32_t ICSR
 Offset: 0x004 (R/W) Interrupt Control and State Register. More...
 
__IO uint32_t VTOR
 Offset: 0x008 (R/W) Vector Table Offset Register. More...
 
__IO uint32_t AIRCR
 Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. More...
 
__IO uint32_t SCR
 Offset: 0x010 (R/W) System Control Register. More...
 
__IO uint32_t CCR
 Offset: 0x014 (R/W) Configuration Control Register. More...
 
__IO uint8_t SHP [12]
 Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) More...
 
__IO uint32_t SHCSR
 Offset: 0x024 (R/W) System Handler Control and State Register. More...
 
__IO uint32_t CFSR
 Offset: 0x028 (R/W) Configurable Fault Status Register. More...
 
__IO uint32_t HFSR
 Offset: 0x02C (R/W) HardFault Status Register. More...
 
__IO uint32_t DFSR
 Offset: 0x030 (R/W) Debug Fault Status Register. More...
 
__IO uint32_t MMFAR
 Offset: 0x034 (R/W) MemManage Fault Address Register. More...
 
__IO uint32_t BFAR
 Offset: 0x038 (R/W) BusFault Address Register. More...
 
__IO uint32_t AFSR
 Offset: 0x03C (R/W) Auxiliary Fault Status Register. More...
 
__I uint32_t PFR [2]
 Offset: 0x040 (R/ ) Processor Feature Register. More...
 
__I uint32_t DFR
 Offset: 0x048 (R/ ) Debug Feature Register. More...
 
__I uint32_t ADR
 Offset: 0x04C (R/ ) Auxiliary Feature Register. More...
 
__I uint32_t MMFR [4]
 Offset: 0x050 (R/ ) Memory Model Feature Register. More...
 
__I uint32_t ISAR [5]
 Offset: 0x060 (R/ ) Instruction Set Attributes Register. More...
 
uint32_t RESERVED0 [5]
 Reserved. More...
 
__IO uint32_t CPACR
 Offset: 0x088 (R/W) Coprocessor Access Control Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__I uint32_t SCB_Type::ADR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::AFSR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::AIRCR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::BFAR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::CCR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::CFSR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::CPACR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::CPUID
+
+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::DFR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::DFSR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::HFSR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::ICSR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::ISAR[5]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::MMFAR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::MMFR[4]
+
+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::PFR[2]
+
+ +
+
+ +
+
+ + + + +
uint32_t SCB_Type::RESERVED0[5]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::SCR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::SHCSR
+
+ +
+
+ +
+
+ + + + +
__IO uint8_t SCB_Type::SHP[12]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::VTOR
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.js new file mode 100644 index 000000000..2a75744d2 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.js @@ -0,0 +1,24 @@ +var struct_s_c_b___type = +[ + [ "ADR", "struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2", null ], + [ "AFSR", "struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef", null ], + [ "AIRCR", "struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d", null ], + [ "BFAR", "struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a", null ], + [ "CCR", "struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8", null ], + [ "CFSR", "struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4", null ], + [ "CPACR", "struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85", null ], + [ "CPUID", "struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032", null ], + [ "DFR", "struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86", null ], + [ "DFSR", "struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d", null ], + [ "HFSR", "struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d", null ], + [ "ICSR", "struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a", null ], + [ "ISAR", "struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f", null ], + [ "MMFAR", "struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd", null ], + [ "MMFR", "struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976", null ], + [ "PFR", "struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7", null ], + [ "RESERVED0", "struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6", null ], + [ "SCR", "struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16", null ], + [ "SHCSR", "struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f", null ], + [ "SHP", "struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4", null ], + [ "VTOR", "struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html new file mode 100644 index 000000000..9b13e736a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html @@ -0,0 +1,189 @@ + + + + + +CMSIS-CORE: SCnSCB_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
SCnSCB_Type Struct Reference
+
+
+ +

Structure type to access the System Control and ID Register not in the SCB. +

+ + + + + + + + + + + +

+Data Fields

uint32_t RESERVED0 [1]
 Reserved. More...
 
__I uint32_t ICTR
 Offset: 0x004 (R/ ) Interrupt Controller Type Register. More...
 
__IO uint32_t ACTLR
 Offset: 0x008 (R/W) Auxiliary Control Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IO uint32_t SCnSCB_Type::ACTLR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t SCnSCB_Type::ICTR
+
+ +
+
+ +
+
+ + + + +
uint32_t SCnSCB_Type::RESERVED0[1]
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.js new file mode 100644 index 000000000..048acfb05 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.js @@ -0,0 +1,6 @@ +var struct_s_cn_s_c_b___type = +[ + [ "ACTLR", "struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d", null ], + [ "ICTR", "struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98", null ], + [ "RESERVED0", "struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html new file mode 100644 index 000000000..da2077522 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html @@ -0,0 +1,204 @@ + + + + + +CMSIS-CORE: SysTick_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
SysTick_Type Struct Reference
+
+
+ +

Structure type to access the System Timer (SysTick). +

+ + + + + + + + + + + + + + +

+Data Fields

__IO uint32_t CTRL
 Offset: 0x000 (R/W) SysTick Control and Status Register. More...
 
__IO uint32_t LOAD
 Offset: 0x004 (R/W) SysTick Reload Value Register. More...
 
__IO uint32_t VAL
 Offset: 0x008 (R/W) SysTick Current Value Register. More...
 
__I uint32_t CALIB
 Offset: 0x00C (R/ ) SysTick Calibration Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__I uint32_t SysTick_Type::CALIB
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SysTick_Type::CTRL
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SysTick_Type::LOAD
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t SysTick_Type::VAL
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.js new file mode 100644 index 000000000..32d007b51 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.js @@ -0,0 +1,7 @@ +var struct_sys_tick___type = +[ + [ "CALIB", "struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238", null ], + [ "CTRL", "struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f", null ], + [ "LOAD", "struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f", null ], + [ "VAL", "struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html new file mode 100644 index 000000000..1ade31312 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html @@ -0,0 +1,504 @@ + + + + + +CMSIS-CORE: TPI_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
TPI_Type Struct Reference
+
+
+ +

Structure type to access the Trace Port Interface Register (TPI). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

__IO uint32_t SSPSR
 Offset: 0x000 (R/ ) Supported Parallel Port Size Register. More...
 
__IO uint32_t CSPSR
 Offset: 0x004 (R/W) Current Parallel Port Size Register. More...
 
uint32_t RESERVED0 [2]
 Reserved. More...
 
__IO uint32_t ACPR
 Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register. More...
 
uint32_t RESERVED1 [55]
 Reserved. More...
 
__IO uint32_t SPPR
 Offset: 0x0F0 (R/W) Selected Pin Protocol Register. More...
 
uint32_t RESERVED2 [131]
 Reserved. More...
 
__I uint32_t FFSR
 Offset: 0x300 (R/ ) Formatter and Flush Status Register. More...
 
__IO uint32_t FFCR
 Offset: 0x304 (R/W) Formatter and Flush Control Register. More...
 
__I uint32_t FSCR
 Offset: 0x308 (R/ ) Formatter Synchronization Counter Register. More...
 
uint32_t RESERVED3 [759]
 Reserved. More...
 
__I uint32_t TRIGGER
 Offset: 0xEE8 (R/ ) TRIGGER. More...
 
__I uint32_t FIFO0
 Offset: 0xEEC (R/ ) Integration ETM Data. More...
 
__I uint32_t ITATBCTR2
 Offset: 0xEF0 (R/ ) ITATBCTR2. More...
 
uint32_t RESERVED4 [1]
 Reserved. More...
 
__I uint32_t ITATBCTR0
 Offset: 0xEF8 (R/ ) ITATBCTR0. More...
 
__I uint32_t FIFO1
 Offset: 0xEFC (R/ ) Integration ITM Data. More...
 
__IO uint32_t ITCTRL
 Offset: 0xF00 (R/W) Integration Mode Control. More...
 
uint32_t RESERVED5 [39]
 Reserved. More...
 
__IO uint32_t CLAIMSET
 Offset: 0xFA0 (R/W) Claim tag set. More...
 
__IO uint32_t CLAIMCLR
 Offset: 0xFA4 (R/W) Claim tag clear. More...
 
uint32_t RESERVED7 [8]
 Reserved. More...
 
__I uint32_t DEVID
 Offset: 0xFC8 (R/ ) TPIU_DEVID. More...
 
__I uint32_t DEVTYPE
 Offset: 0xFCC (R/ ) TPIU_DEVTYPE. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IO uint32_t TPI_Type::ACPR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::CLAIMCLR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::CLAIMSET
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::CSPSR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::DEVID
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::DEVTYPE
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::FFCR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FFSR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FIFO0
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FIFO1
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FSCR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::ITATBCTR0
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::ITATBCTR2
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::ITCTRL
+
+ +
+
+ +
+
+ + + + +
uint32_t TPI_Type::RESERVED0[2]
+
+ +
+
+ +
+
+ + + + +
uint32_t TPI_Type::RESERVED1[55]
+
+ +
+
+ +
+
+ + + + +
uint32_t TPI_Type::RESERVED2[131]
+
+ +
+
+ +
+
+ + + + +
uint32_t TPI_Type::RESERVED3[759]
+
+ +
+
+ +
+
+ + + + +
uint32_t TPI_Type::RESERVED4[1]
+
+ +
+
+ +
+
+ + + + +
uint32_t TPI_Type::RESERVED5[39]
+
+ +
+
+ +
+
+ + + + +
uint32_t TPI_Type::RESERVED7[8]
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::SPPR
+
+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::SSPSR
+
+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::TRIGGER
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.js new file mode 100644 index 000000000..68f56d623 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.js @@ -0,0 +1,27 @@ +var struct_t_p_i___type = +[ + [ "ACPR", "struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab", null ], + [ "CLAIMCLR", "struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad", null ], + [ "CLAIMSET", "struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84", null ], + [ "CSPSR", "struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a", null ], + [ "DEVID", "struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d", null ], + [ "DEVTYPE", "struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35", null ], + [ "FFCR", "struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880", null ], + [ "FFSR", "struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd", null ], + [ "FIFO0", "struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10", null ], + [ "FIFO1", "struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e", null ], + [ "FSCR", "struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef", null ], + [ "ITATBCTR0", "struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0", null ], + [ "ITATBCTR2", "struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d", null ], + [ "ITCTRL", "struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198", null ], + [ "RESERVED0", "struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9", null ], + [ "RESERVED1", "struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12", null ], + [ "RESERVED2", "struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096", null ], + [ "RESERVED3", "struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c", null ], + [ "RESERVED4", "struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46", null ], + [ "RESERVED5", "struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30", null ], + [ "RESERVED7", "struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550", null ], + [ "SPPR", "struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e", null ], + [ "SSPSR", "struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912", null ], + [ "TRIGGER", "struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/sync_off.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/sync_off.png new file mode 100644 index 000000000..e8e314d6c Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/sync_off.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/sync_on.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/sync_on.png new file mode 100644 index 000000000..f80906a72 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/sync_on.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/system_c_pg.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/system_c_pg.html new file mode 100644 index 000000000..f398d0c02 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/system_c_pg.html @@ -0,0 +1,309 @@ + + + + + +CMSIS-CORE: System Configuration Files system_<device>.c and system_<device>.h + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
System Configuration Files system_<device>.c and system_<device>.h
+
+
+

The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System and Clock Configuration. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.

+

For devices with external memory BUS the system_<device>.c also configures the BUS system.

+

The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.

+

+system_Device.c Template File

+

The system_Device.c Template File for the Cortex-M3 is shown below.

+
/**************************************************************************//**
+ * @file     system_<Device>.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#include <stdint.h>
+#include "<Device>.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization
+         following is an example for different system frequencies             */
+#define __HSI             ( 6000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit()    */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings.                                */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+         do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+

+system_Device.h Template File

+

The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The system_Device.h Template File is shown below.

+
/**************************************************************************//**
+ * @file     system_<Device>.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_<Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_<Device>_H */
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_a.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_a.png new file mode 100644 index 000000000..fffadc1ab Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_a.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_b.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_b.png new file mode 100644 index 000000000..b7ce1af92 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_b.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_h.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_h.png new file mode 100644 index 000000000..5e9188f3e Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_h.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_s.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_s.png new file mode 100644 index 000000000..956e1c2f5 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_s.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_topnav.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_topnav.png new file mode 100644 index 000000000..b257b7780 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tab_topnav.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tabs.css b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tabs.css new file mode 100644 index 000000000..ffbab509d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/tabs.css @@ -0,0 +1,71 @@ +.tabs, .tabs1, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 10px; +} + +.tabs1 { + background-image: url('tab_topnav.png'); + font-size: 12px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; + line-height: 24px; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + list-style: none; +} + +.tabs1 .tablist li { + float: left; + display: table-cell; + background-image: url('tab_topnav.png'); + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html new file mode 100644 index 000000000..cda017405 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html @@ -0,0 +1,265 @@ + + + + + +CMSIS-CORE: APSR_Type Union Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
APSR_Type Union Reference
+
+
+ +

Union type to access the Application Program Status Register (APSR). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   _reserved0:27
 bit: 0..26 Reserved More...
 
   uint32_t   Q:1
 bit: 27 Saturation condition flag More...
 
   uint32_t   V:1
 bit: 28 Overflow condition code flag More...
 
   uint32_t   C:1
 bit: 29 Carry condition code flag More...
 
   uint32_t   Z:1
 bit: 30 Zero condition code flag More...
 
   uint32_t   N:1
 bit: 31 Negative condition code flag More...
 
} b
 Structure used for bit access. More...
 
uint32_t w
 Type used for word access. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t APSR_Type::_reserved0
+
+ +
+
+ +
+
+ + + + +
struct { ... } APSR_Type::b
+
+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::C
+
+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::N
+
+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::Q
+
+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::V
+
+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::w
+
+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::Z
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.js new file mode 100644 index 000000000..cbea61bf5 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.js @@ -0,0 +1,11 @@ +var union_a_p_s_r___type = +[ + [ "_reserved0", "union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728", null ], + [ "b", "union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14", null ], + [ "C", "union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6", null ], + [ "N", "union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0", null ], + [ "Q", "union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de", null ], + [ "V", "union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e", null ], + [ "w", "union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94", null ], + [ "Z", "union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html new file mode 100644 index 000000000..c188f7dda --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html @@ -0,0 +1,235 @@ + + + + + +CMSIS-CORE: CONTROL_Type Union Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
CONTROL_Type Union Reference
+
+
+ +

Union type to access the Control Registers (CONTROL). +

+ + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   nPRIV:1
 bit: 0 Execution privilege in Thread mode More...
 
   uint32_t   SPSEL:1
 bit: 1 Stack to be used More...
 
   uint32_t   FPCA:1
 bit: 2 FP extension active flag More...
 
   uint32_t   _reserved0:29
 bit: 3..31 Reserved More...
 
} b
 Structure used for bit access. More...
 
uint32_t w
 Type used for word access. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t CONTROL_Type::_reserved0
+
+ +
+
+ +
+
+ + + + +
struct { ... } CONTROL_Type::b
+
+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::FPCA
+
+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::nPRIV
+
+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::SPSEL
+
+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::w
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.js new file mode 100644 index 000000000..eb2c173f3 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.js @@ -0,0 +1,9 @@ +var union_c_o_n_t_r_o_l___type = +[ + [ "_reserved0", "union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50", null ], + [ "b", "union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9", null ], + [ "FPCA", "union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd", null ], + [ "nPRIV", "union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605", null ], + [ "SPSEL", "union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2", null ], + [ "w", "union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html new file mode 100644 index 000000000..aa1c80494 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html @@ -0,0 +1,205 @@ + + + + + +CMSIS-CORE: IPSR_Type Union Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
IPSR_Type Union Reference
+
+
+ +

Union type to access the Interrupt Program Status Register (IPSR). +

+ + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   ISR:9
 bit: 0.. 8 Exception number More...
 
   uint32_t   _reserved0:23
 bit: 9..31 Reserved More...
 
} b
 Structure used for bit access. More...
 
uint32_t w
 Type used for word access. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t IPSR_Type::_reserved0
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+ +
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+ +
+
+ + + + +
struct { ... } IPSR_Type::b
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+ +
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+ +
+
+ + + + +
uint32_t IPSR_Type::ISR
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+ +
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+ +
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+ + + + +
uint32_t IPSR_Type::w
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+ +
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+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.js new file mode 100644 index 000000000..ca9eac6b5 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.js @@ -0,0 +1,7 @@ +var union_i_p_s_r___type = +[ + [ "_reserved0", "union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa", null ], + [ "b", "union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50", null ], + [ "ISR", "union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5", null ], + [ "w", "union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html new file mode 100644 index 000000000..18d7e43c4 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html @@ -0,0 +1,310 @@ + + + + + +CMSIS-CORE: xPSR_Type Union Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 3.20 +
+
CMSIS-CORE support for Cortex-M processor-based devices
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+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
xPSR_Type Union Reference
+
+
+ +

Union type to access the Special-Purpose Program Status Registers (xPSR). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   ISR:9
 bit: 0.. 8 Exception number More...
 
   uint32_t   _reserved0:15
 bit: 9..23 Reserved More...
 
   uint32_t   T:1
 bit: 24 Thumb bit (read 0) More...
 
   uint32_t   IT:2
 bit: 25..26 saved IT state (read 0) More...
 
   uint32_t   Q:1
 bit: 27 Saturation condition flag More...
 
   uint32_t   V:1
 bit: 28 Overflow condition code flag More...
 
   uint32_t   C:1
 bit: 29 Carry condition code flag More...
 
   uint32_t   Z:1
 bit: 30 Zero condition code flag More...
 
   uint32_t   N:1
 bit: 31 Negative condition code flag More...
 
} b
 Structure used for bit access. More...
 
uint32_t w
 Type used for word access. More...
 
+

Field Documentation

+ +
+
+ + + + +
uint32_t xPSR_Type::_reserved0
+
+ +
+
+ +
+
+ + + + +
struct { ... } xPSR_Type::b
+
+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::C
+
+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::ISR
+
+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::IT
+
+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::N
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+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::Q
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+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::T
+
+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::V
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+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::w
+
+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::Z
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.js new file mode 100644 index 000000000..b02f482be --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.js @@ -0,0 +1,14 @@ +var unionx_p_s_r___type = +[ + [ "_reserved0", "unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5", null ], + [ "b", "unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70", null ], + [ "C", "unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d", null ], + [ "ISR", "unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970", null ], + [ "IT", "unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328", null ], + [ "N", "unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5", null ], + [ "Q", "unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c", null ], + [ "T", "unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658", null ], + [ "V", "unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a", null ], + [ "w", "unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2", null ], + [ "Z", "unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/CMSIS_Logo_Final.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/CMSIS_Logo_Final.png new file mode 100644 index 000000000..2056b7e74 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/CMSIS_Logo_Final.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/CMSIS_V3_small.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/CMSIS_V3_small.png new file mode 100644 index 000000000..34aa5d9cb Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/CMSIS_V3_small.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/bc_s.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/bc_s.png new file mode 100644 index 000000000..224b29aa9 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/bc_s.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/bdwn.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/bdwn.png new file mode 100644 index 000000000..940a0b950 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/bdwn.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/closed.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/closed.png new file mode 100644 index 000000000..98cc2c909 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/closed.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/cmsis.css b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/cmsis.css new file mode 100644 index 000000000..a9ec718c0 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/cmsis.css @@ -0,0 +1,1256 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 13px; + line-height: 1.3; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + border: 1px solid #2D4068; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + height: 28px; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + + + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; +} + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; 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+ display:inline; + } +} + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/doxygen.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/doxygen.png new file mode 100644 index 000000000..3ff17d807 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/doxygen.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/dynsections.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/dynsections.js new file mode 100644 index 000000000..ed092c7f6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/General/html/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + +CMSIS: Introduction + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS +  Version 3.20 +
+
Cortex Microcontroller Software Interface Standard
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Introduction
+
+
+

The Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for microcontroller developers, and reducing the time to market for new devices.

+

The CMSIS is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components. The CMSIS is intended to enable the combination of software components from multiple middleware vendors.

+

The CMSIS components are:

+
    +
  • CMSIS-CORE: API for the Cortex-M processor core and peripherals. It provides at standardized interface for Cortex-M0, Cortex-M3, Cortex-M4, SC000, and SC300. Included are also SIMD intrinsic functions for Cortex-M4 SIMD instructions.
    • +
+
    +
  • CMSIS-DSP: DSP Library Collection with over 60 Functions for various data types: fix-point (fractional q7, q15, q31) and single precision floating-point (32-bit). The library is available for Cortex-M0, Cortex-M3, and Cortex-M4. The Cortex-M4 implementation is optimized for the SIMD instruction set.
    • +
+
    +
  • CMSIS-RTOS API: Common API for Real-Time operating systems. It provides a standardized programming interface that is portable to many RTOS and enables therefore software templates, middleware, libraries, and other components that can work acrosss supported the RTOS systems.
    • +
+
    +
  • CMSIS-SVD: System View Description for Peripherals. Describes the peripherals of a device in an XML file and can be used to create peripheral awareness in debuggers or header files with peripheral register and interrupt definitions.
    • +
+
    +
  • CMSIS-DAP: Debug Access Port. Standardized firmware for a Debug Unit that connects to the CoreSight Debug Access Port. CMSIS-DAP is distributed as separate package and well suited for integration on evaluation boards.
    • +
+
+CMSIS_V3_small.png +
+CMSIS Structure
+

+Motivation

+

CMSIS has been created to help the industry in standardization. It is not a huge software layer that introduces overhead and does not define standard peripherals. The silicon industry can therefore support the wide variations of Cortex-M processor-based devices with this common standard. In detail the benefits of the CMSIS are:

+
    +
  • Consistent software interfaces improve the software portability and re-usability. Generic software libraries can interface with device libraries from various silicon vendors.
    • +
  • Reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through an easy to use and standardized software interface.
    • +
  • Provides a compiler independent layer that allows using different compilers. CMSIS is supported by all mainstream compilers (ARMCC, IAR, and GNU).
    • +
  • Enhances program debugging with peripheral information for debuggers and ITM channels for printf-style output and RTOS kernel awareness.
    • +
+

+Coding Rules

+

The CMSIS uses the following essential coding rules and conventions:

+
    +
  • Compliant with ANSI C and C++.
    • +
  • Uses ANSI C standard data types defined in <stdint.h>.
    • +
  • Variables and parameters have a complete data type.
    • +
  • Expressions for #define constants are enclosed in parenthesis.
    • +
  • Conforms to MISRA 2004. MIRSA rule violations are documented.
    • +
+

In addition, the CMSIS recommends the following conventions for identifiers:

+
    +
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • +
  • CamelCase names to identify function names and interrupt functions.
    • +
  • Namespace_ prefixes avoid clashes with user identifiers and provide functional groups (i.e. for peripherals, RTOS, or DSP Library).
    • +
+

The CMSIS is documented within the source files with:

+
    +
  • Comments that use the C or C++ style.
    • +
  • Doxygen compliant function comments that provide:
      +
    • brief function overview.
      • +
    • detailed description of the function.
      • +
    • detailed parameter explanation.
      • +
    • detailed information about return values.
      • +
    +
    • +
+

Doxygen comment example:

+
/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
+

+Licence

+

The CMSIS is provided free of charge by ARM and can be used for all Cortex-M based devices.

+

The software portions that are deployed in the application program are under a BSD license which allows usage of CMSIS in any commercial or open source projects.

+

View the LICENCE AGREEMENT for CMSIS in detail.

+
+
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b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+".preventClickEvent",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery); +/* + * jQuery UI Resizable 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * jquery.ui.core.js + * jquery.ui.mouse.js + * jquery.ui.widget.js + */ +(function(a,b){a.widget("ui.resizable",a.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:!1,animate:!1,animateDuration:"slow",animateEasing:"swing",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:"e,s,se",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass("ui-resizable"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||"ui-resizable-helper":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")})),this.element=this.element.parent().data("resizable",this.element.data("resizable")),this.elementIsWrapper=!0,this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")}),this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0}),this.originalResizeStyle=this.originalElement.css("resize"),this.originalElement.css("resize","none"),this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"})),this.originalElement.css({margin:this.originalElement.css("margin")}),this._proportionallyResize()),this.handles=c.handles||(a(".ui-resizable-handle",this.element).length?{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"}:"e,s,se");if(this.handles.constructor==String){this.handles=="all"&&(this.handles="n,e,s,w,se,sw,ne,nw");var d=this.handles.split(",");this.handles={};for(var e=0;e
');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),"se"==f&&h.addClass("ui-icon ui-icon-gripsmall-diagonal-se"),this.handles[f]=".ui-resizable-"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=["padding",/ne|nw|n/.test(c)?"Top":/se|sw|s/.test(c)?"Bottom":/^e$/.test(c)?"Right":"Left"].join("");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(".ui-resizable-handle",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:"se"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass("ui-resizable-autohide").hover(function(){c.disabled||(a(this).removeClass("ui-resizable-autohide"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass("ui-resizable-autohide"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css("position"),width:c.outerWidth(),height:c.outerHeight(),top:c.css("top"),left:c.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(".ui-draggable")||/absolute/.test(f.css("position")))&&f.css({position:"absolute",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css("left")),h=c(this.helper.css("top"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio=="number"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(".ui-resizable-"+this.axis).css("cursor");a("body").css("cursor",i=="auto"?this.axis+"-resize":i),f.addClass("ui-resizable-resizing"),this._propagate("start",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate("resize",b),c.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger("resize",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],"left")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css("left"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css("top"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a("body").css("cursor","auto"),this.element.removeClass("ui-resizable-resizing"),this._propagate("stop",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:"absolute",left:this.elementOffset.left-e+"px",top:this.elementOffset.top-e+"px",zIndex:++c.zIndex}),this.helper.appendTo("body").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!="resize"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:"1.8.18"}),a.ui.plugin.add("resizable","alsoResize",{start:function(b,c){var d=a(this).data("resizable"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data("resizable-alsoresize",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css("left"),10),top:parseInt(b.css("top"),10)})})};typeof e.alsoResize=="object"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data("resizable-alsoresize"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?["width","height"]:["width","height","top","left"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof e.alsoResize=="object"&&!e.alsoResize.nodeType?a.each(e.alsoResize,function(a,b){i(a,b)}):i(e.alsoResize)},stop:function(b,c){a(this).removeData("resizable-alsoresize")}}),a.ui.plugin.add("resizable","animate",{stop:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d._proportionallyResizeElements,g=f.length&&/textarea/i.test(f[0].nodeName),h=g&&a.ui.hasScroll(f[0],"left")?0:d.sizeDiff.height,i=g?0:d.sizeDiff.width,j={width:d.size.width-i,height:d.size.height-h},k=parseInt(d.element.css("left"),10)+(d.position.left-d.originalPosition.left)||null,l=parseInt(d.element.css("top"),10)+(d.position.top-d.originalPosition.top)||null;d.element.animate(a.extend(j,l&&k?{top:l,left:k}:{}),{duration:e.animateDuration,easing:e.animateEasing,step:function(){var c={width:parseInt(d.element.css("width"),10),height:parseInt(d.element.css("height"),10),top:parseInt(d.element.css("top"),10),left:parseInt(d.element.css("left"),10)};f&&f.length&&a(f[0]).css({width:c.width,height:c.height}),d._updateCache(c),d._propagate("resize",b)}})}}),a.ui.plugin.add("resizable","containment",{start:function(b,d){var e=a(this).data("resizable"),f=e.options,g=e.element,h=f.containment,i=h instanceof a?h.get(0):/parent/.test(h)?g.parent().get(0):h;if(!!i){e.containerElement=a(i);if(/document/.test(h)||h==document)e.containerOffset={left:0,top:0},e.containerPosition={left:0,top:0},e.parentData={element:a(document),left:0,top:0,width:a(document).width(),height:a(document).height()||document.body.parentNode.scrollHeight};else{var j=a(i),k=[];a(["Top","Right","Left","Bottom"]).each(function(a,b){k[a]=c(j.css("padding"+b))}),e.containerOffset=j.offset(),e.containerPosition=j.position(),e.containerSize={height:j.innerHeight()-k[3],width:j.innerWidth()-k[1]};var l=e.containerOffset,m=e.containerSize.height,n=e.containerSize.width,o=a.ui.hasScroll(i,"left")?i.scrollWidth:n,p=a.ui.hasScroll(i)?i.scrollHeight:m;e.parentData={element:i,left:l.left,top:l.top,width:o,height:p}}}},resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.containerSize,g=d.containerOffset,h=d.size,i=d.position,j=d._aspectRatio||b.shiftKey,k={top:0,left:0},l=d.containerElement;l[0]!=document&&/static/.test(l.css("position"))&&(k=g),i.left<(d._helper?g.left:0)&&(d.size.width=d.size.width+(d._helper?d.position.left-g.left:d.position.left-k.left),j&&(d.size.height=d.size.width/e.aspectRatio),d.position.left=e.helper?g.left:0),i.top<(d._helper?g.top:0)&&(d.size.height=d.size.height+(d._helper?d.position.top-g.top:d.position.top),j&&(d.size.width=d.size.height*e.aspectRatio),d.position.top=d._helper?g.top:0),d.offset.left=d.parentData.left+d.position.left,d.offset.top=d.parentData.top+d.position.top;var m=Math.abs((d._helper?d.offset.left-k.left:d.offset.left-k.left)+d.sizeDiff.width),n=Math.abs((d._helper?d.offset.top-k.top:d.offset.top-g.top)+d.sizeDiff.height),o=d.containerElement.get(0)==d.element.parent().get(0),p=/relative|absolute/.test(d.containerElement.css("position"));o&&p +&&(m-=d.parentData.left),m+d.size.width>=d.parentData.width&&(d.size.width=d.parentData.width-m,j&&(d.size.height=d.size.width/d.aspectRatio)),n+d.size.height>=d.parentData.height&&(d.size.height=d.parentData.height-n,j&&(d.size.width=d.size.height*d.aspectRatio))},stop:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.position,g=d.containerOffset,h=d.containerPosition,i=d.containerElement,j=a(d.helper),k=j.offset(),l=j.outerWidth()-d.sizeDiff.width,m=j.outerHeight()-d.sizeDiff.height;d._helper&&!e.animate&&/relative/.test(i.css("position"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m}),d._helper&&!e.animate&&/static/.test(i.css("position"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m})}}),a.ui.plugin.add("resizable","ghost",{start:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.size;d.ghost=d.originalElement.clone(),d.ghost.css({opacity:.25,display:"block",position:"relative",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof e.ghost=="string"?e.ghost:""),d.ghost.appendTo(d.helper)},resize:function(b,c){var d=a(this).data("resizable"),e=d.options;d.ghost&&d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})},stop:function(b,c){var d=a(this).data("resizable"),e=d.options;d.ghost&&d.helper&&d.helper.get(0).removeChild(d.ghost.get(0))}}),a.ui.plugin.add("resizable","grid",{resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.size,g=d.originalSize,h=d.originalPosition,i=d.axis,j=e._aspectRatio||b.shiftKey;e.grid=typeof e.grid=="number"?[e.grid,e.grid]:e.grid;var k=Math.round((f.width-g.width)/(e.grid[0]||1))*(e.grid[0]||1),l=Math.round((f.height-g.height)/(e.grid[1]||1))*(e.grid[1]||1);/^(se|s|e)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l):/^(ne)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l):/^(sw)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.left=h.left-k):(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l,d.position.left=h.left-k)}});var c=function(a){return parseInt(a,10)||0},d=function(a){return!isNaN(parseInt(a,10))}})(jQuery); +/* + * jQuery hashchange event - v1.3 - 7/21/2010 + * http://benalman.com/projects/jquery-hashchange-plugin/ + * + * Copyright (c) 2010 "Cowboy" Ben Alman + * Dual licensed under the MIT and GPL licenses. + * http://benalman.com/about/license/ + */ +(function($,e,b){var c="hashchange",h=document,f,g=$.event.special,i=h.documentMode,d="on"+c in e&&(i===b||i>7);function a(j){j=j||location.href;return"#"+j.replace(/^[^#]*#?(.*)$/,"$1")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,"")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$(' + + +
+
+
Function Overview
+
+
+

The following list provides a brief overview of all CMSIS-RTOS functions. Functions marked with $ are optional. A CMSIS RTOS implementation may not provided functions, but this is clearly indicated with osFeatureXXXX defines.

+ + + + + + + + + + +
+ + + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html new file mode 100644 index 000000000..a1a118d58 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html @@ -0,0 +1,172 @@ + + + + + +CMSIS-RTOS: Using a CMSIS RTOS Implementation + + + + + + + + + + + + + + +
+
+
+ + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+ + +
+ +
+ + + + +
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Using a CMSIS RTOS Implementation
+
+
+

A CMSIS RTOS implementation is typically provided as a library. To add the RTOS functionality to an existing CMSIS-based application the RTOS library (and typically a configuration file) needs to be added. The available functionality of the RTOS library is defined in the file cmsis_os.h that is specific for each RTOS implementation.

+
+CMSIS_RTOS_Files.png +
+CMSIS-RTOS File Structure
+

Depending on the CMSIS-RTOS implementation, execution may start with the main function as the first thread. This has the benefit that an application programmer may use other middleware libraries that create threads internally, but the remaining part of the user application just uses the main thread. Therefore, the usage of the RTOS can be invisible to the application programmer, but libraries can use CMSIS-RTOS features.

+

Once the files are added to a project, the user can start using the CMSIS-RTOS functions. A code example is provided below:

+

Example

+
#include "cmsis_os.h" // CMSIS RTOS header file
+
+
void job1 (void const *argument) { // thread function 'job1'
+
while (1) {
+
: // execute some code
+
osDelay (10); // delay execution for 10 milliseconds
+
}
+
}
+
// define job1 as thread function
+
osThreadDef(job1, osPriorityAboveNormal, 1, 0); // define job1 as thread function
+
+
+
void job2 (void const *argument) { // thread function 'job2'
+
osThreadCreate(osThread(job1),NULL); // create job1 thread
+
while (1) {
+
: // execute some code
+
}
+
}
+
+
osThreadDef(job2, osPriorityNormal, 1, 0); // define job2 as thread function
+
+
void job3 (void const *argument) { // thread function 'job3'
+
while (1) {
+
: // execute some code
+
osDelay (20); // delay execution for 20 milliseconds
+
}
+
}
+
+
osThreadDef(job3, osPriorityNormal, 1, 0); // define job3 as thread function
+
+
int main (void) { // program execution starts here
+
osKernelInitialize (); // initialize RTOS kernel
+
: // setup and initialize peripherals
+
osThreadCreate (osThread(job2));
+
osThreadCreate (osThread(job3));
+
osKernelStart (); // start kernel with job2 execution
+
}
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/annotated.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/annotated.html new file mode 100644 index 000000000..71c8afbab --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/annotated.html @@ -0,0 +1,147 @@ + + + + + +CMSIS-RTOS: Data Structures + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
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+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Data Structures
+
+
+
Here are the data structures with brief descriptions:
+ + + + + + + + + + +
oCos_mailQ
oCosEventEvent structure contains detailed information about an event
oCosMailQDef_tDefinition structure for mail queue
oCosMessageQDef_tDefinition structure for message queue
oCosMutexDef_tMutex Definition structure contains setup information for a mutex
oCosPoolDef_tDefinition structure for memory block allocation
oCosSemaphoreDef_tSemaphore Definition structure contains setup information for a semaphore
oCosThreadDef_tThread Definition structure contains startup information of a thread
\CosTimerDef_tTimer Definition structure contains timer parameters
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/annotated.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/annotated.js new file mode 100644 index 000000000..3ed6589c9 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/annotated.js @@ -0,0 +1,12 @@ +var annotated = +[ + [ "os_mailQ", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos__mail_q", null ], + [ "osEvent", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event", "group___c_m_s_i_s___r_t_o_s___definitions" ], + [ "osMailQDef_t", "structos_mail_q_def__t.html", "structos_mail_q_def__t" ], + [ "osMessageQDef_t", "structos_message_q_def__t.html", "structos_message_q_def__t" ], + [ "osMutexDef_t", "structos_mutex_def__t.html", "structos_mutex_def__t" ], + [ "osPoolDef_t", "structos_pool_def__t.html", "structos_pool_def__t" ], + [ "osSemaphoreDef_t", "structos_semaphore_def__t.html", "structos_semaphore_def__t" ], + [ "osThreadDef_t", "structos_thread_def__t.html", "structos_thread_def__t" ], + [ "osTimerDef_t", "structos_timer_def__t.html", "structos_timer_def__t" ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/bc_s.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/bc_s.png new file mode 100644 index 000000000..224b29aa9 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/bc_s.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/bdwn.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/bdwn.png new file mode 100644 index 000000000..940a0b950 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/bdwn.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/classes.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/classes.html new file mode 100644 index 000000000..329738dc5 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/classes.html @@ -0,0 +1,143 @@ + + + + + +CMSIS-RTOS: Data Structure Index + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Data Structure Index
+
+
+
O
+ + + + + +
  O  
+		osEvent   osMutexDef_t   osThreadDef_t   
osMailQDef_t   osPoolDef_t   osTimerDef_t   
os_mailQ   osMessageQDef_t   osSemaphoreDef_t   
+
O
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/closed.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/closed.png new file mode 100644 index 000000000..98cc2c909 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/closed.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis.css b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis.css new file mode 100644 index 000000000..a9ec718c0 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis.css @@ -0,0 +1,1256 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 13px; + line-height: 1.3; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + border: 1px solid #2D4068; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + height: 28px; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + + + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; +} + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #354E81; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + width: 100%; + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + width: 100%; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + margin-left: 5px; + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 7px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html new file mode 100644 index 000000000..04fcbffe1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html @@ -0,0 +1,720 @@ + + + + + +CMSIS-RTOS: cmsis_os.h File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs | +Enumerations | +Functions
+
+
cmsis_os.h File Reference
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Structures

struct  osThreadDef_t
 Thread Definition structure contains startup information of a thread. More...
 
struct  osTimerDef_t
 Timer Definition structure contains timer parameters. More...
 
struct  osMutexDef_t
 Mutex Definition structure contains setup information for a mutex. More...
 
struct  osSemaphoreDef_t
 Semaphore Definition structure contains setup information for a semaphore. More...
 
struct  osPoolDef_t
 Definition structure for memory block allocation. More...
 
struct  osMessageQDef_t
 Definition structure for message queue. More...
 
struct  osMailQDef_t
 Definition structure for mail queue. More...
 
struct  osEvent
 Event structure contains detailed information about an event. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define osCMSIS   0x10002
 API version (main [31:16] .sub [15:0]) More...
 
#define osCMSIS_KERNEL   0x10000
 RTOS identification and version (main [31:16] .sub [15:0]) More...
 
#define osKernelSystemId   "KERNEL V1.00"
 RTOS identification string. More...
 
#define osFeature_MainThread   1
 main thread 1=main can be thread, 0=not available More...
 
#define osFeature_Pool   1
 Memory Pools: 1=available, 0=not available. More...
 
#define osFeature_MailQ   1
 Mail Queues: 1=available, 0=not available. More...
 
#define osFeature_MessageQ   1
 Message Queues: 1=available, 0=not available. More...
 
#define osFeature_Signals   8
 maximum number of Signal Flags available per thread More...
 
#define osFeature_Semaphore   30
 maximum count for osSemaphoreCreate function More...
 
#define osFeature_Wait   1
 osWait function: 1=available, 0=not available More...
 
#define osFeature_SysTick   1
 osKernelSysTick functions: 1=available, 0=not available More...
 
#define osWaitForever   0xFFFFFFFF
 Timeout value. More...
 
#define osKernelSysTickFrequency   100000000
 The RTOS kernel system timer frequency in Hz. More...
 
#define osKernelSysTickMicroSec(microsec)   (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
 Convert a microseconds value to a RTOS kernel system timer value. More...
 
#define osThreadDef(name, priority, instances, stacksz)
 Create a Thread Definition with function, priority, and stack requirements. More...
 
#define osThread(name)   &os_thread_def_##name
 Access a Thread definition. More...
 
#define osTimerDef(name, function)
 Define a Timer object. More...
 
#define osTimer(name)   &os_timer_def_##name
 Access a Timer definition. More...
 
#define osMutexDef(name)   const osMutexDef_t os_mutex_def_##name = { 0 }
 Define a Mutex. More...
 
#define osMutex(name)   &os_mutex_def_##name
 Access a Mutex definition. More...
 
#define osSemaphoreDef(name)   const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 Define a Semaphore object. More...
 
#define osSemaphore(name)   &os_semaphore_def_##name
 Access a Semaphore definition. More...
 
#define osPoolDef(name, no, type)
 Define a Memory Pool. More...
 
#define osPool(name)   &os_pool_def_##name
 Access a Memory Pool definition. More...
 
#define osMessageQDef(name, queue_sz, type)
 Create a Message Queue Definition. More...
 
#define osMessageQ(name)   &os_messageQ_def_##name
 Access a Message Queue Definition. More...
 
#define osMailQDef(name, queue_sz, type)
 Create a Mail Queue Definition. More...
 
#define osMailQ(name)   &os_mailQ_def_##name
 Access a Mail Queue Definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef void(* os_pthread )(void const *argument)
 Entry point of a thread. More...
 
typedef void(* os_ptimer )(void const *argument)
 Entry point of a timer call back function. More...
 
typedef struct os_thread_cb * osThreadId
 Thread ID identifies the thread (pointer to a thread control block). More...
 
typedef struct os_timer_cb * osTimerId
 Timer ID identifies the timer (pointer to a timer control block). More...
 
typedef struct os_mutex_cb * osMutexId
 Mutex ID identifies the mutex (pointer to a mutex control block). More...
 
typedef struct os_semaphore_cb * osSemaphoreId
 Semaphore ID identifies the semaphore (pointer to a semaphore control block). More...
 
typedef struct os_pool_cb * osPoolId
 Pool ID identifies the memory pool (pointer to a memory pool control block). More...
 
typedef struct os_messageQ_cb * osMessageQId
 Message ID identifies the message queue (pointer to a message queue control block). More...
 
typedef struct os_mailQ_cb * osMailQId
 Mail ID identifies the mail queue (pointer to a mail queue control block). More...
 
+ + + + + + + + + + +

+Enumerations

enum  osPriority {
+  osPriorityIdle = -3, +
+  osPriorityLow = -2, +
+  osPriorityBelowNormal = -1, +
+  osPriorityNormal = 0, +
+  osPriorityAboveNormal = +1, +
+  osPriorityHigh = +2, +
+  osPriorityRealtime = +3, +
+  osPriorityError = 0x84 +
+ }
 Priority used for thread control. More...
 
enum  osStatus {
+  osOK = 0, +
+  osEventSignal = 0x08, +
+  osEventMessage = 0x10, +
+  osEventMail = 0x20, +
+  osEventTimeout = 0x40, +
+  osErrorParameter = 0x80, +
+  osErrorResource = 0x81, +
+  osErrorTimeoutResource = 0xC1, +
+  osErrorISR = 0x82, +
+  osErrorISRRecursive = 0x83, +
+  osErrorPriority = 0x84, +
+  osErrorNoMemory = 0x85, +
+  osErrorValue = 0x86, +
+  osErrorOS = 0xFF, +
+  os_status_reserved = 0x7FFFFFFF +
+ }
 Status code values returned by CMSIS-RTOS functions. More...
 
enum  os_timer_type {
+  osTimerOnce = 0, +
+  osTimerPeriodic = 1 +
+ }
 Timer type value for the timer definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

osStatus osKernelInitialize (void)
 Initialize the RTOS Kernel for creating objects. More...
 
osStatus osKernelStart (void)
 Start the RTOS Kernel. More...
 
int32_t osKernelRunning (void)
 Check if the RTOS kernel is already started. More...
 
uint32_t osKernelSysTick (void)
 Get the RTOS kernel system timer counter. More...
 
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
 Create a thread and add it to Active Threads and set it to state READY. More...
 
osThreadId osThreadGetId (void)
 Return the thread ID of the current running thread. More...
 
osStatus osThreadTerminate (osThreadId thread_id)
 Terminate execution of a thread and remove it from Active Threads. More...
 
osStatus osThreadYield (void)
 Pass control to next thread that is in state READY. More...
 
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
 Change priority of an active thread. More...
 
osPriority osThreadGetPriority (osThreadId thread_id)
 Get current priority of an active thread. More...
 
osStatus osDelay (uint32_t millisec)
 Wait for Timeout (Time Delay). More...
 
osEvent osWait (uint32_t millisec)
 Wait for Signal, Message, Mail, or Timeout. More...
 
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)
 Create a timer. More...
 
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
 Start or restart a timer. More...
 
osStatus osTimerStop (osTimerId timer_id)
 Stop the timer. More...
 
osStatus osTimerDelete (osTimerId timer_id)
 Delete a timer that was created by osTimerCreate. More...
 
int32_t osSignalSet (osThreadId thread_id, int32_t signals)
 Set the specified Signal Flags of an active thread. More...
 
int32_t osSignalClear (osThreadId thread_id, int32_t signals)
 Clear the specified Signal Flags of an active thread. More...
 
osEvent osSignalWait (int32_t signals, uint32_t millisec)
 Wait for one or more Signal Flags to become signaled for the current RUNNING thread. More...
 
osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
 Create and Initialize a Mutex object. More...
 
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
 Wait until a Mutex becomes available. More...
 
osStatus osMutexRelease (osMutexId mutex_id)
 Release a Mutex that was obtained by osMutexWait. More...
 
osStatus osMutexDelete (osMutexId mutex_id)
 Delete a Mutex that was created by osMutexCreate. More...
 
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
 Create and Initialize a Semaphore object used for managing resources. More...
 
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
 Wait until a Semaphore token becomes available. More...
 
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
 Release a Semaphore token. More...
 
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
 Delete a Semaphore that was created by osSemaphoreCreate. More...
 
osPoolId osPoolCreate (const osPoolDef_t *pool_def)
 Create and Initialize a memory pool. More...
 
void * osPoolAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool. More...
 
void * osPoolCAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool and set memory block to zero. More...
 
osStatus osPoolFree (osPoolId pool_id, void *block)
 Return an allocated memory block back to a specific memory pool. More...
 
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize a Message Queue. More...
 
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
 Put a Message to a Queue. More...
 
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
 Get a Message or Wait for a Message from a Queue. More...
 
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize mail queue. More...
 
void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail. More...
 
void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail and set memory block to zero. More...
 
osStatus osMailPut (osMailQId queue_id, void *mail)
 Put a mail to a queue. More...
 
osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
 Get a mail from a queue. More...
 
osStatus osMailFree (osMailQId queue_id, void *mail)
 Free a memory block from a mail. More...
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define osWaitForever   0xFFFFFFFF
+
+
Note
MUST REMAIN UNCHANGED: osWaitForever shall be consistent in every CMSIS-RTOS. wait forever timeout value
+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* os_pthread)(void const *argument)
+
+
Note
MUST REMAIN UNCHANGED: os_pthread shall be consistent in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef void(* os_ptimer)(void const *argument)
+
+
Note
MUST REMAIN UNCHANGED: os_ptimer shall be consistent in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef struct os_mailQ_cb* osMailQId
+
+
Note
CAN BE CHANGED: os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef struct os_messageQ_cb* osMessageQId
+
+
Note
CAN BE CHANGED: os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef struct os_mutex_cb* osMutexId
+
+
Note
CAN BE CHANGED: os_mutex_cb is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef struct os_pool_cb* osPoolId
+
+
Note
CAN BE CHANGED: os_pool_cb is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef struct os_semaphore_cb* osSemaphoreId
+
+
Note
CAN BE CHANGED: os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef struct os_thread_cb* osThreadId
+
+
Note
CAN BE CHANGED: os_thread_cb is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
typedef struct os_timer_cb* osTimerId
+
+
Note
CAN BE CHANGED: os_timer_cb is implementation specific in every CMSIS-RTOS.
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum os_timer_type
+
+
Note
MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS.
+ + + +
Enumerator
osTimerOnce  +

one-shot timer

+
osTimerPeriodic  +

repeating timer

+
+ +
+
+ +
+
+ + + + +
enum osPriority
+
+
Note
MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS.
+ + + + + + + + + +
Enumerator
osPriorityIdle  +

priority: idle (lowest)

+
osPriorityLow  +

priority: low

+
osPriorityBelowNormal  +

priority: below normal

+
osPriorityNormal  +

priority: normal (default)

+
osPriorityAboveNormal  +

priority: above normal

+
osPriorityHigh  +

priority: high

+
osPriorityRealtime  +

priority: realtime (highest)

+
osPriorityError  +

system cannot determine priority or thread has illegal priority

+
+ +
+
+ +
+
+ + + + +
enum osStatus
+
+
Note
MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS.
+ + + + + + + + + + + + + + + + +
Enumerator
osOK  +

function completed; no error or event occurred.

+
osEventSignal  +

function completed; signal event occurred.

+
osEventMessage  +

function completed; message event occurred.

+
osEventMail  +

function completed; mail event occurred.

+
osEventTimeout  +

function completed; timeout occurred.

+
osErrorParameter  +

parameter error: a mandatory parameter was missing or specified an incorrect object.

+
osErrorResource  +

resource not available: a specified resource was not available.

+
osErrorTimeoutResource  +

resource not available within given time: a specified resource was not available within the timeout period.

+
osErrorISR  +

not allowed in ISR context: the function cannot be called from interrupt service routines.

+
osErrorISRRecursive  +

function called multiple times from ISR with same object.

+
osErrorPriority  +

system cannot determine priority or thread has illegal priority.

+
osErrorNoMemory  +

system is out of memory: it was impossible to allocate or reserve memory for the operation.

+
osErrorValue  +

value of a parameter is out of range.

+
osErrorOS  +

unspecified RTOS error: run-time error but no other error message fits.

+
os_status_reserved  +

prevent from enum down-size compiler optimization.

+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html new file mode 100644 index 000000000..e40fbeb89 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html @@ -0,0 +1,193 @@ + + + + + +CMSIS-RTOS: cmsis_os.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Enumerations
+
+
cmsis_os.txt File Reference
+
+
+ + + + + + + + +

+Enumerations

enum  osPriority {
+  osPriorityIdle = -3, +
+  osPriorityLow = -2, +
+  osPriorityBelowNormal = -1, +
+  osPriorityNormal = 0, +
+  osPriorityAboveNormal = +1, +
+  osPriorityHigh = +2, +
+  osPriorityRealtime = +3, +
+  osPriorityError = 0x84 +
+ }
 
enum  os_timer_type {
+  osTimerOnce = 0, +
+  osTimerPeriodic = 1 +
+ }
 
enum  osStatus {
+  osOK = 0, +
+  osEventSignal = 0x08, +
+  osEventMessage = 0x10, +
+  osEventMail = 0x20, +
+  osEventTimeout = 0x40, +
+  osErrorParameter = 0x80, +
+  osErrorResource = 0x81, +
+  osErrorTimeoutResource = 0xC1, +
+  osErrorISR = 0x82, +
+  osErrorISRRecursive = 0x83, +
+  osErrorPriority = 0x84, +
+  osErrorNoMemory = 0x85, +
+  osErrorValue = 0x86, +
+  osErrorOS = 0xFF, +
+  os_status_reserved = 0x7FFFFFFF +
+ }
 
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html new file mode 100644 index 000000000..f3378a400 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html @@ -0,0 +1,166 @@ + + + + + +CMSIS-RTOS: Header File Template: cmsis_os.h + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Header File Template: cmsis_os.h
+
+
+

The file cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). Each RTOS that is compliant with CMSIS-RTOS shall provide a specific cmsis_os.h header file that represents its implementation.

+

The file cmsis_os.h contains:

+
    +
  • CMSIS-RTOS API function definitions
    • +
  • struct definitions for parameters and return types
    • +
  • status and priority values used by CMSIS-RTOS API functions
    • +
  • macros for defining threads and other kernel objects
    • +
+

Name conventions and header file modifications

+

All definitions are prefixed with os to give an unique name space for CMSIS-RTOS functions. Definitions that are prefixed os_ are not used in the application code but local to this header file. All definitions and functions that belong to a module are grouped and have a common prefix, i.e. osThread.

+

Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. These definitions can be specific to the underlying RTOS kernel.

+

Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.

+

Function calls from interrupt service routines

+

The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):

+ +

Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called from an ISR context the status code osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.

+

Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code osErrorISRRecursive.

+

Define and reference object definitions

+

With #define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file that is used throughout a project as shown below:

+

Header File

+
#include <cmsis_os.h> // CMSIS RTOS header file
+
+
// Thread definition
+
extern void thread_sample (void const *argument); // function prototype
+
osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+
// Pool definition
+
osPoolDef(MyPool, 10, long);
+

This header file defines all objects when included in a C/C++ source file. When #define osObjectsExternal is present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be used throughout the whole project.

+

Example

+
#include "osObjects.h" // Definition of the CMSIS-RTOS objects
+
#define osObjectExternal // Objects will be defined as external symbols
+
#include "osObjects.h" // Reference to the CMSIS-RTOS objects
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dir_67baed4ff719a838d401a6dc7774cf41.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dir_67baed4ff719a838d401a6dc7774cf41.html new file mode 100644 index 000000000..1ab879a8c --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dir_67baed4ff719a838d401a6dc7774cf41.html @@ -0,0 +1,134 @@ + + + + + +CMSIS-RTOS: RTOS Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
RTOS Directory Reference
+
+
+ + + + +

+Directories

directory  Template
 
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dir_9afdeffb8e409a4e0df5c5bf9ab1a7d2.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dir_9afdeffb8e409a4e0df5c5bf9ab1a7d2.html new file mode 100644 index 000000000..f2cc75580 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dir_9afdeffb8e409a4e0df5c5bf9ab1a7d2.html @@ -0,0 +1,134 @@ + + + + + +CMSIS-RTOS: Template Directory Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Template Directory Reference
+
+
+ + + + +

+Files

file  cmsis_os.h
 
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/doxygen.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/doxygen.png new file mode 100644 index 000000000..3ff17d807 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/doxygen.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dynsections.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dynsections.js new file mode 100644 index 000000000..ed092c7f6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + +CMSIS-RTOS: File List + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
File List
+
+
+
Here is a list of all files with brief descriptions:
+ + +
\*cmsis_os.h
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2blank.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2blank.png new file mode 100644 index 000000000..63c605bb4 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2blank.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2cl.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2cl.png new file mode 100644 index 000000000..132f6577b Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2cl.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2doc.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2doc.png new file mode 100644 index 000000000..17edabff9 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2doc.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2folderclosed.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2folderclosed.png new file mode 100644 index 000000000..bb8ab35ed Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2folderclosed.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2folderopen.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2folderopen.png new file mode 100644 index 000000000..d6c7f676a Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2folderopen.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2lastnode.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2lastnode.png new file mode 100644 index 000000000..63c605bb4 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2lastnode.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2link.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2link.png new file mode 100644 index 000000000..17edabff9 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2link.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mlastnode.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mlastnode.png new file mode 100644 index 000000000..0b63f6d38 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mlastnode.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mnode.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mnode.png new file mode 100644 index 000000000..0b63f6d38 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mnode.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mo.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mo.png new file mode 100644 index 000000000..4bfb80f76 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2mo.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2node.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2node.png new file mode 100644 index 000000000..63c605bb4 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2node.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2ns.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2ns.png new file mode 100644 index 000000000..72e3d71c2 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2ns.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2plastnode.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2plastnode.png new file mode 100644 index 000000000..c6ee22f93 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2plastnode.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2pnode.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2pnode.png new file mode 100644 index 000000000..c6ee22f93 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2pnode.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2splitbar.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2splitbar.png new file mode 100644 index 000000000..fe895f2c5 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2splitbar.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2vertline.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2vertline.png new file mode 100644 index 000000000..63c605bb4 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/ftv2vertline.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/functions.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/functions.html new file mode 100644 index 000000000..0d32455de --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/functions.html @@ -0,0 +1,198 @@ + + + + + +CMSIS-RTOS: Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/functions_vars.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/functions_vars.html new file mode 100644 index 000000000..4471846b8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/functions_vars.html @@ -0,0 +1,198 @@ + + + + + +CMSIS-RTOS: Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  +
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals.html new file mode 100644 index 000000000..3e3e1667e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals.html @@ -0,0 +1,460 @@ + + + + + +CMSIS-RTOS: Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+ +

- o -

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_defs.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_defs.html new file mode 100644 index 000000000..44fbd1b64 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_defs.html @@ -0,0 +1,219 @@ + + + + + +CMSIS-RTOS: Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  +
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_enum.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_enum.html new file mode 100644 index 000000000..0612f8240 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_enum.html @@ -0,0 +1,147 @@ + + + + + +CMSIS-RTOS: Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  +
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_eval.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_eval.html new file mode 100644 index 000000000..c1a9350cc --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_eval.html @@ -0,0 +1,210 @@ + + + + + +CMSIS-RTOS: Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  +
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_func.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_func.html new file mode 100644 index 000000000..09f197120 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_func.html @@ -0,0 +1,262 @@ + + + + + +CMSIS-RTOS: Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- o -

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_type.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_type.html new file mode 100644 index 000000000..6689d8b16 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/globals_type.html @@ -0,0 +1,162 @@ + + + + + +CMSIS-RTOS: Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  +
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html new file mode 100644 index 000000000..93daa5cd3 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html @@ -0,0 +1,174 @@ + + + + + +CMSIS-RTOS: CMSIS-RTOS API + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content
+
+
CMSIS-RTOS API
+
+
+ +

This section describes the CMSIS-RTOS API. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Content

 Kernel Information and Control
 Provide version/system information and start the RTOS Kernel.
 
 Thread Management
 Define, create, and control thread functions.
 
 Generic Wait Functions
 Wait for a time period or unspecified events.
 
 Timer Management
 Create and control timer and timer callback functions.
 
 Signal Management
 Control or wait for signal flags.
 
 Mutex Management
 Synchronize thread execution with a Mutex.
 
 Semaphore Management
 Control access to shared resources.
 
 Memory Pool Management
 Define and manage fixed-size memory pools.
 
 Message Queue Management
 Control, send, receive, or wait for messages.
 
 Mail Queue Management
 Control, send, receive, or wait for mail.
 
 Generic Data Types and Definitions
 Data Type Definitions used by the CMSIS-RTOS API functions.
 
 Status and Error Codes
 Status and Error Codes returned by CMSIS-RTOS API functions.
 
+

Description

+

The CMSIS-RTOS is a generic API layer that interfaces to an existing RTOS kernel. It provides the following functional modules:

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.js new file mode 100644 index 000000000..7656915b8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.js @@ -0,0 +1,15 @@ +var group___c_m_s_i_s___r_t_o_s = +[ + [ "Kernel Information and Control", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl" ], + [ "Thread Management", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html", "group___c_m_s_i_s___r_t_o_s___thread_mgmt" ], + [ "Generic Wait Functions", "group___c_m_s_i_s___r_t_o_s___wait.html", "group___c_m_s_i_s___r_t_o_s___wait" ], + [ "Timer Management", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html", "group___c_m_s_i_s___r_t_o_s___timer_mgmt" ], + [ "Signal Management", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html", "group___c_m_s_i_s___r_t_o_s___signal_mgmt" ], + [ "Mutex Management", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt" ], + [ "Semaphore Management", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt" ], + [ "Memory Pool Management", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html", "group___c_m_s_i_s___r_t_o_s___pool_mgmt" ], + [ "Message Queue Management", "group___c_m_s_i_s___r_t_o_s___message.html", "group___c_m_s_i_s___r_t_o_s___message" ], + [ "Mail Queue Management", "group___c_m_s_i_s___r_t_o_s___mail.html", "group___c_m_s_i_s___r_t_o_s___mail" ], + [ "Generic Data Types and Definitions", "group___c_m_s_i_s___r_t_o_s___definitions.html", "group___c_m_s_i_s___r_t_o_s___definitions" ], + [ "Status and Error Codes", "group___c_m_s_i_s___r_t_o_s___status.html", "group___c_m_s_i_s___r_t_o_s___status" ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html new file mode 100644 index 000000000..fe9f33c06 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html @@ -0,0 +1,297 @@ + + + + + +CMSIS-RTOS: Generic Data Types and Definitions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures
+
+
Generic Data Types and Definitions
CMSIS-RTOS API
+
+
+ +

Data Type Definitions used by the CMSIS-RTOS API functions. +More...

+ + + + + + + +

+Data Structures

struct  osEvent
 Event structure contains detailed information about an event. More...
 
struct  os_mailQ
 
+

Description

+

The Data Type section lists all data types that are used to exchange information with CMSIS-RTOS functions.

+

Data Structure Documentation

+ +
+
+ + + + +
struct osEvent
+
+
Note
MUST REMAIN UNCHANGED: os_event shall be consistent in every CMSIS-RTOS. However the struct may be extended at the end.
+

The osEvent structure describes the events returned by CMSIS-RTOS functions.

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

osStatus status
 status code: event or error information More...
 
union {
   uint32_t   v
 message as 32-bit value More...
 
   void *   p
 message or mail as void pointer More...
 
   int32_t   signals
 signal flags More...
 
} value
 event value More...
 
union {
   osMailQId   mail_id
 mail id obtained by osMailCreate More...
 
   osMessageQId   message_id
 message id obtained by osMessageCreate More...
 
} def
 event definition More...
 
+

Field Documentation

+ +
+
+ + + + +
union { ... } def
+
+ +
+
+ +
+
+ + + + +
osMailQId mail_id
+
+ +
+
+ +
+
+ + + + +
osMessageQId message_id
+
+ +
+
+ +
+
+ + + + +
void* p
+
+ +
+
+ +
+
+ + + + +
int32_t signals
+
+ +
+
+ +
+
+ + + + +
osStatus status
+
+ +
+
+ +
+
+ + + + +
uint32_t v
+
+ +
+
+ +
+
+ + + + +
union { ... } value
+
+ +
+
+ +
+
+ +
+
+ + + + +
struct os_mailQ
+
+

The osEvent structure describes the events returned by CMSIS-RTOS functions.

+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.js new file mode 100644 index 000000000..6e901dc34 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.js @@ -0,0 +1,11 @@ +var group___c_m_s_i_s___r_t_o_s___definitions = +[ + [ "def", "group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6", null ], + [ "mail_id", "group___c_m_s_i_s___r_t_o_s___definitions.html#ac86175a4b1706bee596f3018322df26e", null ], + [ "message_id", "group___c_m_s_i_s___r_t_o_s___definitions.html#af394cbe21dde7377974e63af38cd87b0", null ], + [ "p", "group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709", null ], + [ "signals", "group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6", null ], + [ "status", "group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3", null ], + [ "v", "group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc", null ], + [ "value", "group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html new file mode 100644 index 000000000..1c5cd2597 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html @@ -0,0 +1,465 @@ + + + + + +CMSIS-RTOS: Kernel Information and Control + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Kernel Information and Control
CMSIS-RTOS API
+
+
+ +

Provide version/system information and start the RTOS Kernel. +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define osFeature_MainThread   1
 main thread 1=main can be thread, 0=not available More...
 
#define osFeature_SysTick   1
 osKernelSysTick functions: 1=available, 0=not available More...
 
#define osCMSIS   0x10002
 API version (main [31:16] .sub [15:0]) More...
 
#define osCMSIS_KERNEL   0x10000
 RTOS identification and version (main [31:16] .sub [15:0]) More...
 
#define osKernelSystemId   "KERNEL V1.00"
 RTOS identification string. More...
 
#define osKernelSysTickFrequency   100000000
 The RTOS kernel system timer frequency in Hz. More...
 
#define osKernelSysTickMicroSec(microsec)   (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
 Convert a microseconds value to a RTOS kernel system timer value. More...
 
+ + + + + + + + + + + + + +

+Functions

osStatus osKernelInitialize (void)
 Initialize the RTOS Kernel for creating objects. More...
 
osStatus osKernelStart (void)
 Start the RTOS Kernel. More...
 
int32_t osKernelRunning (void)
 Check if the RTOS kernel is already started. More...
 
uint32_t osKernelSysTick (void)
 Get the RTOS kernel system timer counter. More...
 
+

Description

+

The Kernel Information and Control function group allow to:

+
    +
  • obtain information about the system and the underlying kernel.
    • +
  • obtain version information about the CMSIS RTOS API.
    • +
  • initialize of the RTOS kernel for creating objects.
    • +
  • start the RTOS kernel and thread switching.
    • +
  • check the execution status of the RTOS kernel.
    • +
+

The function main is a special thread function that may be started at system initialization. In this case it has the initial priority osPriorityNormal.

+

Example

+
void system_error (void) {
+
// fatal error: set system to a safe state
+
while (1);
+
}
+
+
+
int main (void) { // program execution starts here
+
if (osKernelInitialize () != osOK) { // initialize RTOS kernel
+
system_error (); // invoke system error function
+
}
+
+
system_initialize (); // setup and initialize peripherals
+
osThreadCreate (osThread(job1)); // create threads
+
osThreadCreate (osThread(job2));
+
if (osKernelStart () != osOK) { // start kernel with job2 execution
+
system_error (); // invoke system error function
+
}
+
}
+

Macro Definition Documentation

+ +
+
+ + + + +
#define osCMSIS   0x10002
+
+

Version information of the CMSIS RTOS API whereby major version is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.

+
Note
MUST REMAIN UNCHANGED: osCMSIS identifies the CMSIS-RTOS API version.
+ +
+
+ +
+
+ + + + +
#define osCMSIS_KERNEL   0x10000
+
+

Identifies the underlying RTOS kernel and version number. The actual name of that define depends on the RTOS Kernel used in the implementation. For example, osCMSIS_FreeRTOS identifies the FreeRTOS kernel and the value indicates the version number of that kernel whereby the major version is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.

+
Note
CAN BE CHANGED: osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+ +
+
+ +
+
+ + + + +
#define osFeature_MainThread   1
+
+

A CMSIS-RTOS implementation may support to start thread execution with the function 'main'.

+ +
Note
MUST REMAIN UNCHANGED: osFeature_xxx shall be consistent in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
#define osFeature_SysTick   1
+
+

A CMSIS-RTOS implementation may provide access to the RTOS kernel system timer.

+ + +
+
+ +
+
+ + + + +
#define osKernelSystemId   "KERNEL V1.00"
+
+

Defines a string that identifies the underlying RTOS Kernel and provides version information. The length of that string is limited to 21 bytes. A valid identification string is for example, "FreeRTOS V1.00".

+
Note
MUST REMAIN UNCHANGED: osKernelSystemId shall be consistent in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + +
#define osKernelSysTickFrequency   100000000
+
+

Specifies the frequency of the Kernel SysTick timer in Hz. The value is typically use to scale a time value and is for example used in osKernelSysTickMicroSec.

+
See Also
osKernelSysTick
+
Note
Reflects the system timer setting and is typically defined in a configuration file.
+ +
+
+ +
+
+ + + + + + + + +
#define osKernelSysTickMicroSec( microsec)   (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+
+

Allows to scale a microsecond value to the frequency of the Kernel SysTick timer. This macro is typically used to check for short timeouts in polling loops.

+
See Also
osKernelSysTick
+
Parameters
+ + +
microsectime value in microseconds.
+
+
+
Returns
time value normalized to the osKernelSysTickFrequency
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
osStatus osKernelInitialize (void )
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osKernelInitialize shall be consistent in every CMSIS-RTOS.
+

Initialize of the RTOS Kernel to allow peripheral setup and creation of other RTOS objects with the functions:

+ +

The RTOS kernel does not start thread switching until the function osKernelStart is called.

+
Note
In case that the RTOS Kernel starts thread execution with the function main the function osKernelInitialize stops thread switching. This allows to setup the system to a defined state before thread switching is resumed with osKernelStart.
+

Example

+
#include "cmsis_os.h"
+
+
int main (void) {
+
if (!osKernelRunning ()) { // if kernel is not running, initialize the kernel
+
if (osKernelInitialize () != osOK) { // check osStatus for other possible valid values
+
// exit with an error message
+
}
+
}
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t osKernelRunning (void )
+
+
Note
MUST REMAIN UNCHANGED: osKernelRunning shall be consistent in every CMSIS-RTOS.
+
Returns
0 RTOS is not started, 1 RTOS is started.
+

Identifies if the RTOS kernel is started. For systems with the option to start the main function as a thread this allows to identify that the RTOS kernel is already running.

+

Example

+
#include "cmsis_os.h"
+
+
int main (void) { // program execution starts here
+
if (osKernelRunning ()) {
+
: // main is already a thread function
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osKernelStart (void )
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osKernelStart shall be consistent in every CMSIS-RTOS.
+

Start the RTOS Kernel and begin thread switching.

+
Note
When the CMSIS-RTOS starts thread execution with the function main this function resumes thread switching. The main thread will continue executing after osKernelStart.
+

Status and Error Codes
+

+
    +
  • osOK: the RTOS kernel has been successfully started.
    • +
  • osErrorISR: osKernelStart cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
int main (void) {
+
if (osKernelInitialize () != osOK) { // check osStatus for other possible valid values
+
// exit with an error message
+
}
+
+
if (!osKernelRunning ()) { // is the kernel running ?
+
if (osKernelStart () != osOK) { // start the kernel
+
// kernel could not be started
+
}
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
uint32_t osKernelSysTick (void )
+
+
Note
MUST REMAIN UNCHANGED: osKernelSysTick shall be consistent in every CMSIS-RTOS.
+
Returns
RTOS kernel system timer as 32-bit value
+

Get the value of the Kernel SysTick timer for time comparison. The value is a rolling 32-bit counter that is typically composed of the kernel system interrupt timer value and an counter that counts these interrupts.

+

This function allows the implementation of timeout checks. These are for example required when checking for a busy status in a device or peripheral initialization routine.

+

Example

+
#include "cmsis_os.h"
+
+
void SetupDevice (void) {
+
uint32_t tick;
+
+
tick = osKernelSysTick(); // get start value of the Kernel system tick
+
Device.Setup (); // initialize a device or peripheral
+
do { // poll device busy status for 100 microseconds
+
if (!Device.Busy) break; // check if device is correctly initialized
+
} while ((osKernelSysTick() - tick) < osKernelTickMicroSec(100));
+
if (Device.Busy) {
+
; // in case device still busy, signal error
+
}
+
// start interacting with device
+
}
+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.js new file mode 100644 index 000000000..50eddf652 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.js @@ -0,0 +1,14 @@ +var group___c_m_s_i_s___r_t_o_s___kernel_ctrl = +[ + [ "osCMSIS", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1", null ], + [ "osCMSIS_KERNEL", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de", null ], + [ "osFeature_MainThread", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696", null ], + [ "osFeature_SysTick", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gae554ec16c23c5b7d65affade2a351891", null ], + [ "osKernelSystemId", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga47cf03658f01cdffca688e9096b58289", null ], + [ "osKernelSysTickFrequency", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga9e0954d52722673e2031233a2ab99960", null ], + [ "osKernelSysTickMicroSec", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gae12c190af42d7310d8006d64f4ed5a88", null ], + [ "osKernelInitialize", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga53d078a801022e202e8115c083ece68e", null ], + [ "osKernelRunning", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5", null ], + [ "osKernelStart", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gaab668ffd2ea76bb0a77ab0ab385eaef2", null ], + [ "osKernelSysTick", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gad0262e4688e95d1e9038afd9bcc16001", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html new file mode 100644 index 000000000..1f051bc4c --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html @@ -0,0 +1,590 @@ + + + + + +CMSIS-RTOS: Mail Queue Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
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+
+ +
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+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Mail Queue Management
CMSIS-RTOS API
+
+
+ +

Control, send, receive, or wait for mail. +More...

+ + + + + + + + + + + +

+Macros

#define osFeature_MailQ   1
 Mail Queues: 1=available, 0=not available. More...
 
#define osMailQDef(name, queue_sz, type)
 Create a Mail Queue Definition. More...
 
#define osMailQ(name)   &os_mailQ_def_##name
 Access a Mail Queue Definition. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize mail queue. More...
 
void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail. More...
 
void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail and set memory block to zero. More...
 
osStatus osMailPut (osMailQId queue_id, void *mail)
 Put a mail to a queue. More...
 
osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
 Get a mail from a queue. More...
 
osStatus osMailFree (osMailQId queue_id, void *mail)
 Free a memory block from a mail. More...
 
+

Description

+

The Mail Queue Management function group allow to control, send, receive, or wait for mail. A mail is a memory block that is send to a thread or interrupt service routine.

+
+MailQueue.png +
+CMSIS-RTOS Mail Queue
+

Macro Definition Documentation

+ +
+
+ + + + +
#define osFeature_MailQ   1
+
+

A CMSIS-RTOS implementation may support mail queues.

+ + +
+
+ +
+
+ + + + + + + + +
#define osMailQ( name)   &os_mailQ_def_##name
+
+

Access to the mail queue definition for the function osMailCreate.

+
Parameters
+ + +
namename of the queue
+
+
+
Note
CAN BE CHANGED: The parameter to osMailQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define osMailQDef( name,
 queue_sz,
 type 
)
+
+

Define the attributes of a mail queue that can by the function osMailCreate using osMailQ.

+
Parameters
+ + + + +
namename of the queue
queue_szmaximum number of messages in queue
typedata type of a single message element
+
+
+
Note
CAN BE CHANGED: The parameter to osMailQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void * osMailAlloc (osMailQId queue_id,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]queue_idmail queue ID obtained with osMailCreate.
[in]millisectimeout value or 0 in case of no time-out
+
+
+
Returns
pointer to memory block that can be filled with mail or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osMailAlloc shall be consistent in every CMSIS-RTOS.
+

Allocate a memory block from the mail queue that is filled with the mail information.

+

The argument queue_id specifies a mail queue identifier that is obtain with osMailCreate.

+

The argument millisec specifies how long the system waits for a mail slot to become available. While the system waits the tread calling this function is put into the state WAITING. The millisec timeout can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until a mail slot can be allocated.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+
Note
The parameter millisec must be 0 for using this function in an ISR.
+

A NULL pointer is returned when no memory slot can be obtained or queue specifies an illegal parameter.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void * osMailCAlloc (osMailQId queue_id,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]queue_idmail queue ID obtained with osMailCreate.
[in]millisectimeout value or 0 in case of no time-out
+
+
+
Returns
pointer to memory block that can be filled with mail or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osMailCAlloc shall be consistent in every CMSIS-RTOS.
+

Allocate a memory block from the mail queue that is filled with the mail information. The memory block returned is cleared.

+

The argument queue_id specifies a mail queue identifier that is obtain with osMailCreate.

+

The argument millisec specifies how long the system waits for a mail slot to become available. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until a mail slot can be allocated.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+
Note
The parameter millisec must be 0 for using this function in an ISR.
+

A NULL pointer is returned when no memory block can be obtained or queue specifies an illegal parameter.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osMailQId osMailCreate (const osMailQDef_t * queue_def,
osThreadId thread_id 
)
+
+
Parameters
+ + + +
[in]queue_defreference to the mail queue definition obtain with osMailQ
[in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL.
+
+
+
Returns
mail queue ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osMailCreate shall be consistent in every CMSIS-RTOS.
+

Initialize and create a mail queue.

+

Example

+
#include "cmsis_os.h"
+
+
osThreadId tid_thread1; // ID for thread 1
+
osThreadId tid_thread2; // ID for thread 2
+
+
typedef struct { // Mail object structure
+
float voltage; // AD result of measured voltage
+
float current; // AD result of measured current
+
int counter; // A counter value
+
} T_MEAS;
+
+
osMailQDef(mail, 16, T_MEAS); // Define mail queue
+
osMailQId mail;
+
+
void send_thread (void const *argument); // forward reference
+
void recv_thread (void const *argument);
+
+
osThreadDef(send_thread, osPriorityNormal, 1, 0); // thread definitions
+
osThreadDef(recv_thread, osPriorityNormal, 1, 2000);
+
+
/*
+
Thread 1: Send thread
+
*/
+
void send_thread (void const *argument) {
+
T_MEAS *mptr;
+
+
mptr = osMailAlloc(mail, osWaitForever); // Allocate memory
+
mptr->voltage = 223.72; // Set the mail content
+
mptr->current = 17.54;
+
mptr->counter = 120786;
+
osMailPut(mail, mptr); // Send Mail
+
osDelay(100);
+
+
mptr = osMailAlloc(mail, osWaitForever); // Allocate memory
+
mptr->voltage = 227.23; // Prepare 2nd mail
+
mptr->current = 12.41;
+
mptr->counter = 170823;
+
osMailPut(mail, mptr); // Send Mail
+
osThreadYield(); // Cooperative multitasking
+
// We are done here, exit this thread
+
}
+
+
/*
+
Thread 2: Receive thread
+
*/
+
void recv_thread (void const *argument) {
+
T_MEAS *rptr;
+
osEvent evt;
+
+
for (;;) {
+
evt = osMailGet(mail, osWaitForever); // wait for mail
+
if (evt.status == osEventMail) {
+
rptr = evt.value.p;
+
printf ("\nVoltage: %.2f V\n", rptr->voltage);
+
printf ("Current: %.2f A\n", rptr->current);
+
printf ("Number of cycles: %d\n", rptr->counter);
+
osMailFree(mail, rptr); // free memory allocated for mail
+
}
+
}
+
}
+
+
void StartApplication (void) {
+
mail = osMailCreate(osMailQ(mail), NULL); // create mail queue
+
+
tid_thread1 = osThreadCreate(osThread(send_thread), NULL);
+
tid_thread2 = osThreadCreate(osThread(recv_thread), NULL);
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osStatus osMailFree (osMailQId queue_id,
void * mail 
)
+
+
Parameters
+ + + +
[in]queue_idmail queue ID obtained with osMailCreate.
[in]mailpointer to the memory block that was obtained with osMailGet.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osMailFree shall be consistent in every CMSIS-RTOS.
+

Free the memory block specified by mail and return it to the mail queue.

+

Status and Error Codes
+

+
    +
  • osOK: the mail block is released.
    • +
  • osErrorValue: mail block does not belong to the mail queue pool.
    • +
  • osErrorParameter: the value to the parameter queue_id is incorrect.
    • +
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osEvent osMailGet (osMailQId queue_id,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]queue_idmail queue ID obtained with osMailCreate.
[in]millisectimeout value or 0 in case of no time-out
+
+
+
Returns
event that contains mail information or error code.
+
Note
MUST REMAIN UNCHANGED: osMailGet shall be consistent in every CMSIS-RTOS.
+

Suspend the execution of the current RUNNING thread until a mail arrives. When a mail is already in the queue, the function returns instantly with the mail information.

+

The argument millisec specifies how long the system waits for a mail to arrive. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until a mail arrives.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+
Note
The parameter millisec must be 0 for using this function in an ISR.
+

Status and Error Codes
+

+
    +
  • osOK: no mail is available in the queue and no timeout was specified
    • +
  • osEventTimeout: no mail has arrived during the given timeout period.
    • +
  • osEventMail: mail received, value.p contains the pointer to mail content.
    • +
  • osErrorParameter: a parameter is invalid or outside of a permitted range.
    • +
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osStatus osMailPut (osMailQId queue_id,
void * mail 
)
+
+
Parameters
+ + + +
[in]queue_idmail queue ID obtained with osMailCreate.
[in]mailmemory block previously allocated with osMailAlloc or osMailCAlloc.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osMailPut shall be consistent in every CMSIS-RTOS.
+

Put the memory block specified with mail into the mail queue specified by queue.

+

Status and Error Codes
+

+
    +
  • osOK: the message is put into the queue.
    • +
  • osErrorValue: mail was previously not allocated as memory slot.
    • +
  • osErrorParameter: a parameter is invalid or outside of a permitted range.
    • +
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.js new file mode 100644 index 000000000..72ce80139 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.js @@ -0,0 +1,12 @@ +var group___c_m_s_i_s___r_t_o_s___mail = +[ + [ "osFeature_MailQ", "group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e", null ], + [ "osMailQ", "group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2", null ], + [ "osMailQDef", "group___c_m_s_i_s___r_t_o_s___mail.html#ga58d712b16c0c6668059f509386d1e55b", null ], + [ "osMailAlloc", "group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194", null ], + [ "osMailCAlloc", "group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd", null ], + [ "osMailCreate", "group___c_m_s_i_s___r_t_o_s___mail.html#gaa177e7fe5820dd70d8c9e46ded131174", null ], + [ "osMailFree", "group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc", null ], + [ "osMailGet", "group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd", null ], + [ "osMailPut", "group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html new file mode 100644 index 000000000..a80b4fe95 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html @@ -0,0 +1,466 @@ + + + + + +CMSIS-RTOS: Message Queue Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Message Queue Management
CMSIS-RTOS API
+
+
+ +

Control, send, receive, or wait for messages. +More...

+ + + + + + + + + + + +

+Macros

#define osFeature_MessageQ   1
 Message Queues: 1=available, 0=not available. More...
 
#define osMessageQDef(name, queue_sz, type)
 Create a Message Queue Definition. More...
 
#define osMessageQ(name)   &os_messageQ_def_##name
 Access a Message Queue Definition. More...
 
+ + + + + + + + + + +

+Functions

osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize a Message Queue. More...
 
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
 Put a Message to a Queue. More...
 
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
 Get a Message or Wait for a Message from a Queue. More...
 
+

Description

+

Message Queue Management functions allow to control, send, receive, or wait for messages. A message can be an integer or pointer value that is send to a thread or interrupt service routine.

+
+MessageQueue.png +
+CMSIS-RTOS Message Queue
+

Macro Definition Documentation

+ +
+
+ + + + +
#define osFeature_MessageQ   1
+
+

A CMSIS-RTOS implementation may support message queues.

+ + +
+
+ +
+
+ + + + + + + + +
#define osMessageQ( name)   &os_messageQ_def_##name
+
+

Access to the message queue definition for the function osMessageCreate.

+
Parameters
+ + +
namename of the queue
+
+
+
Note
CAN BE CHANGED: The parameter to osMessageQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define osMessageQDef( name,
 queue_sz,
 type 
)
+
+

Define the attributes of a message queue created by the function osMessageCreate using osMessageQ.

+
Parameters
+ + + + +
namename of the queue.
queue_szmaximum number of messages in the queue.
typedata type of a single message element (for debugger).
+
+
+
Note
CAN BE CHANGED: The parameter to osMessageQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
osMessageQId osMessageCreate (const osMessageQDef_t * queue_def,
osThreadId thread_id 
)
+
+
Parameters
+ + + +
[in]queue_defqueue definition referenced with osMessageQ.
[in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL.
+
+
+
Returns
message queue ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osMessageCreate shall be consistent in every CMSIS-RTOS.
+

Create and initialize a message queue.

+

Example

+
#include "cmsis_os.h"
+
+
osThreadId tid_thread1; // ID for thread 1
+
osThreadId tid_thread2; // for thread 2
+
+
typedef struct { // Message object structure
+
float voltage; // AD result of measured voltage
+
float current; // AD result of measured current
+
int counter; // A counter value
+
} T_MEAS;
+
+
osPoolDef(mpool, 16, T_MEAS); // Define memory pool
+
osPoolId mpool;
+
osMessageQDef(MsgBox, 16, T_MEAS); // Define message queue
+
osMessageQId MsgBox;
+
+
void send_thread (void const *argument); // forward reference
+
void recv_thread (void const *argument); // forward reference
+
// Thread definitions
+
osThreadDef(send_thread, osPriorityNormal, 1, 0);
+
osThreadDef(recv_thread, osPriorityNormal, 1, 2000);
+
+
/*
+
Thread 1: Send thread
+
*/
+
void send_thread (void const *argument) {
+
T_MEAS *mptr;
+
+
mptr = osPoolAlloc(mpool); // Allocate memory for the message
+
mptr->voltage = 223.72; // Set the message content
+
mptr->current = 17.54;
+
mptr->counter = 120786;
+
osMessagePut(MsgBox, (uint32_t)mptr, osWaitForever); // Send Message
+
osDelay(100);
+
+
mptr = osPoolAlloc(mpool); // Allocate memory for the message
+
mptr->voltage = 227.23; // Prepare a 2nd message
+
mptr->current = 12.41;
+
mptr->counter = 170823;
+
osMessagePut(MsgBox, (uint32_t)mptr, osWaitForever); // Send Message
+
osThreadYield(); // Cooperative multitasking
+
// We are done here, exit this thread
+
}
+
+
/*
+
Thread 2: Receive thread
+
*/
+
void recv_thread (void const *argument) {
+
T_MEAS *rptr;
+
osEvent evt;
+
+
for (;;) {
+
evt = osMessageGet(MsgBox, osWaitForever); // wait for message
+
if (evt.status == osEventMessage) {
+
rptr = evt.value.p;
+
printf ("\nVoltage: %.2f V\n", rptr->voltage);
+
printf ("Current: %.2f A\n", rptr->current);
+
printf ("Number of cycles: %d\n", rptr->counter);
+
osPoolFree(mpool, rptr); // free memory allocated for message
+
}
+
}
+
}
+
+
void StartApplication (void) {
+
mpool = osPoolCreate(osPool(mpool)); // create memory pool
+
MsgBox = osMessageCreate(osMessageQ(MsgBox), NULL); // create msg queue
+
+
tid_thread1 = osThreadCreate(osThread(send_thread), NULL);
+
tid_thread2 = osThreadCreate(osThread(recv_thread), NULL);
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osEvent osMessageGet (osMessageQId queue_id,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]queue_idmessage queue ID obtained with osMessageCreate.
[in]millisectimeout value or 0 in case of no time-out.
+
+
+
Returns
event information that includes status code.
+
Note
MUST REMAIN UNCHANGED: osMessageGet shall be consistent in every CMSIS-RTOS.
+

Suspend the execution of the current RUNNING thread until a message arrives. When a message is already in the queue, the function returns instantly with the message information.

+

The argument millisec specifies how long the system waits for a message to become available. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout value can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until a message arrives.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+
Note
The parameter millisec must be 0 for using this function in an ISR.
+

Status and Error Codes
+

+
    +
  • osOK: no message is available in the queue and no timeout was specified.
    • +
  • osEventTimeout: no message has arrived during the given timeout period.
    • +
  • osEventMessage: message received, value.p contains the pointer to message.
    • +
  • osErrorParameter: a parameter is invalid or outside of a permitted range.
    • +
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
osStatus osMessagePut (osMessageQId queue_id,
uint32_t info,
uint32_t millisec 
)
+
+
Parameters
+ + + + +
[in]queue_idmessage queue ID obtained with osMessageCreate.
[in]infomessage information.
[in]millisectimeout value or 0 in case of no time-out.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osMessagePut shall be consistent in every CMSIS-RTOS.
+

Put the message info in a message queue specified by queue_id.

+

When the message queue is full, the system retries for a specified time with millisec. While the system retries the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until a message queue slot becomes available.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+
Note
The parameter millisec must be 0 for using this function in an ISR.
+

Status and Error Codes
+

+
    +
  • osOK: the message is put into the queue.
    • +
  • osErrorResource: no memory in the queue was available.
    • +
  • osErrorTimeoutResource: no memory in the queue was available during the given time limit.
    • +
  • osErrorParameter: a parameter is invalid or outside of a permitted range.
    • +
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.js new file mode 100644 index 000000000..38de1fab8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.js @@ -0,0 +1,9 @@ +var group___c_m_s_i_s___r_t_o_s___message = +[ + [ "osFeature_MessageQ", "group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203", null ], + [ "osMessageQ", "group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97", null ], + [ "osMessageQDef", "group___c_m_s_i_s___r_t_o_s___message.html#gac9a6a6276c12609793e7701afcc82326", null ], + [ "osMessageCreate", "group___c_m_s_i_s___r_t_o_s___message.html#gaf3b9345cf426304d46565152bc26fb78", null ], + [ "osMessageGet", "group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae", null ], + [ "osMessagePut", "group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html new file mode 100644 index 000000000..844f53617 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html @@ -0,0 +1,421 @@ + + + + + +CMSIS-RTOS: Mutex Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Mutex Management
CMSIS-RTOS API
+
+
+ +

Synchronize thread execution with a Mutex. +More...

+ + + + + + + + +

+Macros

#define osMutexDef(name)   const osMutexDef_t os_mutex_def_##name = { 0 }
 Define a Mutex. More...
 
#define osMutex(name)   &os_mutex_def_##name
 Access a Mutex definition. More...
 
+ + + + + + + + + + + + + +

+Functions

osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
 Create and Initialize a Mutex object. More...
 
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
 Wait until a Mutex becomes available. More...
 
osStatus osMutexRelease (osMutexId mutex_id)
 Release a Mutex that was obtained by osMutexWait. More...
 
osStatus osMutexDelete (osMutexId mutex_id)
 Delete a Mutex that was created by osMutexCreate. More...
 
+

Description

+

The Mutex Management function group is used to synchronize the execution of threads. This is for example used to protect access to a shared resource, for example a shared memory image.

+
Note
Mutex Management functions cannot be called from interrupt service routines (ISR).
+
+Mutex.png +
+CMSIS-RTOS Mutex
+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define osMutex( name)   &os_mutex_def_##name
+
+

Access to mutex object for the functions osMutexCreate.

+
Parameters
+ + +
namename of the mutex object.
+
+
+
Note
CAN BE CHANGED: The parameter to osMutex shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + + + + + +
#define osMutexDef( name)   const osMutexDef_t os_mutex_def_##name = { 0 }
+
+

Define a mutex object that is referenced by osMutex.

+
Parameters
+ + +
namename of the mutex object.
+
+
+
Note
CAN BE CHANGED: The parameter to osMutexDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
osMutexId osMutexCreate (const osMutexDef_t * mutex_def)
+
+
Parameters
+ + +
[in]mutex_defmutex definition referenced with osMutex.
+
+
+
Returns
mutex ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osMutexCreate shall be consistent in every CMSIS-RTOS.
+

Create and initialize a Mutex object.

+

Example

+
#include "cmsis_os.h"
+
+
osMutexDef (MutexIsr); // Mutex name definition
+
+
void CreateMutex (void) {
+
osMutexId mutex_id;
+
+
mutex_id = osMutexCreate (osMutex (MutexIsr));
+
if (mutex_id != NULL) {
+
// Mutex object created
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osMutexDelete (osMutexId mutex_id)
+
+
Parameters
+ + +
[in]mutex_idmutex ID obtained by osMutexCreate.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osMutexDelete shall be consistent in every CMSIS-RTOS.
+

Delete a Mutex object. The function releases internal memory obtained for Mutex handling. After this call the mutex_id is no longer valid and cannot be used. The Mutex may be created again using the function osMutexCreate.

+

Status and Error Codes
+

+
    +
  • osOK: the mutex object has been deleted.
    • +
  • osErrorISR: osMutexDelete cannot be called from interrupt service routines.
    • +
  • osErrorResource: all tokens have already been released.
    • +
  • osErrorParameter: the parameter mutex_id is incorrect.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
osMutexDef (MutexIsr); // Mutex name definition
+
osMutexId mutex_id; // Mutex id populated by the function CreateMutex()
+
osMutexId CreateMutex (void); // function prototype that creates the Mutex
+
+
void DeleteMutex (osMutexId mutex_id) {
+
osStatus status;
+
+
if (mutex_id != NULL) {
+
status = osMutexDelete(mutex_id);
+
if (status != osOK) {
+
// handle failure code
+
}
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osMutexRelease (osMutexId mutex_id)
+
+
Parameters
+ + +
[in]mutex_idmutex ID obtained by osMutexCreate.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osMutexRelease shall be consistent in every CMSIS-RTOS.
+

Release a Mutex that was obtained with osMutexWait. Other threads that currently wait for the same mutex will be now put into the state READY.

+

Status and Error Codes
+

+
    +
  • osOK: the mutex has been correctly released.
    • +
  • osErrorResource: the mutex was not obtained before.
    • +
  • osErrorParameter: the parameter mutex_id is incorrect.
    • +
  • osErrorISR: osMutexRelease cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
osMutexDef (MutexIsr); // Mutex name definition
+
osMutexId mutex_id; // Mutex id populated by the function CreateMutex()
+
osMutexId CreateMutex (void); // function prototype that creates the Mutex
+
+
void ReleaseMutex (osMutexId mutex_id) {
+
osStatus status;
+
+
if (mutex_id != NULL) {
+
status = osMutexRelease(mutex_id);
+
if (status != osOK) {
+
// handle failure code
+
}
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osStatus osMutexWait (osMutexId mutex_id,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]mutex_idmutex ID obtained by osMutexCreate.
[in]millisectimeout value or 0 in case of no time-out.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osMutexWait shall be consistent in every CMSIS-RTOS.
+

Wait until a Mutex becomes available. If no other thread has obtained the Mutex, the function instantly returns and blocks the mutex object.

+

The argument millisec specifies how long the system waits for a mutex. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until the mutex becomes available.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+

Status and Error Codes
+

+
    +
  • osOK: the mutex has been obtain.
    • +
  • osErrorTimeoutResource: the mutex could not be obtained in the given time.
    • +
  • osErrorResource: the mutex could not be obtained when no timeout was specified.
    • +
  • osErrorParameter: the parameter mutex_id is incorrect.
    • +
  • osErrorISR: osMutexWait cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
osMutexDef (MutexIsr);
+
+
void WaitMutex (void) {
+
osMutexId mutex_id;
+
osStatus status;
+
+
mutex_id = osMutexCreate (osMutex (MutexIsr));
+
if (mutex_id != NULL) {
+
status = osMutexWait (mutex_id, 0);
+
if (status != osOK) {
+
// handle failure code
+
}
+
}
+
}
+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.js new file mode 100644 index 000000000..1587dca9d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.js @@ -0,0 +1,9 @@ +var group___c_m_s_i_s___r_t_o_s___mutex_mgmt = +[ + [ "osMutex", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934", null ], + [ "osMutexDef", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga9b522438489d7c402c95332b58bc94f3", null ], + [ "osMutexCreate", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5c9de56e717016e39e788064e9a291cc", null ], + [ "osMutexDelete", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#gac27e24135185d51d18f3dabc20910219", null ], + [ "osMutexRelease", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1", null ], + [ "osMutexWait", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html new file mode 100644 index 000000000..a20ed60b3 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html @@ -0,0 +1,464 @@ + + + + + +CMSIS-RTOS: Memory Pool Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Memory Pool Management
CMSIS-RTOS API
+
+
+ +

Define and manage fixed-size memory pools. +More...

+ + + + + + + + + + + +

+Macros

#define osFeature_Pool   1
 Memory Pools: 1=available, 0=not available. More...
 
#define osPoolDef(name, no, type)
 Define a Memory Pool. More...
 
#define osPool(name)   &os_pool_def_##name
 Access a Memory Pool definition. More...
 
+ + + + + + + + + + + + + +

+Functions

osPoolId osPoolCreate (const osPoolDef_t *pool_def)
 Create and Initialize a memory pool. More...
 
void * osPoolAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool. More...
 
void * osPoolCAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool and set memory block to zero. More...
 
osStatus osPoolFree (osPoolId pool_id, void *block)
 Return an allocated memory block back to a specific memory pool. More...
 
+

Description

+

The Memory Pool Management function group is used to define and manage fixed-sized memory pools.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define osFeature_Pool   1
+
+

A CMSIS-RTOS implementation may support fixed-size memory pools.

+ + +
+
+ +
+
+ + + + + + + + +
#define osPool( name)   &os_pool_def_##name
+
+

Access a memory pool for the functions osPoolCreate.

+
Parameters
+ + +
namename of the memory pool
+
+
+
Note
CAN BE CHANGED: The parameter to osPool shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define osPoolDef( name,
 no,
 type 
)
+
+

Define a memory pool that is referenced by osPool.

+
Parameters
+ + + + +
namename of the memory pool.
nomaximum number of blocks (objects) in the memory pool.
typedata type of a single block (object).
+
+
+
Note
CAN BE CHANGED: The parameter to osPoolDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void * osPoolAlloc (osPoolId pool_id)
+
+
Parameters
+ + +
[in]pool_idmemory pool ID obtain referenced with osPoolCreate.
+
+
+
Returns
address of the allocated memory block or NULL in case of no memory available.
+
Note
MUST REMAIN UNCHANGED: osPoolAlloc shall be consistent in every CMSIS-RTOS.
+

Allocate a memory block from the memory pool.

+

Example

+
#include "cmsis_os.h"
+
+
typedef struct {
+
uint8_t Buf[32];
+
uint8_t Idx;
+
} MEM_BLOCK;
+
+
osPoolDef (MemPool, 8, MEM_BLOCK);
+
+
void AlocMemoryPoolBlock (void) {
+
osPoolId MemPool_Id;
+
MEM_BLOCK *addr;
+
+
MemPool_Id = osPoolCreate (osPool (MemPool));
+
if (MemPool_Id != NULL) {
+
:
+
// allocate a memory block
+
addr = (MEM_BLOCK *)osPoolAlloc (MemPool_Id);
+
+
if (addr != NULL) {
+
// memory block was allocated
+
:
+
}
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
void * osPoolCAlloc (osPoolId pool_id)
+
+
Parameters
+ + +
[in]pool_idmemory pool ID obtain referenced with osPoolCreate.
+
+
+
Returns
address of the allocated memory block or NULL in case of no memory available.
+
Note
MUST REMAIN UNCHANGED: osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+

Allocate a memory block from the memory pool. The block is initialized to zero.

+

Example

+
#include "cmsis_os.h"
+
+
typedef struct {
+
uint8_t Buf[32];
+
uint8_t Idx;
+
} MEM_BLOCK;
+
+
osPoolDef (MemPool, 8, MEM_BLOCK);
+
+
void CAlocMemoryPoolBlock (void) {
+
osPoolId MemPool_Id;
+
MEM_BLOCK *addr;
+
+
MemPool_Id = osPoolCreate (osPool (MemPool));
+
if (MemPool_Id != NULL) {
+
:
+
// allocate a memory block
+
addr = (MEM_BLOCK *)osPoolCAlloc (MemPool_Id);
+
+
if (addr != NULL) {
+
// memory block was allocated
+
:
+
}
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
osPoolId osPoolCreate (const osPoolDef_t * pool_def)
+
+
Parameters
+ + +
[in]pool_defmemory pool definition referenced with osPool.
+
+
+
Returns
memory pool ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osPoolCreate shall be consistent in every CMSIS-RTOS.
+

Create and initialize a memory pool.

+

Example

+
#include "cmsis_os.h"
+
+
typedef struct {
+
uint8_t Buf[32];
+
uint8_t Idx;
+
} MEM_BLOCK;
+
+
osPoolDef (MemPool, 8, MEM_BLOCK);
+
+
void CreateMemoryPool (void) {
+
osPoolId MemPool_Id;
+
+
MemPool_Id = osPoolCreate (osPool (MemPool));
+
if (MemPool_Id != NULL) {
+
// memory pool created
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osStatus osPoolFree (osPoolId pool_id,
void * block 
)
+
+
Parameters
+ + + +
[in]pool_idmemory pool ID obtain referenced with osPoolCreate.
[in]blockaddress of the allocated memory block that is returned to the memory pool.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osPoolFree shall be consistent in every CMSIS-RTOS.
+

Return a memory block to a memory pool.

+

Status and Error Codes
+

+
    +
  • osOK: the memory block is released.
    • +
  • osErrorValue: block does not belong to the memory pool.
    • +
  • osErrorParameter: a parameter is invalid or outside of a permitted range.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
typedef struct {
+
uint8_t Buf[32];
+
uint8_t Idx;
+
} MEM_BLOCK;
+
+
osPoolDef (MemPool, 8, MEM_BLOCK);
+
+
void CAlocMemoryPoolBlock (void) {
+
osPoolId MemPool_Id;
+
MEM_BLOCK *addr;
+
osStatus status;
+
+
MemPool_Id = osPoolCreate (osPool (MemPool));
+
if (MemPool_Id != NULL) {
+
addr = (MEM_BLOCK *)osPoolCAlloc (MemPool_Id);
+
if (addr != NULL) {
+
:
+
// return a memory block back to pool
+
status = osPoolFree (MemPool_Id, addr);
+
if (status==osOK) {
+
// handle status code
+
}
+
}
+
}
+
}
+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.js new file mode 100644 index 000000000..51d5079a7 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.js @@ -0,0 +1,10 @@ +var group___c_m_s_i_s___r_t_o_s___pool_mgmt = +[ + [ "osFeature_Pool", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa", null ], + [ "osPool", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697", null ], + [ "osPoolDef", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga87b471d4fe2d5dbd0040708edd52771b", null ], + [ "osPoolAlloc", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543", null ], + [ "osPoolCAlloc", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a", null ], + [ "osPoolCreate", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga34af5c4f4ab38f4138ea7f1f9ece3a1a", null ], + [ "osPoolFree", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html new file mode 100644 index 000000000..9d6a129cd --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html @@ -0,0 +1,426 @@ + + + + + +CMSIS-RTOS: Semaphore Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Semaphore Management
CMSIS-RTOS API
+
+
+ +

Control access to shared resources. +More...

+ + + + + + + + + + + +

+Macros

#define osFeature_Semaphore   30
 maximum count for osSemaphoreCreate function More...
 
#define osSemaphoreDef(name)   const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 Define a Semaphore object. More...
 
#define osSemaphore(name)   &os_semaphore_def_##name
 Access a Semaphore definition. More...
 
+ + + + + + + + + + + + + +

+Functions

osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
 Create and Initialize a Semaphore object used for managing resources. More...
 
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
 Wait until a Semaphore token becomes available. More...
 
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
 Release a Semaphore token. More...
 
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
 Delete a Semaphore that was created by osSemaphoreCreate. More...
 
+

Description

+

The Semaphore Management function group is used to manage and protect access to shared resources. For example, with a Semaphore the access to a group of identical peripherals can be managed. The number of available resources is specified as parameter of the osSemaphoreCreate function.

+

Each time a Semaphore token is obtained with osSemaphoreWait the semaphore count is decremented. When the semaphore count is 0, no Semaphore token can be obtained. Semaphores are released with osSemaphoreRelease; this function increments the semaphore count.

+
+Semaphore.png +
+CMSIS-RTOS Semaphore
+

Macro Definition Documentation

+ +
+
+ + + + +
#define osFeature_Semaphore   30
+
+

A CMSIS-RTOS implementation may support semaphores. The value osFeature_Semaphore indicates the maximum index count for a semaphore.

+ +
+
+ +
+
+ + + + + + + + +
#define osSemaphore( name)   &os_semaphore_def_##name
+
+

Access to semaphore object for the functions osSemaphoreCreate.

+
Parameters
+ + +
namename of the semaphore object.
+
+
+
Note
CAN BE CHANGED: The parameter to osSemaphore shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + + + + + +
#define osSemaphoreDef( name)   const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+
+

Define a semaphore object that is referenced by osSemaphore.

+
Parameters
+ + +
namename of the semaphore object.
+
+
+
Note
CAN BE CHANGED: The parameter to osSemaphoreDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t * semaphore_def,
int32_t count 
)
+
+
Parameters
+ + + +
[in]semaphore_defsemaphore definition referenced with osSemaphore.
[in]countnumber of available resources.
+
+
+
Returns
semaphore ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+

Create and initialize a Semaphore object that is used to manage access to shared resources. The parameter count specifies the number of available resources. The count value 1 creates a binary semaphore.

+

Example

+
#include "cmsis_os.h"
+
+
osThreadId tid_thread1; // ID for thread 1
+
osThreadId tid_thread2; // ID for thread 2
+
+
osSemaphoreId semaphore; // Semaphore ID
+
osSemaphoreDef(semaphore); // Semaphore definition
+
+
/*
+
Thread 1 - High Priority - Active every 3ms
+
*/
+
void thread1 (void const *argument) {
+
int32_t value;
+
+
while (1) {
+
osDelay(3); // Pass control to other tasks for 3ms
+
val = osSemaphoreWait (semaphore, 1); // Wait 1ms for the free semaphore
+
if (val > 0) {
+
// If there was no time-out the semaphore was acquired
+
: // OK, the interface is free now, use it.
+
osSemaphoreRelease (semaphore); // Return a token back to a semaphore
+
}
+
}
+
}
+
+
/*
+
Thread 2 - Normal Priority - looks for a free semaphore and uses
+
the resource whenever it is available
+
*/
+
void thread2 (void const *argument) {
+
while (1) {
+
osSemaphoreWait (semaphore, osWaitForever); // Wait indefinitely for a free semaphore
+
// OK, the interface is free now, use it.
+
:
+
osSemaphoreRelease (semaphore); // Return a token back to a semaphore.
+
}
+
}
+
+
/* Thread definitions */
+
osThreadDef(thread1, osPriorityHigh, 1, 0);
+
osThreadDef(thread2, osPriorityNormal, 1, 0);
+
+
void StartApplication (void) {
+
semaphore = osSemaphoreCreate(osSemaphore(semaphore), 1);
+
+
tid_thread1 = osThreadCreate(osThread(thread1), NULL);
+
tid_thread2 = osThreadCreate(osThread(thread2), NULL);
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
+
+
Parameters
+ + +
[in]semaphore_idsemaphore object referenced with osSemaphoreCreate.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+

Delete a Semaphore object. The function releases internal memory obtained for Semaphore handling. After this call the semaphore_id is no longer valid and cannot be used. The Semaphore may be created again using the function osSemaphoreCreate.

+

Status and Error Codes
+

+
    +
  • osOK: the semaphore object has been deleted.
    • +
  • osErrorISR: osSemaphoreDelete cannot be called from interrupt service routines.
    • +
  • osErrorResource: the semaphore object could not be deleted.
    • +
  • osErrorParameter: the parameter semaphore_id is incorrect.
    • +
+ +
+
+ +
+
+ + + + + + + + +
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
+
+
Parameters
+ + +
[in]semaphore_idsemaphore object referenced with osSemaphoreCreate.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+

Release a Semaphore token. This increments the count of available semaphore tokens.

+
Note
osSemaphoreRelease can be called also from interrupt service routines.
+

Status and Error Codes
+

+
    +
  • osOK: the semaphore has been released.
    • +
  • osErrorResource: all tokens have already been released.
    • +
  • osErrorParameter: the parameter semaphore_id is incorrect.
    • +
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int32_t osSemaphoreWait (osSemaphoreId semaphore_id,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]semaphore_idsemaphore object referenced with osSemaphoreCreate.
[in]millisectimeout value or 0 in case of no time-out.
+
+
+
Returns
number of available tokens, or -1 in case of incorrect parameters.
+
Note
MUST REMAIN UNCHANGED: osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+

Wait until a Semaphore token becomes available. When no Semaphore token is available, the function waits for the time specified with the parameter millisec.

+

The argument millisec specifies how long the system waits for a Semaphore token to become available. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until the Semaphore token becomes available.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+

The return value indicates the number of available tokens (the semaphore count value). If 0 is returned, then no semaphore was available.

+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.js new file mode 100644 index 000000000..cb194a85c --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.js @@ -0,0 +1,10 @@ +var group___c_m_s_i_s___r_t_o_s___semaphore_mgmt = +[ + [ "osFeature_Semaphore", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a", null ], + [ "osSemaphore", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac", null ], + [ "osSemaphoreDef", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b", null ], + [ "osSemaphoreCreate", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga97381e8e55cd47cec390bf57c96d6edb", null ], + [ "osSemaphoreDelete", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gabae2801ac2c096f6e8c69a264908f595", null ], + [ "osSemaphoreRelease", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0", null ], + [ "osSemaphoreWait", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html new file mode 100644 index 000000000..6c8ceeeaf --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html @@ -0,0 +1,350 @@ + + + + + +CMSIS-RTOS: Signal Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Signal Management
CMSIS-RTOS API
+
+
+ +

Control or wait for signal flags. +More...

+ + + + + +

+Macros

#define osFeature_Signals   8
 maximum number of Signal Flags available per thread More...
 
+ + + + + + + + + + +

+Functions

int32_t osSignalSet (osThreadId thread_id, int32_t signals)
 Set the specified Signal Flags of an active thread. More...
 
int32_t osSignalClear (osThreadId thread_id, int32_t signals)
 Clear the specified Signal Flags of an active thread. More...
 
osEvent osSignalWait (int32_t signals, uint32_t millisec)
 Wait for one or more Signal Flags to become signaled for the current RUNNING thread. More...
 
+

Description

+

The Signal Management function group allows to control or wait signal flags. Each thread has assigned signal flags.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define osFeature_Signals   8
+
+

The CMSIS-RTOS API may support a variable number of signal flags. This define specifies the number of signal flags available per thread. The maximum value is 31 signal flags per thread.

+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
int32_t osSignalClear (osThreadId thread_id,
int32_t signals 
)
+
+
Parameters
+ + + +
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
[in]signalsspecifies the signal flags of the thread that shall be cleared.
+
+
+
Returns
previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+
Note
MUST REMAIN UNCHANGED: osSignalClear shall be consistent in every CMSIS-RTOS.
+

Clear the signal flags of an active thread. This function may be used also within interrupt service routines.

+

Example

+
void Thread_2 (void const *arg);
+
+
osThreadDef (Thread_2, osPriorityHigh, 1, 0);
+
+
static void EX_Signal_1 (void) {
+
int32_t signals;
+
osThreadId thread_id;
+
+
thread_id = osThreadCreate (osThread(Thread_2), NULL);
+
if (thread_id == NULL) {
+
// Failed to create a thread.
+
}
+
else {
+
f :
+
signals = osSignalClear (thread_id, 0x01);
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int32_t osSignalSet (osThreadId thread_id,
int32_t signals 
)
+
+
Parameters
+ + + +
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
[in]signalsspecifies the signal flags of the thread that should be set.
+
+
+
Returns
previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+
Note
MUST REMAIN UNCHANGED: osSignalSet shall be consistent in every CMSIS-RTOS.
+

Set the signal flags of an active thread. This function may be used also within interrupt service routines.

+

Example

+
void Thread_2 (void const *arg);
+
+
osThreadDef (Thread_2, osPriorityHigh, 1, 0);
+
+
static void EX_Signal_1 (void) {
+
int32_t signals;
+
uint32_t exec;
+
osThreadId thread_id;
+
+
thread_id = osThreadCreate (osThread(Thread_2), NULL);
+
if (thread_id == NULL) {
+
// Failed to create a thread.
+
}
+
else {
+
signals = osSignalSet (thread_id, 0x00000005); // Send signals to the created thread
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osEvent osSignalWait (int32_t signals,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]signalswait until all specified signal flags set or 0 for any single signal flag.
[in]millisectimeout value or 0 in case of no time-out.
+
+
+
Returns
event flag information or error code.
+
Note
MUST REMAIN UNCHANGED: osSignalWait shall be consistent in every CMSIS-RTOS.
+

Suspend the execution of the current RUNNING thread until all specified signal flags with the parameter signals are set. When this signal flags are already set, the function returns instantly. Otherwise the thread is put into the state WAITING. Signal flags that are reported as event are automatically cleared.

+

The argument millisec specifies how long the system waits for the specified signal flags. While the system waits the tread calling this function is put into the state WAITING. The timeout value can have the following values:

+
    +
  • when millisec is 0, the function returns instantly.
    • +
  • when millisec is set to osWaitForever the function will wait for an infinite time until a specified signal is set.
    • +
  • all other values specify a time in millisecond for a timeout.
    • +
+

Status and Error Codes
+

+
    +
  • osOK: no signal received when the timeout value millisec was 0.
    • +
  • osEventTimeout: signal not occurred within timeout
    • +
  • osEventSignal: signal occurred, value.signals contains the signal flags; these signal flags are cleared.
    • +
  • osErrorValue: the value signals is outside of the permitted range.
    • +
  • osErrorISR: osSignalWait cannot be called from interrupt service routines.
    • +
+

Example

+
void Thread_2 (void const *arg);
+
+
osThreadDef (Thread_2, osPriorityHigh, 1, 0);
+
+
static void EX_Signal_1 (void) {
+
osThreadId thread_id;
+
osEvent evt;
+
+
thread_id = osThreadCreate (osThread(Thread_2), NULL);
+
if (thread_id == NULL) {
+
// Failed to create a thread.
+
}
+
else {
+
:
+
// wait for a signal
+
evt = osSignalWait (0x01, 100);
+
if (evt.status == osEventSignal) {
+
// handle event status
+
}
+
}
+
}
+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.js new file mode 100644 index 000000000..825b993e1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.js @@ -0,0 +1,7 @@ +var group___c_m_s_i_s___r_t_o_s___signal_mgmt = +[ + [ "osFeature_Signals", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga01edde265710d883b6e237d34a6ef4a6", null ], + [ "osSignalClear", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga87283a6ebc31ce9ed42baf3ea7e4eab6", null ], + [ "osSignalSet", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga3de2730654589d6c3559c4b9e2825553", null ], + [ "osSignalWait", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html new file mode 100644 index 000000000..2ffc187e5 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html @@ -0,0 +1,233 @@ + + + + + +CMSIS-RTOS: Status and Error Codes + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Enumerations
+
+
Status and Error Codes
CMSIS-RTOS API
+
+
+ +

Status and Error Codes returned by CMSIS-RTOS API functions. +More...

+ + + + +

+Enumerations

enum  osStatus {
+  osOK = 0, +
+  osEventSignal = 0x08, +
+  osEventMessage = 0x10, +
+  osEventMail = 0x20, +
+  osEventTimeout = 0x40, +
+  osErrorParameter = 0x80, +
+  osErrorResource = 0x81, +
+  osErrorTimeoutResource = 0xC1, +
+  osErrorISR = 0x82, +
+  osErrorISRRecursive = 0x83, +
+  osErrorPriority = 0x84, +
+  osErrorNoMemory = 0x85, +
+  osErrorValue = 0x86, +
+  osErrorOS = 0xFF, +
+  os_status_reserved = 0x7FFFFFFF +
+ }
 
+

Description

+

The Status and Error Codes section lists all the return values that the CMSIS-RTOS functions will return.

+

Enumeration Type Documentation

+ +
+
+ + + + +
enum osStatus
+
+
Note
MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS.
+

The osStatus enumeration defines the event status and error codes that are returned by the CMSIS-RTOS functions.

+ + + + + + + + + + + + + + + + +
Enumerator
osOK  +

function completed; no error or event occurred.

+
osEventSignal  +

function completed; signal event occurred.

+
osEventMessage  +

function completed; message event occurred.

+
osEventMail  +

function completed; mail event occurred.

+
osEventTimeout  +

function completed; timeout occurred.

+
osErrorParameter  +

parameter error: a mandatory parameter was missing or specified an incorrect object.

+
osErrorResource  +

resource not available: a specified resource was not available.

+
osErrorTimeoutResource  +

resource not available within given time: a specified resource was not available within the timeout period.

+
osErrorISR  +

not allowed in ISR context: the function cannot be called from interrupt service routines.

+
osErrorISRRecursive  +

function called multiple times from ISR with same object.

+
osErrorPriority  +

system cannot determine priority or thread has illegal priority.

+
osErrorNoMemory  +

system is out of memory: it was impossible to allocate or reserve memory for the operation.

+
osErrorValue  +

value of a parameter is out of range.

+
osErrorOS  +

unspecified RTOS error: run-time error but no other error message fits.

+
os_status_reserved  +

prevent from enum down-size compiler optimization.

+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.js new file mode 100644 index 000000000..a89063698 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.js @@ -0,0 +1,20 @@ +var group___c_m_s_i_s___r_t_o_s___status = +[ + [ "osStatus", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e", [ + [ "osOK", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f", null ], + [ "osEventSignal", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518", null ], + [ "osEventMessage", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342", null ], + [ "osEventMail", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926", null ], + [ "osEventTimeout", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177", null ], + [ "osErrorParameter", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109", null ], + [ "osErrorResource", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d", null ], + [ "osErrorTimeoutResource", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467", null ], + [ "osErrorISR", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f", null ], + [ "osErrorISRRecursive", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65", null ], + [ "osErrorPriority", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f", null ], + [ "osErrorNoMemory", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81", null ], + [ "osErrorValue", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee", null ], + [ "osErrorOS", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc", null ], + [ "os_status_reserved", "group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1", null ] + ] ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html new file mode 100644 index 000000000..defeeb2d1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html @@ -0,0 +1,607 @@ + + + + + +CMSIS-RTOS: Thread Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Enumerations | +Functions
+
+
Thread Management
CMSIS-RTOS API
+
+
+ +

Define, create, and control thread functions. +More...

+ + + + + + + + +

+Macros

#define osThreadDef(name, priority, instances, stacksz)
 Create a Thread Definition with function, priority, and stack requirements. More...
 
#define osThread(name)   &os_thread_def_##name
 Access a Thread definition. More...
 
+ + + +

+Enumerations

enum  osPriority {
+  osPriorityIdle = -3, +
+  osPriorityLow = -2, +
+  osPriorityBelowNormal = -1, +
+  osPriorityNormal = 0, +
+  osPriorityAboveNormal = +1, +
+  osPriorityHigh = +2, +
+  osPriorityRealtime = +3, +
+  osPriorityError = 0x84 +
+ }
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
 Create a thread and add it to Active Threads and set it to state READY. More...
 
osThreadId osThreadGetId (void)
 Return the thread ID of the current running thread. More...
 
osStatus osThreadTerminate (osThreadId thread_id)
 Terminate execution of a thread and remove it from Active Threads. More...
 
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
 Change priority of an active thread. More...
 
osPriority osThreadGetPriority (osThreadId thread_id)
 Get current priority of an active thread. More...
 
osStatus osThreadYield (void)
 Pass control to next thread that is in state READY. More...
 
+

Description

+

The Thread Management function group allow defining, creating, and controlling thread functions in the system. The function main is a special thread function that is started at system initialization and has the initial priority osPriorityNormal.

+

Threads can be in the following states:

+
    +
  • RUNNING: The thread that is currently running is in the RUNNING state. Only one thread at a time can be in this state.
    • +
  • READY: Threads which are ready to run are in the READY state. Once the RUNNING thread has terminated or is WAITING the next READY thread with the highest priority becomes the RUNNING thread.
    • +
  • WAITING: Threads that are waiting for an event to occur are in the WAITING state.
    • +
  • INACTIVE: Threads that are not created or terminated are in the INACTIVE state. These threads typically consume no system resources.
    • +
+
+ThreadStatus.png +
+Thread State and State Transitions
+

The CMSIS-RTOS assumes that threads are scheduled as shown in the figure Thread State and State Transitions. The thread states change as described below:

+
    +
  • A thread is created using the function osThreadCreate. This puts the thread into the READY or RUNNING state (depending on the thread priority).
    • +
  • CMSIS-RTOS is pre-emptive. The active thread with the highest priority becomes the RUNNING thread provided it does not wait for any event. The initial priority of a thread is defined with the osThreadDef but may be changed during execution using the function osThreadSetPriority.
    • +
  • The RUNNING thread transfers into the WAITING state when it is waiting for an event.
    • +
  • Active threads can be terminated any time using the function osThreadTerminate. Threads can terminate also by just returning from the thread function. Threads that are terminated are in the INACTIVE state and typically do not consume any dynamic memory resources.
    • +
+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define osThread( name)   &os_thread_def_##name
+
+

Access to the thread definition for the function osThreadCreate.

+
Parameters
+ + +
namename of the thread definition object.
+
+
+
Note
CAN BE CHANGED: The parameter to osThread shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define osThreadDef( name,
 priority,
 instances,
 stacksz 
)
+
+

Define the attributes of a thread functions that can be created by the function osThreadCreate using osThread.

+
Parameters
+ + + + + +
namename of the thread function.
priorityinitial priority of the thread function.
instancesnumber of possible thread instances.
stackszstack size (in bytes) requirements for the thread function.
+
+
+
Note
CAN BE CHANGED: The parameters to osThreadDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum osPriority
+
+
Note
MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS.
+

The osPriority value specifies the priority for a thread. The default thread priority should be osPriorityNormal. If a Thread is active that has a higher priority than the currently executing thread, then a thread switch occurs immediately to execute the new task.

+

To prevent from a priority inversion, a CMSIS-RTOS complained OS may optionally implement a priority inheritance method. A priority inversion occurs when a high priority thread is waiting for a resource or event that is controlled by a thread with a lower priority.

+ + + + + + + + + +
Enumerator
osPriorityIdle  +

priority: idle (lowest)

+
osPriorityLow  +

priority: low

+
osPriorityBelowNormal  +

priority: below normal

+
osPriorityNormal  +

priority: normal (default)

+
osPriorityAboveNormal  +

priority: above normal

+
osPriorityHigh  +

priority: high

+
osPriorityRealtime  +

priority: realtime (highest)

+
osPriorityError  +

system cannot determine priority or thread has illegal priority

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
osThreadId osThreadCreate (const osThreadDef_t * thread_def,
void * argument 
)
+
+
Parameters
+ + + +
[in]thread_defthread definition referenced with osThread.
[in]argumentpointer that is passed to the thread function as start argument.
+
+
+
Returns
thread ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osThreadCreate shall be consistent in every CMSIS-RTOS.
+

Start a thread function by adding it to the Active Threads list and set it to state READY. The thread function receives the argument pointer as function argument when the function is started. When the priority of the created thread function is higher than the current RUNNING thread, the created thread function starts instantly and becomes the new RUNNING thread.

+

Example

+
#include "cmsis_os.h"
+
+
void Thread_1 (void const *arg); // function prototype for Thread_1
+
osThreadDef (Thread_1, osPriorityNormal, 1, 0); // define Thread_1
+
+
void ThreadCreate_example (void) {
+
osThreadId id;
+
+
id = osThreadCreate (osThread (Thread_1), NULL); // create the thread
+
if (id == NULL) { // handle thread creation
+
// Failed to create a thread
+
}
+
:
+
osThreadTerminate (id); // stop the thread
+
}
+
+
+
+ +
+
+ + + + + + + + +
osThreadId osThreadGetId (void )
+
+
Returns
thread ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osThreadGetId shall be consistent in every CMSIS-RTOS.
+

Get the thread ID of the current running thread.

+

Example

+
void ThreadGetId_example (void) {
+
osThreadId id; // id for the currently running thread
+
+
id = osThreadGetId ();
+
if (id == NULL) {
+
// Failed to get the id; not in a thread
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
osPriority osThreadGetPriority (osThreadId thread_id)
+
+
Parameters
+ + +
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
+
+
+
Returns
current priority value of the thread function.
+
Note
MUST REMAIN UNCHANGED: osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+

Get the priority of an active thread. In case of a failure the value osPriorityError is returned.

+

Example

+
#include "cmsis_os.h"
+
+
void Thread_1 (void const *arg) { // Thread function
+
osThreadId id; // id for the currently running thread
+
osPriority priority; // thread priority
+
+
id = osThreadGetId (); // Obtain ID of current running thread
+
+
if (id != NULL) {
+
priority = osThreadGetPriority (id);
+
}
+
else {
+
// Failed to get the id
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osStatus osThreadSetPriority (osThreadId thread_id,
osPriority priority 
)
+
+
Parameters
+ + + +
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
[in]prioritynew priority value for the thread function.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+

Change the priority of an active thread.

+

Status and Error Codes
+

+
    +
  • osOK: the priority of the specified thread has been successfully changed.
    • +
  • osErrorParameter: thread_id is incorrect.
    • +
  • osErrorValue: incorrect priority value.
    • +
  • osErrorResource: thread_id refers to a thread that is not an active thread.
    • +
  • osErrorISR: osThreadSetPriority cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Thread_1 (void const *arg) { // Thread function
+
osThreadId id; // id for the currently running thread
+
osPriority pr; // thread priority
+
osStatus status; // status of the executed function
+
+
:
+
id = osThreadGetId (); // Obtain ID of current running thread
+
+
if (id != NULL) {
+
status = osThreadSetPriority (id, osPriorityBelowNormal);
+
if (status == osOK) {
+
// Thread priority changed to BelowNormal
+
}
+
else {
+
// Failed to set the priority
+
}
+
}
+
else {
+
// Failed to get the id
+
}
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osThreadTerminate (osThreadId thread_id)
+
+
Parameters
+ + +
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osThreadTerminate shall be consistent in every CMSIS-RTOS.
+

Remove the thread function from the active thread list. If the thread is currently RUNNING the execution will stop.

+
Note
In case that osThreadTerminate terminates the currently running task, the function never returns and other threads that are in the READY state are started.
+

Status and Error Codes
+

+
    +
  • osOK: the specified thread has been successfully terminated.
    • +
  • osErrorParameter: thread_id is incorrect.
    • +
  • osErrorResource: thread_id refers to a thread that is not an active thread.
    • +
  • osErrorISR: osThreadTerminate cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Thread_1 (void const *arg); // function prototype for Thread_1
+
osThreadDef (Thread_1, osPriorityNormal, 1, 0); // define Thread_1
+
+
void ThreadTerminate_example (void) {
+
osStatus status;
+
osThreadId id;
+
+
id = osThreadCreate (osThread (Thread_1), NULL); // create the thread
+
:
+
status = osThreadTerminate (id); // stop the thread
+
if (status == osOK) {
+
// Thread was terminated successfully
+
}
+
else {
+
// Failed to terminate a thread
+
}
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osThreadYield (void )
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osThreadYield shall be consistent in every CMSIS-RTOS.
+

Pass control to the next thread that is in state READY. If there is no other thread in the state READY, the current thread continues execution and no thread switching occurs.

+

Status and Error Codes
+

+
    +
  • osOK: the function has been correctly executed.
    • +
  • osErrorISR: osThreadYield cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Thread_1 (void const *arg) { // Thread function
+
osStatus status; // status of the executed function
+
:
+
while (1) {
+
status = osThreadYield(); //
+
if (status != osOK) {
+
// thread switch not occurred, not in a thread function
+
}
+
}
+
}
+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.js new file mode 100644 index 000000000..fa5d5de16 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.js @@ -0,0 +1,21 @@ +var group___c_m_s_i_s___r_t_o_s___thread_mgmt = +[ + [ "osThread", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453", null ], + [ "osThreadDef", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f", null ], + [ "osPriority", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a", [ + [ "osPriorityIdle", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81", null ], + [ "osPriorityLow", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4", null ], + [ "osPriorityBelowNormal", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6", null ], + [ "osPriorityNormal", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1", null ], + [ "osPriorityAboveNormal", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b", null ], + [ "osPriorityHigh", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2", null ], + [ "osPriorityRealtime", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af", null ], + [ "osPriorityError", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4", null ] + ] ], + [ "osThreadCreate", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gac59b5713cb083702dce759c73fd90dff", null ], + [ "osThreadGetId", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7", null ], + [ "osThreadGetPriority", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9", null ], + [ "osThreadSetPriority", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b", null ], + [ "osThreadTerminate", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab", null ], + [ "osThreadYield", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html new file mode 100644 index 000000000..02b5164fa --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html @@ -0,0 +1,514 @@ + + + + + +CMSIS-RTOS: Timer Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Enumerations | +Functions
+
+
Timer Management
CMSIS-RTOS API
+
+
+ +

Create and control timer and timer callback functions. +More...

+ + + + + + + + +

+Macros

#define osTimerDef(name, function)
 Define a Timer object. More...
 
#define osTimer(name)   &os_timer_def_##name
 Access a Timer definition. More...
 
+ + + +

+Enumerations

enum  os_timer_type {
+  osTimerOnce = 0, +
+  osTimerPeriodic = 1 +
+ }
 
+ + + + + + + + + + + + + +

+Functions

osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)
 Create a timer. More...
 
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
 Start or restart a timer. More...
 
osStatus osTimerStop (osTimerId timer_id)
 Stop the timer. More...
 
osStatus osTimerDelete (osTimerId timer_id)
 Delete a timer that was created by osTimerCreate. More...
 
+

Description

+

The Timer Management function group allow creating and controlling of timers and callback functions in the system. A callback function is called when a time period expires whereby both one-shot and periodic timers are possible. A timer can be started, restarted, or stopped.

+

Timers are handled in the thread osTimerThread. Callback functions run under control of this thread and may use other CMSIS-RTOS API calls.

+

The figure below shows the behavior of a periodic timer. For one-shot timers, the timer stops after execution of the callback function.

+
+Timer.png +
+Behavior of a Periodic Timer
+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define osTimer( name)   &os_timer_def_##name
+
+

Access to the timer definition for the function osTimerCreate.

+
Parameters
+ + +
namename of the timer object.
+
+
+
Note
CAN BE CHANGED: The parameter to osTimer shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define osTimerDef( name,
 function 
)
+
+

Define the attributes of a timer.

+
Parameters
+ + + +
namename of the timer object.
functionname of the timer call back function.
+
+
+
Note
CAN BE CHANGED: The parameter to osTimerDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum os_timer_type
+
+
Note
MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS. The os_timer_type specifies the a repeating (periodic) or one-shot timer for the function osTimerCreate.
+ + + +
Enumerator
osTimerOnce  +

one-shot timer

+
osTimerPeriodic  +

repeating timer

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
osTimerId osTimerCreate (const osTimerDef_t * timer_def,
os_timer_type type,
void * argument 
)
+
+
Parameters
+ + + + +
[in]timer_deftimer object referenced with osTimer.
[in]typeosTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
[in]argumentargument to the timer call back function.
+
+
+
Returns
timer ID for reference by other functions or NULL in case of error.
+
Note
MUST REMAIN UNCHANGED: osTimerCreate shall be consistent in every CMSIS-RTOS.
+

Create a one-shot or periodic timer and associate it with a callback function argument. The timer is in stopped until it is started with osTimerStart.

+

Example

+
#include "cmsis_os.h"
+
+
void Timer1_Callback (void const *arg); // prototypes for timer callback function
+
void Timer2_Callback (void const *arg);
+
+
osTimerDef (Timer1, Timer1_Callback); // define timers
+
osTimerDef (Timer2, Timer2_Callback);
+
+
uint32_t exec1; // argument for the timer call back function
+
uint32_t exec2; // argument for the timer call back function
+
+
void TimerCreate_example (void) {
+
osTimerId id1; // timer id
+
osTimerId id2; // timer id
+
+
// Create one-shoot timer
+
exec1 = 1;
+
id1 = osTimerCreate (osTimer(Timer1), osTimerOnce, &exec1);
+
if (id1 != NULL) {
+
// One-shoot timer created
+
}
+
+
// Create periodic timer
+
exec2 = 2;
+
id2 = osTimerCreate (osTimer(Timer2), osTimerPeriodic, &exec2);
+
if (id2 != NULL) {
+
// Periodic timer created
+
}
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osTimerDelete (osTimerId timer_id)
+
+
Parameters
+ + +
[in]timer_idtimer ID obtained by osTimerCreate.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osTimerDelete shall be consistent in every CMSIS-RTOS.
+

Delete the timer object.

+

Status and Error Codes
+

+
    +
  • osOK: the specified timer has been deleted.
    • +
  • osErrorISR: osTimerDelete cannot be called from interrupt service routines.
    • +
  • osErrorParameter: timer_id is incorrect.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Timer_Callback (void const *arg); // prototype for timer callback function
+
osTimerDef (Timer, Timer_Callback); // define timer
+
+
void TimerDelete_example (void) {
+
osTimerId id; // timer id
+
osStatus status; // function return status
+
+
// Create periodic timer
+
exec = 1;
+
id = osTimerCreate (osTimer(Timer2), osTimerPeriodic, NULL);
+
osTimerStart (id, 1000UL); // start timer
+
:
+
status = osTimerDelete (id); // stop and delete timer
+
if (status != osOK) {
+
// Timer could not be deleted
+
}
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
osStatus osTimerStart (osTimerId timer_id,
uint32_t millisec 
)
+
+
Parameters
+ + + +
[in]timer_idtimer ID obtained by osTimerCreate.
[in]millisectime delay value of the timer.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osTimerStart shall be consistent in every CMSIS-RTOS.
+

Start or restart the timer.

+

Status and Error Codes
+

+
    +
  • osOK: the specified timer has been started or restarted.
    • +
  • osErrorISR: osTimerStart cannot be called from interrupt service routines.
    • +
  • osErrorParameter: timer_id is incorrect.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Time_Callback (void const *arg) { // timer callback function
+
// arg contains &exec
+
// called every second after osTimerStart
+
}
+
+
osTimerDef (Timer, Timer_Callback); // define timer
+
uint32_t exec; // argument for the timer call back function
+
+
void TimerStart_example (void) {
+
osTimerId id; // timer id
+
uint32_t timerDelay; // timer value
+
osStatus status; // function return status
+
+
// Create periodic timer
+
exec = 1;
+
id = osTimerCreate (osTimer(Timer), osTimerPeriodic, &exec);
+
if (id) {
+
timerDelay = 1000;
+
status = osTimerStart (id, timerDelay); // start timer
+
if (status != osOK) {
+
// Timer could not be started
+
}
+
}
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + +
osStatus osTimerStop (osTimerId timer_id)
+
+
Parameters
+ + +
[in]timer_idtimer ID obtained by osTimerCreate.
+
+
+
Returns
status code that indicates the execution status of the function.
+
Note
MUST REMAIN UNCHANGED: osTimerStop shall be consistent in every CMSIS-RTOS.
+

Stop the timer.

+

Status and Error Codes
+

+
    +
  • osOK: the specified timer has been stopped.
    • +
  • osErrorISR: osTimerStop cannot be called from interrupt service routines.
    • +
  • osErrorParameter: timer_id is incorrect.
    • +
  • osErrorResource: the timer is not started.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Timer_Callback (void const *arg); // prototype for timer callback function
+
osTimerDef (Timer, Timer_Callback); // define timer
+
+
void TimerStop_example (void) {
+
osTimerId id; // timer id
+
osStatus status; // function return status
+
+
// Create periodic timer
+
exec = 1;
+
id = osTimerCreate (osTimer(Timer2), osTimerPeriodic, NULL);
+
osTimerStart (id, 1000); // start timer
+
:
+
status = osTimerStop (id); // stop timer
+
if (status != osOK) {
+
// Timer could not be stopped
+
}
+
:
+
osTimerStart (id, 1000); // start timer again
+
:
+
}
+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.js new file mode 100644 index 000000000..60f1ace74 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.js @@ -0,0 +1,13 @@ +var group___c_m_s_i_s___r_t_o_s___timer_mgmt = +[ + [ "osTimer", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678", null ], + [ "osTimerDef", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1c720627e08d1cc1afcad44e799ed492", null ], + [ "os_timer_type", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9", [ + [ "osTimerOnce", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951", null ], + [ "osTimerPeriodic", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788", null ] + ] ], + [ "osTimerCreate", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gaedd312bfdca04e0b8162b666e09a1ae6", null ], + [ "osTimerDelete", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga746b8043d906849bd65e3900fcb483cf", null ], + [ "osTimerStart", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca", null ], + [ "osTimerStop", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html new file mode 100644 index 000000000..102a322e8 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html @@ -0,0 +1,281 @@ + + + + + +CMSIS-RTOS: Generic Wait Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Generic Wait Functions
CMSIS-RTOS API
+
+
+ +

Wait for a time period or unspecified events. +More...

+ + + + + +

+Macros

#define osFeature_Wait   1
 osWait function: 1=available, 0=not available More...
 
+ + + + + + + +

+Functions

osStatus osDelay (uint32_t millisec)
 Wait for Timeout (Time Delay). More...
 
osEvent osWait (uint32_t millisec)
 Wait for Signal, Message, Mail, or Timeout. More...
 
+

Description

+

The Generic Wait function group provides means for a time delay and allow to wait for unspecified events.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define osFeature_Wait   1
+
+

A CMSIS-RTOS implementation may support the generic wait function osWait.

+ + +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
osStatus osDelay (uint32_t millisec)
+
+
Parameters
+ + +
[in]millisectime delay value
+
+
+
Returns
status code that indicates the execution status of the function.
+

Wait for a specified time period in millisec.

+

Status and Error Codes
+

+
    +
  • osEventTimeout: the time delay is executed.
    • +
  • osErrorISR: osDelay cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Thread_1 (void const *arg) { // Thread function
+
osStatus status; // capture the return status
+
uint32_t delayTime; // delay time in milliseconds
+
+
delayTime = 1000; // delay 1 second
+
:
+
status = osDelay (delayTime); // suspend thread execution
+
// handle erroe code
+
:
+
}
+
+
+
+ +
+
+ + + + + + + + +
osEvent osWait (uint32_t millisec)
+
+
Parameters
+ + +
[in]millisectimeout value or 0 in case of no time-out
+
+
+
Returns
event that contains signal, message, or mail information or error code.
+
Note
MUST REMAIN UNCHANGED: osWait shall be consistent in every CMSIS-RTOS.
+

Wait for any event of the type Signal, Message, Mail for a specified time period in millisec. While the system waits the thread that is calling this function is put into the state WAITING. When millisec is set to osWaitForever the function will wait for an infinite time until a event occurs.

+
Note
this function is optionally and may not be provided by all CMSIS-RTOS implementations.
+

Status and Error Codes
+

+
    +
  • osEventSignal: a signal event occurred and is returned.
    • +
  • osEventMessage: a message event occurred and is returned.
    • +
  • osEventMail: a mail event occurred and is returned.
    • +
  • osEventTimeout: the time delay is executed.
    • +
  • osErrorISR: osDelay cannot be called from interrupt service routines.
    • +
+

Example

+
#include "cmsis_os.h"
+
+
void Thread_1 (void const *arg) { // Thread function
+
osEvent Event; // capture the event
+
uint32_t waitTime; // wait time in milliseconds
+
+
:
+
waitTime = osWaitForever; // special "wait" value
+
Event = osWait (waitTime); // wait forever and until an event occurred
+
switch (Event.status) {
+
case osEventSignal: // Signal arrived
+
: // Event.value.signals contains the signal flags
+
break;
+
+
case osEventMessage: // Message arrived
+
: // Event.value.p contains the message pointer
+
: // Event.def.message_id contains the message Id
+
break;
+
+
case osEventMail: // Mail arrived
+
: // Event.value.p contains the mail pointer
+
: // Event.def.mail_id contains the mail Id
+
break;
+
+
case osEventTimeout: // Timeout occurred
+
break;
+
+
default: // Error occurred
+
break;
+
}
+
:
+
}
+
+
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.js new file mode 100644 index 000000000..6694d9f4d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.js @@ -0,0 +1,6 @@ +var group___c_m_s_i_s___r_t_o_s___wait = +[ + [ "osFeature_Wait", "group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad", null ], + [ "osDelay", "group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255", null ], + [ "osWait", "group___c_m_s_i_s___r_t_o_s___wait.html#ga8470c8aaedfde524a44e22e5b2328285", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/index.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/index.html new file mode 100644 index 000000000..b820e7668 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/index.html @@ -0,0 +1,206 @@ + + + + + +CMSIS-RTOS: Overview + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

The CMSIS-RTOS API is a generic RTOS interface for Cortex-M processor-based devices. CMSIS-RTOS provides a standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users and the software industry.

+
    +
  • CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).
    • +
  • The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.
    • +
  • Middleware components that use the CMSIS-RTOS API are RTOS agnostic. CMSIS-RTOS compliant middleware is easier to adapt.
    • +
  • Standard project templates (such as motor control) of the CMSIS-RTOS API may be shipped with freely available CMSIS-RTOS implementations.
    • +
+
Note
The CMSIS-RTOS API defines a minimum feature set. Implementations with extended features may be provided by RTOS vendors.
+
+API_Structure.png +
+CMSIS-RTOS API Structure
+

A typical CMSIS-RTOS API implementation interfaces to an existing Real-Time Kernel. The CMSIS-RTOS API provides the following attributes and functionalities:

+
    +
  • Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and flexible which reduces the number of functions exposed to the user.
    • +
+ +
    +
  • Interrupt Service Routines (ISR) can call many CMSIS-RTOS functions. When a CMSIS-RTOS function cannot be called from ISR context, it rejects the invocation.
    • +
+
    +
  • Three different thread event types support communication between multiple threads and/or ISR:
      +
    • Signals: are flags that may be used to signal specific conditions to a thread. Signals can be modified in an ISR or set from other threads.
      • +
    • Message: is a 32-bit value that can be sent to a thread or an ISR. Messages are buffered in a queue. The message type and queue size is defined in a descriptor.
      • +
    • Mail: is a fixed-size memory block that can be sent to a thread or an ISR. Mails are buffered in a queue and memory allocation is provided. The mail type and queue size is defined in a descriptor.
      • +
    +
    • +
+ +
    +
  • CPU time can be schedule with the following functionalities:
      +
    • A timeout parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified, the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.
      • +
    • The osDelay function puts a thread into the state WAITING for a specified period of time.
      • +
    • The generic osWait function waits for events that are assigned to a thread.
      • +
    • The osThreadYield provides co-operative thread switching and passes execution to another thread of the same priority.
      • +
    +
    • +
+

The CMSIS-RTOS API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M Memory Protection Unit (MPU).

+

In some RTOS implementations threads may execute on different processors and Mail and Message queues can therefore reside in shard memory resources.

+

The CMSIS-RTOS API encourages the software industry to evolve existing RTOS implementations. Kernel objects are defined and accessed using macros. This allows differentiation. RTOS implementations can be different and optimized in various aspects towards the Cortex-M processors. Optional features may be for Example

+
    +
  • Generic Wait function; i.e. with support of time intervals.
    • +
  • Support of the Cortex-M Memory Protection Unit (MPU).
    • +
  • Zero-copy mail queue.
    • +
  • Support of multi-processor systems.
    • +
  • Support of a DMA controller.
    • +
  • Deterministic context switching.
    • +
  • Round-robin context switching.
    • +
  • Deadlock avoidance, for example with priority inversion.
    • +
  • Zero interrupt latency by using the Cortex-M3/M4 instructions LDEX and STEX.
    • +
+
+

Revision History of CMSIS-RTOS API

+ + + + + + + + + + + +
Version Description
V1.02 Added: New control functions for short timeouts in microsecond resolution osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec.
+ Removed: osSignalGet.
V1.01 Added capabilities for C++, kernel initialization and object deletion.
+ Prepared for C++ class interface. In this context to const attribute has been moved from osXxxxDef_t typedefs to the osXxxxDef macros.
+ Added: osTimerDelete, osMutexDelete, osSemaphoreDelete.
+ Added: osKernelInitialize that prepares the Kernel for object creation.
+
V0.03 V1.00 First official Release.
+ Added: osKernelStart; starting 'main' as a thread is now an optional feature.
+ Semaphores have now the standard behavior.
+ osTimerCreate does no longer start the timer. Added: osTimerStart (replaces osTimerRestart).
+ Changed: osThreadPass is renamed to osThreadYield.
V0.02 Preview Release.
+
+
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b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+".preventClickEvent",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery); +/* + * jQuery UI Resizable 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * jquery.ui.core.js + * jquery.ui.mouse.js + * jquery.ui.widget.js + */ +(function(a,b){a.widget("ui.resizable",a.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:!1,animate:!1,animateDuration:"slow",animateEasing:"swing",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:"e,s,se",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass("ui-resizable"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||"ui-resizable-helper":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")})),this.element=this.element.parent().data("resizable",this.element.data("resizable")),this.elementIsWrapper=!0,this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")}),this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0}),this.originalResizeStyle=this.originalElement.css("resize"),this.originalElement.css("resize","none"),this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"})),this.originalElement.css({margin:this.originalElement.css("margin")}),this._proportionallyResize()),this.handles=c.handles||(a(".ui-resizable-handle",this.element).length?{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"}:"e,s,se");if(this.handles.constructor==String){this.handles=="all"&&(this.handles="n,e,s,w,se,sw,ne,nw");var d=this.handles.split(",");this.handles={};for(var e=0;e
');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),"se"==f&&h.addClass("ui-icon ui-icon-gripsmall-diagonal-se"),this.handles[f]=".ui-resizable-"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=["padding",/ne|nw|n/.test(c)?"Top":/se|sw|s/.test(c)?"Bottom":/^e$/.test(c)?"Right":"Left"].join("");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(".ui-resizable-handle",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:"se"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass("ui-resizable-autohide").hover(function(){c.disabled||(a(this).removeClass("ui-resizable-autohide"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass("ui-resizable-autohide"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css("position"),width:c.outerWidth(),height:c.outerHeight(),top:c.css("top"),left:c.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(".ui-draggable")||/absolute/.test(f.css("position")))&&f.css({position:"absolute",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css("left")),h=c(this.helper.css("top"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio=="number"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(".ui-resizable-"+this.axis).css("cursor");a("body").css("cursor",i=="auto"?this.axis+"-resize":i),f.addClass("ui-resizable-resizing"),this._propagate("start",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate("resize",b),c.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger("resize",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],"left")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css("left"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css("top"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a("body").css("cursor","auto"),this.element.removeClass("ui-resizable-resizing"),this._propagate("stop",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:"absolute",left:this.elementOffset.left-e+"px",top:this.elementOffset.top-e+"px",zIndex:++c.zIndex}),this.helper.appendTo("body").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!="resize"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:"1.8.18"}),a.ui.plugin.add("resizable","alsoResize",{start:function(b,c){var d=a(this).data("resizable"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data("resizable-alsoresize",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css("left"),10),top:parseInt(b.css("top"),10)})})};typeof e.alsoResize=="object"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data("resizable-alsoresize"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?["width","height"]:["width","height","top","left"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof e.alsoResize=="object"&&!e.alsoResize.nodeType?a.each(e.alsoResize,function(a,b){i(a,b)}):i(e.alsoResize)},stop:function(b,c){a(this).removeData("resizable-alsoresize")}}),a.ui.plugin.add("resizable","animate",{stop:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d._proportionallyResizeElements,g=f.length&&/textarea/i.test(f[0].nodeName),h=g&&a.ui.hasScroll(f[0],"left")?0:d.sizeDiff.height,i=g?0:d.sizeDiff.width,j={width:d.size.width-i,height:d.size.height-h},k=parseInt(d.element.css("left"),10)+(d.position.left-d.originalPosition.left)||null,l=parseInt(d.element.css("top"),10)+(d.position.top-d.originalPosition.top)||null;d.element.animate(a.extend(j,l&&k?{top:l,left:k}:{}),{duration:e.animateDuration,easing:e.animateEasing,step:function(){var c={width:parseInt(d.element.css("width"),10),height:parseInt(d.element.css("height"),10),top:parseInt(d.element.css("top"),10),left:parseInt(d.element.css("left"),10)};f&&f.length&&a(f[0]).css({width:c.width,height:c.height}),d._updateCache(c),d._propagate("resize",b)}})}}),a.ui.plugin.add("resizable","containment",{start:function(b,d){var e=a(this).data("resizable"),f=e.options,g=e.element,h=f.containment,i=h instanceof a?h.get(0):/parent/.test(h)?g.parent().get(0):h;if(!!i){e.containerElement=a(i);if(/document/.test(h)||h==document)e.containerOffset={left:0,top:0},e.containerPosition={left:0,top:0},e.parentData={element:a(document),left:0,top:0,width:a(document).width(),height:a(document).height()||document.body.parentNode.scrollHeight};else{var j=a(i),k=[];a(["Top","Right","Left","Bottom"]).each(function(a,b){k[a]=c(j.css("padding"+b))}),e.containerOffset=j.offset(),e.containerPosition=j.position(),e.containerSize={height:j.innerHeight()-k[3],width:j.innerWidth()-k[1]};var l=e.containerOffset,m=e.containerSize.height,n=e.containerSize.width,o=a.ui.hasScroll(i,"left")?i.scrollWidth:n,p=a.ui.hasScroll(i)?i.scrollHeight:m;e.parentData={element:i,left:l.left,top:l.top,width:o,height:p}}}},resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.containerSize,g=d.containerOffset,h=d.size,i=d.position,j=d._aspectRatio||b.shiftKey,k={top:0,left:0},l=d.containerElement;l[0]!=document&&/static/.test(l.css("position"))&&(k=g),i.left<(d._helper?g.left:0)&&(d.size.width=d.size.width+(d._helper?d.position.left-g.left:d.position.left-k.left),j&&(d.size.height=d.size.width/e.aspectRatio),d.position.left=e.helper?g.left:0),i.top<(d._helper?g.top:0)&&(d.size.height=d.size.height+(d._helper?d.position.top-g.top:d.position.top),j&&(d.size.width=d.size.height*e.aspectRatio),d.position.top=d._helper?g.top:0),d.offset.left=d.parentData.left+d.position.left,d.offset.top=d.parentData.top+d.position.top;var m=Math.abs((d._helper?d.offset.left-k.left:d.offset.left-k.left)+d.sizeDiff.width),n=Math.abs((d._helper?d.offset.top-k.top:d.offset.top-g.top)+d.sizeDiff.height),o=d.containerElement.get(0)==d.element.parent().get(0),p=/relative|absolute/.test(d.containerElement.css("position"));o&&p +&&(m-=d.parentData.left),m+d.size.width>=d.parentData.width&&(d.size.width=d.parentData.width-m,j&&(d.size.height=d.size.width/d.aspectRatio)),n+d.size.height>=d.parentData.height&&(d.size.height=d.parentData.height-n,j&&(d.size.width=d.size.height*d.aspectRatio))},stop:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.position,g=d.containerOffset,h=d.containerPosition,i=d.containerElement,j=a(d.helper),k=j.offset(),l=j.outerWidth()-d.sizeDiff.width,m=j.outerHeight()-d.sizeDiff.height;d._helper&&!e.animate&&/relative/.test(i.css("position"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m}),d._helper&&!e.animate&&/static/.test(i.css("position"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m})}}),a.ui.plugin.add("resizable","ghost",{start:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.size;d.ghost=d.originalElement.clone(),d.ghost.css({opacity:.25,display:"block",position:"relative",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof e.ghost=="string"?e.ghost:""),d.ghost.appendTo(d.helper)},resize:function(b,c){var d=a(this).data("resizable"),e=d.options;d.ghost&&d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})},stop:function(b,c){var d=a(this).data("resizable"),e=d.options;d.ghost&&d.helper&&d.helper.get(0).removeChild(d.ghost.get(0))}}),a.ui.plugin.add("resizable","grid",{resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.size,g=d.originalSize,h=d.originalPosition,i=d.axis,j=e._aspectRatio||b.shiftKey;e.grid=typeof e.grid=="number"?[e.grid,e.grid]:e.grid;var k=Math.round((f.width-g.width)/(e.grid[0]||1))*(e.grid[0]||1),l=Math.round((f.height-g.height)/(e.grid[1]||1))*(e.grid[1]||1);/^(se|s|e)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l):/^(ne)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l):/^(sw)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.left=h.left-k):(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l,d.position.left=h.left-k)}});var c=function(a){return parseInt(a,10)||0},d=function(a){return!isNaN(parseInt(a,10))}})(jQuery); +/* + * jQuery hashchange event - v1.3 - 7/21/2010 + * http://benalman.com/projects/jquery-hashchange-plugin/ + * + * Copyright (c) 2010 "Cowboy" Ben Alman + * Dual licensed under the MIT and GPL licenses. + * http://benalman.com/about/license/ + */ +(function($,e,b){var c="hashchange",h=document,f,g=$.event.special,i=h.documentMode,d="on"+c in e&&(i===b||i>7);function a(j){j=j||location.href;return"#"+j.replace(/^[^#]*#?(.*)$/,"$1")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,"")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$(' + + +
+
+
Reference
+
+
+
Here is a list of all modules:
+
[detail level 12]
+ + + + + + + + + + + + + +
\CMSIS-RTOS APIThis section describes the CMSIS-RTOS API
 oKernel Information and ControlProvide version/system information and start the RTOS Kernel
 oThread ManagementDefine, create, and control thread functions
 oGeneric Wait FunctionsWait for a time period or unspecified events
 oTimer ManagementCreate and control timer and timer callback functions
 oSignal ManagementControl or wait for signal flags
 oMutex ManagementSynchronize thread execution with a Mutex
 oSemaphore ManagementControl access to shared resources
 oMemory Pool ManagementDefine and manage fixed-size memory pools
 oMessage Queue ManagementControl, send, receive, or wait for messages
 oMail Queue ManagementControl, send, receive, or wait for mail
 oGeneric Data Types and DefinitionsData Type Definitions used by the CMSIS-RTOS API functions
 \Status and Error CodesStatus and Error Codes returned by CMSIS-RTOS API functions
+ + + + + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/modules.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/modules.js new file mode 100644 index 000000000..909dd3d60 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/modules.js @@ -0,0 +1,4 @@ +var modules = +[ + [ "CMSIS-RTOS API", "group___c_m_s_i_s___r_t_o_s.html", "group___c_m_s_i_s___r_t_o_s" ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_f.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_f.png new file mode 100644 index 000000000..72a58a529 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_f.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_g.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_g.png new file mode 100644 index 000000000..2093a237a Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_g.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_h.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_h.png new file mode 100644 index 000000000..33389b101 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/nav_h.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/navtree.css b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/navtree.css new file mode 100644 index 000000000..41a9cb969 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/navtree.css @@ -0,0 +1,143 @@ +#nav-tree .children_ul { + margin:0; + padding:4px; +} + +#nav-tree ul { + list-style:none outside none; + margin:0px; + padding:0px; +} + +#nav-tree li { + white-space:nowrap; + margin:0px; + padding:0px; +} + +#nav-tree .plus { + margin:0px; +} + +#nav-tree .selected { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} + +#nav-tree img { + margin:0px; + padding:0px; + border:0px; + vertical-align: middle; +} + +#nav-tree a { + text-decoration:none; + padding:0px; + margin:0px; + outline:none; +} + +#nav-tree .label { + margin:0px; + padding:0px; + font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; +} + +#nav-tree .label a { + padding:2px; +} + +#nav-tree .selected a { + text-decoration:none; + color:#fff; +} + +#nav-tree .children_ul { + margin:0px; + padding:0px; +} + +#nav-tree .item { + margin:0px; + padding:0px; +} + +#nav-tree { + padding: 0px 0px; + background-color: #FAFAFF; + font-size:14px; + overflow:auto; +} + +#doc-content { + overflow:auto; + display:block; + padding:0px; + margin:0px; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#side-nav { + padding:0 6px 0 0; + margin: 0px; + display:block; + position: absolute; + left: 0px; + width: 250px; +} + +.ui-resizable .ui-resizable-handle { + display:block; +} + +.ui-resizable-e { + background:url("ftv2splitbar.png") repeat scroll right center transparent; + cursor:e-resize; + height:100%; + right:0; + top:0; + width:6px; +} + +.ui-resizable-handle { + display:none; + font-size:0.1px; + position:absolute; + z-index:1; +} + +#nav-tree-contents { + margin: 6px 0px 0px 0px; +} + +#nav-tree { + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#nav-sync { + position:absolute; + top:5px; + right:24px; + z-index:0; +} + +#nav-sync img { + opacity:0.3; +} + +#nav-sync img:hover { + opacity:0.9; +} + +@media print +{ + #nav-tree { display: none; } + div.ui-resizable-handle { display: none; position: relative; } +} + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/navtree.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/navtree.js new file mode 100644 index 000000000..29894a7c2 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/navtree.js @@ -0,0 +1,517 @@ +var NAVTREE = +[ + [ "CMSIS-RTOS", "index.html", [ + [ "Overview", "index.html", null ], + [ "Using a CMSIS RTOS Implementation", "_using_o_s.html", null ], + [ "Function Overview", "_function_overview.html", null ], + [ "Header File Template: cmsis_os.h", "cmsis_os_h.html", null ], + [ "Reference", "modules.html", "modules" ], + [ "Data Structures", "annotated.html", "annotated" ], + [ "Data Structure Index", "classes.html", null ], + [ "Data Fields", "functions.html", [ + [ "All", "functions.html", null ], + [ "Variables", "functions_vars.html", null ] + ] ] + ] ] +]; + +var NAVTREEINDEX = +[ +"_function_overview.html" +]; + +var SYNCONMSG = 'click to disable panel synchronisation'; +var SYNCOFFMSG = 'click to enable panel synchronisation'; +var navTreeSubIndices = new Array(); + +function getData(varName) +{ + var i = varName.lastIndexOf('/'); + var n = i>=0 ? varName.substring(i+1) : varName; + return eval(n.replace(/\-/g,'_')); +} + +function stripPath(uri) +{ + return uri.substring(uri.lastIndexOf('/')+1); +} + +function stripPath2(uri) +{ + var i = uri.lastIndexOf('/'); + var s = uri.substring(i+1); + var m = uri.substring(0,i+1).match(/\/d\w\/d\w\w\/$/); + return m ? uri.substring(i-6) : s; +} + +function localStorageSupported() +{ + try { + return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem; + } + catch(e) { + return false; + } +} + + +function storeLink(link) +{ + if (!$("#nav-sync").hasClass('sync') && localStorageSupported()) { + window.localStorage.setItem('navpath',link); + } +} + +function deleteLink() +{ + if (localStorageSupported()) { + window.localStorage.setItem('navpath',''); + } +} + +function cachedLink() +{ + if (localStorageSupported()) { + return window.localStorage.getItem('navpath'); + } else { + return ''; + } +} + +function getScript(scriptName,func,show) +{ + var head = document.getElementsByTagName("head")[0]; + var script = document.createElement('script'); + script.id = scriptName; + script.type = 'text/javascript'; + script.onload = func; + script.src = scriptName+'.js'; + if ($.browser.msie && $.browser.version<=8) { + // script.onload does not work with older versions of IE + script.onreadystatechange = function() { + if (script.readyState=='complete' || script.readyState=='loaded') { + func(); if (show) showRoot(); + } + } + } + head.appendChild(script); +} + +function createIndent(o,domNode,node,level) +{ + var level=-1; + var n = node; + while (n.parentNode) { level++; n=n.parentNode; } + var imgNode = document.createElement("img"); + imgNode.style.paddingLeft=(16*level).toString()+'px'; + imgNode.width = 16; + imgNode.height = 22; + imgNode.border = 0; + if (node.childrenData) { + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() { + if (node.expanded) { + $(node.getChildrenUL()).slideUp("fast"); + node.plus_img.src = node.relpath+"ftv2pnode.png"; + node.expanded = false; + } else { + expandNode(o, node, false, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + imgNode.src = node.relpath+"ftv2pnode.png"; + } else { + imgNode.src = node.relpath+"ftv2node.png"; + domNode.appendChild(imgNode); + } +} + +var animationInProgress = false; + +function gotoAnchor(anchor,aname,updateLocation) +{ + var pos, docContent = $('#doc-content'); + if (anchor.parent().attr('class')=='memItemLeft' || + anchor.parent().attr('class')=='fieldtype' || + anchor.parent().is(':header')) + { + pos = anchor.parent().position().top; + } else if (anchor.position()) { + pos = anchor.position().top; + } + if (pos) { + var dist = Math.abs(Math.min( + pos-docContent.offset().top, + docContent[0].scrollHeight- + docContent.height()-docContent.scrollTop())); + animationInProgress=true; + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + if (updateLocation) window.location.href=aname; + animationInProgress=false; + }); + } +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + node.expanded = false; + a.appendChild(node.label); + if (link) { + var url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + link = url; + } else { + url = node.relpath+link; + } + a.className = stripPath(link.replace('#',':')); + if (link.indexOf('#')!=-1) { + var aname = '#'+link.split('#')[1]; + var srcPage = stripPath($(location).attr('pathname')); + var targetPage = stripPath(link.split('#')[0]); + a.href = srcPage!=targetPage ? url : "javascript:void(0)"; + a.onclick = function(){ + storeLink(link); + if (!$(a).parent().parent().hasClass('selected')) + { + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + $(a).parent().parent().addClass('selected'); + $(a).parent().parent().attr('id','selected'); + } + var anchor = $(aname); + gotoAnchor(anchor,aname,true); + }; + } else { + a.href = url; + a.onclick = function() { storeLink(link); } + } + } else { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() { + if (!node.childrenUL) { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } if (imm || ($.browser.msie && $.browser.version>8)) { + // somehow slideDown jumps to the start of tree for IE9 :-( + $(node.getChildrenUL()).show(); + } else { + $(node.getChildrenUL()).slideDown("fast"); + } + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var aname = $(location).attr('hash'); + var anchor = $(aname); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+ + window.location.hash.substring(1)+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parents().slice(2).prop('tagName')=='TR') { + glowEffect(anchor.parents('div.memitem'),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if (anchor.parent().is(":header")) { + glowEffect(anchor.parent(),1000); // section header + } else { + glowEffect(anchor.next(),1000); // normal member + } + gotoAnchor(anchor,aname,false); +} + +function selectAndHighlight(hash,n) +{ + var a; + if (hash) { + var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1); + a=$('.item a[class$="'+link+'"]'); + } + if (a && a.length) { + a.parent().parent().addClass('selected'); + a.parent().parent().attr('id','selected'); + highlightAnchor(); + } else if (n) { + $(n.itemDiv).addClass('selected'); + $(n.itemDiv).attr('id','selected'); + } + if ($('#nav-tree-contents .item:first').hasClass('selected')) { + $('#nav-sync').css('top','30px'); + } else { + $('#nav-sync').css('top','5px'); + } + showRoot(); +} + +function showNode(o, node, index, hash) +{ + if (node && node.childrenData) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + showNode(o,node,index,hash); + },true); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } + $(node.getChildrenUL()).show(); + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + var n = node.children[o.breadcrumbs[index]]; + if (index+11) hash = '#'+parts[1]; + else hash=''; + } + if (hash.match(/^#l\d+$/)) { + var anchor=$('a[name='+hash.substring(1)+']'); + glowEffect(anchor.parent(),1000); // line number + hash=''; // strip line number anchors + //root=root.replace(/_source\./,'.'); // source link to doc link + } + var url=root+hash; + var i=-1; + while (NAVTREEINDEX[i+1]<=url) i++; + if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath) + } else { + getScript(relpath+'navtreeindex'+i,function(){ + navTreeSubIndices[i] = eval('NAVTREEINDEX'+i); + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath); + } + },true); + } +} + +function showSyncOff(n,relpath) +{ + n.html(''); +} + +function showSyncOn(n,relpath) +{ + n.html(''); +} + +function toggleSyncButton(relpath) +{ + var navSync = $('#nav-sync'); + if (navSync.hasClass('sync')) { + navSync.removeClass('sync'); + showSyncOff(navSync,relpath); + storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash')); + } else { + navSync.addClass('sync'); + showSyncOn(navSync,relpath); + deleteLink(); + } +} + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = NAVTREE; + o.node.children = new Array(); + o.node.childrenUL = document.createElement("ul"); + o.node.getChildrenUL = function() { return o.node.childrenUL; }; + o.node.li.appendChild(o.node.childrenUL); + o.node.depth = 0; + o.node.relpath = relpath; + o.node.expanded = false; + o.node.isLast = true; + o.node.plus_img = document.createElement("img"); + o.node.plus_img.src = relpath+"ftv2pnode.png"; + o.node.plus_img.width = 16; + o.node.plus_img.height = 22; + + if (localStorageSupported()) { + var navSync = $('#nav-sync'); + if (cachedLink()) { + showSyncOff(navSync,relpath); + navSync.removeClass('sync'); + } else { + showSyncOn(navSync,relpath); + } + navSync.click(function(){ toggleSyncButton(relpath); }); + } + + navTo(o,toroot,window.location.hash,relpath); + + $(window).bind('hashchange', function(){ + if (window.location.hash && window.location.hash.length>1){ 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b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/open.png new file mode 100644 index 000000000..30f75c7ef Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/open.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/pages.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/pages.html new file mode 100644 index 000000000..8be6f8912 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/pages.html @@ -0,0 +1,134 @@ + + + + + +CMSIS-RTOS: Usage and Description + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + +
+
+ +
+
+
+ +
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+
Usage and Description
+
+
+
Here is a list of all related documentation pages:
+ + + + +
oUsing a CMSIS RTOS Implementation
oFunction Overview
\Header File Template: cmsis_os.h
+
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+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/pages_75.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/pages_75.js new file mode 100644 index 000000000..2482eafab --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/pages_75.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['using_20a_20cmsis_20rtos_20implementation',['Using a CMSIS RTOS Implementation',['../_using_o_s.html',1,'']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/search.css b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/search.css new file mode 100644 index 000000000..1746d13fd --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/search.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/search.js new file mode 100644 index 000000000..222cdd331 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/search.js @@ -0,0 +1,815 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101111010101110111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000100110110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 9: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100010100000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 10: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000001000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "typedefs", + 6: "enums", + 7: "enumvalues", + 8: "defines", + 9: "groups", + 10: "pages" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var hexCode; + if (code<16) + { + hexCode="0"+code.toString(16); + } + else + { + hexCode=code.toString(16); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1') + { + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/typedefs_6f.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/typedefs_6f.js new file mode 100644 index 000000000..e543bcc9e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/typedefs_6f.js @@ -0,0 +1,12 @@ +var searchData= +[ + ['os_5fpthread',['os_pthread',['../cmsis__os_8h.html#aee631e5ea1b700fc35695cc7bc574cf7',1,'cmsis_os.h']]], + ['os_5fptimer',['os_ptimer',['../cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065',1,'cmsis_os.h']]], + ['osmailqid',['osMailQId',['../cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5',1,'cmsis_os.h']]], + ['osmessageqid',['osMessageQId',['../cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f',1,'cmsis_os.h']]], + ['osmutexid',['osMutexId',['../cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2',1,'cmsis_os.h']]], + ['ospoolid',['osPoolId',['../cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686',1,'cmsis_os.h']]], + ['ossemaphoreid',['osSemaphoreId',['../cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84',1,'cmsis_os.h']]], + ['osthreadid',['osThreadId',['../cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f',1,'cmsis_os.h']]], + ['ostimerid',['osTimerId',['../cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7',1,'cmsis_os.h']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html new file mode 100644 index 000000000..df4414b92 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_64.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_64.js new file mode 100644 index 000000000..0d71cbb4d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_64.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['def',['def',['../group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6',1,'osEvent']]], + ['dummy',['dummy',['../structos_mutex_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca',1,'osMutexDef_t::dummy()'],['../structos_semaphore_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca',1,'osSemaphoreDef_t::dummy()']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html new file mode 100644 index 000000000..44c2cd1ee --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_69.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_69.js new file mode 100644 index 000000000..44d5ab347 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_69.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['instances',['instances',['../structos_thread_def__t.html#aa4c4115851a098c0b87358ab6c025603',1,'osThreadDef_t']]], + ['item_5fsz',['item_sz',['../structos_pool_def__t.html#a4c2a0c691de3365c00ecd22d8102811f',1,'osPoolDef_t::item_sz()'],['../structos_message_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f',1,'osMessageQDef_t::item_sz()'],['../structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f',1,'osMailQDef_t::item_sz()']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html new file mode 100644 index 000000000..1b8f1a83a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.js new file mode 100644 index 000000000..c9d2b49ed --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['mail_5fid',['mail_id',['../group___c_m_s_i_s___r_t_o_s___definitions.html#ac86175a4b1706bee596f3018322df26e',1,'osEvent']]], + ['message_5fid',['message_id',['../group___c_m_s_i_s___r_t_o_s___definitions.html#af394cbe21dde7377974e63af38cd87b0',1,'osEvent']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html new file mode 100644 index 000000000..439d152f5 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_70.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_70.js new file mode 100644 index 000000000..68e34f3a0 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_70.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['p',['p',['../group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709',1,'osEvent']]], + ['pool',['pool',['../structos_pool_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c',1,'osPoolDef_t::pool()'],['../structos_message_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c',1,'osMessageQDef_t::pool()'],['../structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c',1,'osMailQDef_t::pool()']]], + ['pool_5fsz',['pool_sz',['../structos_pool_def__t.html#ac112e786b2a234e0e45cb5bdbee53763',1,'osPoolDef_t']]], + ['pthread',['pthread',['../structos_thread_def__t.html#ad3c9624ee214329fb34e71f544a6933e',1,'osThreadDef_t']]], + ['ptimer',['ptimer',['../structos_timer_def__t.html#a15773df83aba93f8e61f3737af5fae47',1,'osTimerDef_t']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html new file mode 100644 index 000000000..1d2bf39ce --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
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+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_71.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_71.js new file mode 100644 index 000000000..5a829f8e5 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_71.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['queue_5fsz',['queue_sz',['../structos_message_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0',1,'osMessageQDef_t::queue_sz()'],['../structos_mail_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0',1,'osMailQDef_t::queue_sz()']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html new file mode 100644 index 000000000..388a6d74b --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_73.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_73.js new file mode 100644 index 000000000..40d255b63 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_73.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['signals',['signals',['../group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6',1,'osEvent']]], + ['stacksize',['stacksize',['../structos_thread_def__t.html#a950b7f81ad4711959517296e63bc79d1',1,'osThreadDef_t']]], + ['status',['status',['../group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3',1,'osEvent']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html new file mode 100644 index 000000000..1665fb806 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
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+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_74.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_74.js new file mode 100644 index 000000000..f516467dd --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_74.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['tpriority',['tpriority',['../structos_thread_def__t.html#a15da8f23c6fe684b70a73646ada685e7',1,'osThreadDef_t']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html new file mode 100644 index 000000000..8af237461 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
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+ +
+ + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_76.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_76.js new file mode 100644 index 000000000..15d25561a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/search/variables_76.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['v',['v',['../group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc',1,'osEvent']]], + ['value',['value',['../group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f',1,'osEvent']]] +]; diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html new file mode 100644 index 000000000..fa243984b --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html @@ -0,0 +1,192 @@ + + + + + +CMSIS-RTOS: osMailQDef_t Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
osMailQDef_t Struct Reference
+
+
+ +

Definition structure for mail queue. + More...

+ + + + + + + + + + + +

+Data Fields

uint32_t queue_sz
 number of elements in the queue More...
 
uint32_t item_sz
 size of an item More...
 
void * pool
 memory array for mail More...
 
+

Description

+
Note
CAN BE CHANGED: os_mailQ_def is implementation specific in every CMSIS-RTOS.
+

Field Documentation

+ +
+
+ + + + +
uint32_t item_sz
+
+ +
+
+ +
+
+ + + + +
void* pool
+
+ +
+
+ +
+
+ + + + +
uint32_t queue_sz
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.js new file mode 100644 index 000000000..dc34d7b76 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.js @@ -0,0 +1,6 @@ +var structos_mail_q_def__t = +[ + [ "item_sz", "structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f", null ], + [ "pool", "structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c", null ], + [ "queue_sz", "structos_mail_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html new file mode 100644 index 000000000..1bd78aad6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html @@ -0,0 +1,192 @@ + + + + + +CMSIS-RTOS: osMessageQDef_t Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
osMessageQDef_t Struct Reference
+
+
+ +

Definition structure for message queue. + More...

+ + + + + + + + + + + +

+Data Fields

uint32_t queue_sz
 number of elements in the queue More...
 
uint32_t item_sz
 size of an item More...
 
void * pool
 memory array for messages More...
 
+

Description

+
Note
CAN BE CHANGED: os_messageQ_def is implementation specific in every CMSIS-RTOS.
+

Field Documentation

+ +
+
+ + + + +
uint32_t item_sz
+
+ +
+
+ +
+
+ + + + +
void* pool
+
+ +
+
+ +
+
+ + + + +
uint32_t queue_sz
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.js new file mode 100644 index 000000000..74afca4a3 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.js @@ -0,0 +1,6 @@ +var structos_message_q_def__t = +[ + [ "item_sz", "structos_message_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f", null ], + [ "pool", "structos_message_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c", null ], + [ "queue_sz", "structos_message_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html new file mode 100644 index 000000000..053b033ce --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html @@ -0,0 +1,162 @@ + + + + + +CMSIS-RTOS: osMutexDef_t Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
osMutexDef_t Struct Reference
+
+
+ +

Mutex Definition structure contains setup information for a mutex. + More...

+ + + + + +

+Data Fields

uint32_t dummy
 dummy value. More...
 
+

Description

+
Note
CAN BE CHANGED: os_mutex_def is implementation specific in every CMSIS-RTOS.
+

Field Documentation

+ +
+
+ + + + +
uint32_t dummy
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.js new file mode 100644 index 000000000..61bec267a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.js @@ -0,0 +1,4 @@ +var structos_mutex_def__t = +[ + [ "dummy", "structos_mutex_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html new file mode 100644 index 000000000..3eaae9be0 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html @@ -0,0 +1,192 @@ + + + + + +CMSIS-RTOS: osPoolDef_t Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
osPoolDef_t Struct Reference
+
+
+ +

Definition structure for memory block allocation. + More...

+ + + + + + + + + + + +

+Data Fields

uint32_t pool_sz
 number of items (elements) in the pool More...
 
uint32_t item_sz
 size of an item More...
 
void * pool
 pointer to memory for pool More...
 
+

Description

+
Note
CAN BE CHANGED: os_pool_def is implementation specific in every CMSIS-RTOS.
+

Field Documentation

+ +
+
+ + + + +
uint32_t item_sz
+
+ +
+
+ +
+
+ + + + +
void* pool
+
+ +
+
+ +
+
+ + + + +
uint32_t pool_sz
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.js new file mode 100644 index 000000000..c5f4af22d --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.js @@ -0,0 +1,6 @@ +var structos_pool_def__t = +[ + [ "item_sz", "structos_pool_def__t.html#a4c2a0c691de3365c00ecd22d8102811f", null ], + [ "pool", "structos_pool_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c", null ], + [ "pool_sz", "structos_pool_def__t.html#ac112e786b2a234e0e45cb5bdbee53763", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html new file mode 100644 index 000000000..679b99c0e --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html @@ -0,0 +1,162 @@ + + + + + +CMSIS-RTOS: osSemaphoreDef_t Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
osSemaphoreDef_t Struct Reference
+
+
+ +

Semaphore Definition structure contains setup information for a semaphore. + More...

+ + + + + +

+Data Fields

uint32_t dummy
 dummy value. More...
 
+

Description

+
Note
CAN BE CHANGED: os_semaphore_def is implementation specific in every CMSIS-RTOS.
+

Field Documentation

+ +
+
+ + + + +
uint32_t dummy
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.js new file mode 100644 index 000000000..9e62fa3b6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.js @@ -0,0 +1,4 @@ +var structos_semaphore_def__t = +[ + [ "dummy", "structos_semaphore_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html new file mode 100644 index 000000000..1ec41e994 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html @@ -0,0 +1,207 @@ + + + + + +CMSIS-RTOS: osThreadDef_t Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
osThreadDef_t Struct Reference
+
+
+ +

Thread Definition structure contains startup information of a thread. + More...

+ + + + + + + + + + + + + + +

+Data Fields

os_pthread pthread
 start address of thread function More...
 
osPriority tpriority
 initial thread priority More...
 
uint32_t instances
 maximum number of instances of that thread function More...
 
uint32_t stacksize
 stack size requirements in bytes; 0 is default stack size More...
 
+

Description

+
Note
CAN BE CHANGED: os_thread_def is implementation specific in every CMSIS-RTOS.
+

Field Documentation

+ +
+
+ + + + +
uint32_t instances
+
+ +
+
+ +
+
+ + + + +
os_pthread pthread
+
+ +
+
+ +
+
+ + + + +
uint32_t stacksize
+
+ +
+
+ +
+
+ + + + +
osPriority tpriority
+
+ +
+
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.js new file mode 100644 index 000000000..33b12075a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.js @@ -0,0 +1,7 @@ +var structos_thread_def__t = +[ + [ "instances", "structos_thread_def__t.html#aa4c4115851a098c0b87358ab6c025603", null ], + [ "pthread", "structos_thread_def__t.html#ad3c9624ee214329fb34e71f544a6933e", null ], + [ "stacksize", "structos_thread_def__t.html#a950b7f81ad4711959517296e63bc79d1", null ], + [ "tpriority", "structos_thread_def__t.html#a15da8f23c6fe684b70a73646ada685e7", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html new file mode 100644 index 000000000..a5113adc0 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html @@ -0,0 +1,162 @@ + + + + + +CMSIS-RTOS: osTimerDef_t Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-RTOS +  Version 1.02 +
+
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
+
+
+ +
+ +
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
osTimerDef_t Struct Reference
+
+
+ +

Timer Definition structure contains timer parameters. + More...

+ + + + + +

+Data Fields

os_ptimer ptimer
 start address of a timer function More...
 
+

Description

+
Note
CAN BE CHANGED: os_timer_def is implementation specific in every CMSIS-RTOS.
+

Field Documentation

+ +
+
+ + + + +
os_ptimer ptimer
+
+ +
+
+
+
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+ font-size: 13px; + line-height: 1.3; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + border: 1px solid #2D4068; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + height: 28px; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + + + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; +} + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #354E81; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + width: 100%; + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + width: 100%; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + margin-left: 5px; + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 7px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/doxygen.png b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/doxygen.png new file mode 100644 index 000000000..3ff17d807 Binary files /dev/null and b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/doxygen.png differ diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/dynsections.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/dynsections.js new file mode 100644 index 000000000..ed092c7f6 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + +CMSIS-SVD: Cluster Level (New) + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Cluster Level (New)
SVD Extension in Version 1.1
+
+
+

Cluster adds a new and optional sub-level to the CMSIS SVD registers level. A cluster describes a sequence of registers within a peripheral. A cluster has an base offset relative to the base address of the peripheral. All registers within a cluster specify their address offset relative to the cluster base address. Register and cluster sections can occur in an arbitrary order. This feature, targeted at the generation of device header files, is useful to create a C data structure within the peripheral structure type, rather than describing all registers of a peripheral in a flat structure.

+
+
+<registers> 
    <cluster derivedFrom=identifierType>
+    
+        <!-- dimElementGroup --> 
+        <dim>scaledNonNegativeInteger</dim>
+        <dimIncrement>scaledNonNegativeInteger</dimIncrement>
+        <dimIndex>dimIndexType</dimIndex>
+        <!-- end of dimElementGroup --> 
+    
+        <name>identifierType</name>
+        <description>xs:string</description>
+    
+        <headerStructName>identifierType</headerStructName>
+        <alternateCluster>identifierType</alternateCluster>
+    
+        <addressOffset>scaledNonNegativeInteger</addressOffset>
        <register>
+            ...
+        </register>
+    </cluster>
+    ...
+    <register>
+        ...
+    </register>
+    <cluster>
+        ...
+    </cluster>
+     
+<registers> 
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
Attribute Name Description Type Occurrence
derivedFrom Specifies the name of the cluster from which to inherit the data. Elements being specified underneath will override the inherited values.
+Remarks: When deriving a cluster, it is mandatory to specify at least the name, the description, and the addressOffset. 		registerType 0..1
Element Name Description Type Occurrence
See dimElementGroup for details.
dimIncrement The value defines the number of elements in an array of clusters. scaledNonNegativeInteger 1..1
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring clusters of the cluster array in the address map. scaledNonNegativeInteger 1..1
dimIndex Specifies the substrings that replaces the [%s] placeholder within the cluster name. By default, the index is a decimal value starting with 0 for the first cluster element. dimIndexType 0..1
name String that identifies the cluster. Register names are required to be unique within the scope of a peripheral. Specify [%s] for generating an array in the device header file. identifierType 1..1
description String describing the details of the register. xs:string 0..1
alternateCluster This tag needs to specify the name of the original description of the register sequence if this cluster provides an alternative description. Otherwise the SVDConv will issue errors. identifierType 0..1
headerStructName This tag specifies the struct type name in the device header file. If not specified, then the name of the cluster will be used. identifierType 0..1
addressOffset Value defining the cluster address relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1
+

+Example:

+
<cluster>
+
<dim>4</dim>
+
<dimIncrement>8</dimIncrement>
+
<dimIndex>0-3</dimIndex>
+
<name>TX[%s]</name>
+
<description>Grouping of Transfer data and address</description>
+
<addressOffset>0x40</addressOffset>
+
<register>
+
<name>TX_DATA</name>
+
...
+
<addressOffset>0x0</addressOffset>
+
...
+
</register>
+
<register>
+
<name>TX_ADDR</name>
+
...
+
<addressOffset>0x4</addressOffset>
+
...
+
</register>
+
</cluster>
+

The example above describes an array of type TX with 4 elements. TX is a cluster of two consecutive registers with 4 elements. The device header file looks like this:

+
typedef struct {
+
...
+
struct {
+
__IO uint32_t TX_DATA;
+
__IO uint32_t TX_ADDR;
+
} TX[4];
+
...
+
} ..._Type;
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html new file mode 100644 index 000000000..373dd1a1a --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html @@ -0,0 +1,150 @@ + + + + + +CMSIS-SVD: CPU Section (New) + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
CPU Section (New)
SVD Extension in Version 1.1
+
+
+

The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.

+
+<cpu>
+    <name>cpuNameType<name>
+    <revision>revisionType<revision>
+    <endian>endianType<endian>
+    <mpuPresent>xs:boolean<mpuPresent>
+    <fpuPresent>xs:boolean<fpuPresent>
+    <vtorPresent>xs:boolean<vtorPresent>
+    <nvicPrioBits>scaledNonNegativeInteger<nvicPrioBits>
+    <vendorSystickConfig>xs:boolean<vendorSystickConfig>
+</cpu>
+
+ + + + + + + + + + + + + + + + + + +
Element Name Description Type Occurrence
name The predefined tokens are:
    +
  • CM0: ARM Cortex-M0
    • +
  • CM0PLUS: ARM Cortex-M0+
    • +
  • CM3: ARM Cortex-M3
    • +
  • CM4: ARM Cortex-M4
    • +
  • SC000: ARM Secure Core SC000
    • +
  • SC300: ARM Secure Core SC300
    • +
  • other: other processor architectures
    • +
+		cpuNameType 1..1
revisionType Defines the HW revision of the processor. The defined version format is rNpM (N,M = [0 - 9]). revisionType 1..1
endian Defines the endianess of the processor being one of:
    +
  • little: little endian memory (least significant byte gets allocated at the lowest address).
    • +
  • big: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).
    • +
  • selectable: little and big endian are configurable for the device and become active after the next reset.
    • +
  • other: the endianess is neither little nor big endian.
    • +
+		endianType 1..1
mpuPresent Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to true or false, 1 or 0. boolean 1..1
fpuPresent Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to true or false, 1 or 0. boolean 1..1
vtorPresent This is an optional flag used for the Cortex-M0+ based devices only. It indicates whether the Vector Table Offset Register (VTOR) is implemented in the Cortex-M0+ device or not. This tag is either set to true or false, 1 or 0. If it is not specified VTOR is assumed to be present. boolean 1..1
nvicPrioBits Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. scaledNonNegativeInteger 1..1
vendorSystickConfig Indicates whether the processor implements a vendor-specific System Tick Timer. If false, then the ARM defined System Tick Timer is available. If true, then a vendor-specific System Tick Timer must be implemented. This tag is either set to true or false, 1 or 0. boolean 1..1
+

+Example:

+
...
+
<cpu>
+
<name>CM4</name>
+
<revision>r0p0</revision>
+
<endian>little</endian>
+
<mpuPresent>true</mpuPresent>
+
<fpuPresent>true</fpuPresent>
+
<nvicPrioBits>4</nvicPrioBits>
+
<vendorSystickConfig>false</vendorSystickConfig>
+
</cpu>
+
...
+

This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM.

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html new file mode 100644 index 000000000..efa548ef1 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html @@ -0,0 +1,149 @@ + + + + + +CMSIS-SVD: Extensions to the Device Section + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Extensions to the Device Section
SVD Extension in Version 1.1
+
+
+

A number of elements have been added to the device section. These elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.

+
+<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+    <vendor>stringType</vendor>
+    <vendorID>stringType</vendorID>
+    <name>identifierType</name>
+    <series>stringType</series>
+    <version>xs:string</version>
+    <description>xs:string</description>
+    <licenseText>xs:string</licenseText>
+    <cpu>cpuType</cpu>
+    <headerSystemFilename>identifierType</headerSystemFilename>
+    <headerDefinitionsPrefix>identifierType</headerDefinitionsPrefix>
+
+    ...
+</device>
+
+
+ + + + + + + + + + + + + + +
Element Name Description Type Occurrence
vendor This specifies the vendor of the device using the full name. stringType 0..1
vendorID This specifies the vendor of the device using the vendor abbreviation that does not contain any spaces or special characters. This information shall be used for defining the directory. stringType 0..1
series This element specifies the name of the device series. stringType 0..1
licenseText The content of this tag will be copied into the header section of the generated device header file and shall contain the legal disclaimer. New lines can be inserted by using "\n". This section is mandatory if the SVD file shall be used for generating the device header file. stringType 0..1
headerSystemFilename This tag specifies the file name (without extension) of the device-specific system include file (system_<device>.h; See CMSIS-Core description). This tag is used by the header file generator for customizing the include statement referencing the CMSIS system file within the CMSIS device header file. By default, the filename is "<kbd>system_<i>device:name</i>.h". In cases where a device series shares a single system header file, the name of the series shall be used instead of the individual device name. identifierType 0..1
headerDefinitionsPrefix The element specifies the string being prepended to all type definition names generated in the CMSIS-Core device header file. This is used if the silicon vendor's software requires vendor-specific types in order to avoid name clashes with other definied types. identifierType 0..1
+

+Example:

+
...
+
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+
<vendor>Advanced RISC Machines</vendor>
+
<vendorID>ARM</vendorID>
+
...
+
<series>ARMCM3</series>
+
...
+
<licenseText>
+
ARM Limited (ARM) is supplying this software for use with Cortex-M \n
+
processor based microcontrollers. This file can be freely distributed \n
+
within development tools that are supporting such ARM based processors. \n
+
\n
+
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED \n
+
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \n
+
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. \n
+
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR \n
+
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
</licenseText>
+
...
+
<headerSystemFilename>system_ARMCM4</headeSystemFilename>
+
<headerDefinitionsPrefix>ARM_</headerDefinitionsPrefix>
+
...
+
</device>
+
...
+

This example describes a device from the vendor Advanced RISC Machines using ARM as short name. The device belongs to the device family identified by ARMCM4. The legal disclaimer in the header files generated from this description is captured and formatted in accordance to the standard ARM CMSIS disclaimer. The CMSIS system file included by the generated device header file is named system_ARMCM4.h and all type definitions will be prepended with ARM_.

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html new file mode 100644 index 000000000..30d18fb97 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html @@ -0,0 +1,120 @@ + + + + + +CMSIS-SVD: dimElementGroup + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
dimElementGroup
Element Groups
+
+
+

The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index-specific substring defined in <dimIndex>. The <dimIncrement> specifies the address offset between two registers. The elements below can be used to generate an array of registers.

+ + + + + + + + + +
Element Name Description Type Occurrence
dim The value defines the number of elements in an array of registers. scaledNonNegativeInteger 1..1
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger 1..1
dimIndex Specifies the substrings that replaces the %s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register. dimIndexType 0..1
+

+Examples:

+
...
+
<register>
+
<dim>6</dim>
+
<dimIncrement>4</dimIncrement>
+
<dimIndex>A,B,C,D,E,Z</dimIndex>
+
<name>GPIO_%s_CTRL</name>
+
...
+
</register>
+

The code above generates: => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, GPIO_Z_CTRL

+
...
+
<register>
+
<dim>4</dim>
+
<dimIncrement>4</dimIncrement>
+
<dimIndex>3-6</dimIndex>
+
<name>IRQ%s</name>
+
...
+
</register>
+

The example above generates: => IRQ3, IRQ4, IRQ5, IRQ6

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html new file mode 100644 index 000000000..5c3d47a2f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html @@ -0,0 +1,100 @@ + + + + + +CMSIS-SVD: Element Groups + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+Content
+
+
Element Groups
+
+
+ + + + + + +

+Content

 dimElementGroup
 
 registerPropertiesGroup
 
+

Description

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.js new file mode 100644 index 000000000..816ec4a02 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.js @@ -0,0 +1,5 @@ +var group__elem__type__gr = +[ + [ "dimElementGroup", "group__dim_element_group__gr.html", null ], + [ "registerPropertiesGroup", "group__register_properties_group__gr.html", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html new file mode 100644 index 000000000..e6d3be0b3 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html @@ -0,0 +1,116 @@ + + + + + +CMSIS-SVD: Extensions to the Peripheral Section + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Extensions to the Peripheral Section
SVD Extension in Version 1.1
+
+
+

The following elements have been added to the peripheral section. All new elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.

+ + + + + + + +
Element Name Description Type Occurrence
alternatePeripheral All address blocks in the memory space of a device are assigned to a unique peripheral by default. If there are multiple peripherals describing the same address blocks, this needs to be specified explicitly. A peripheral redefining an address block needs to specify the name of the peripheral that is listed first in the description. If no alternate peripheral is specified, then the SVDConv utility will generate errors. identifierType 0..1
headerStructName The header file generator uses the name of a peripheral as the base name for the C structure type. If this element is specfied, then this string is used instead of the peripheral name. This is particularly useful when multiple peripherals get derived from a peripheral description and a generic type name shall be used. identifierType 0..1
+

+Example:

+
<peripheral>
+
<name>Timer1</name>
+
<version>1.0</version>
+
<description>Timer 1 is a standard timer ... </description>
+
<baseAddress>0x40002000</baseAddress>
+
...
+
</peripheral>
+
<peripheral>
+
<name>Timer1_Alt</name>
+
<version>1.0</version>
+
<description>Alternate Timer 1 is a special timer execution mode ... </description>
+
<baseAddress>0x40002000</baseAddress>
+
<alternatePeripheral>Timer1</alternatePeripheral>
+
...
+
</peripheral>
+

Two timer peripheral descriptions are specified for the same memory block. No redefined addresses will be reported for both peripherals.

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html new file mode 100644 index 000000000..f27d1e274 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html @@ -0,0 +1,111 @@ + + + + + +CMSIS-SVD: registerPropertiesGroup + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
registerPropertiesGroup
Element Groups
+
+
+

Register properties can be set on device, peripheral, and register level. Element values defined on a lower level overwrite element values defined on a more general level. For example, the register-level.<size> will overwrite peripheral-level.<size>. Elements that have not been defined on a more general level, must be defined at register level at the latest.

+ + + + + + + + + + + +
Element Name Description Type Occurrence
size Defines the default bit-width of any register contained in the device (implicit inheritance). This element can be redefined on any lower level of the description using the size element there. scaledNonNegativeInteger 0..1
access Defines the default access rights for all registers. Access rights can be redefined on any lower level of the description using the access element there.
+
+ The predefined tokens are:
    +
  • read-only: read access is permitted. Write operations have an undefined result.
    • +
  • write-only: write access is permitted. Read operations have an undefined result.
    • +
  • read-write: both read and write accesses are permitted. Writes affect the state of the register and reads return a value related to the register.
    • +
  • writeOnce: only the first write after reset has an effect on the register. Read operations deliver undefined results.
    • +
  • read-writeOnce: Read operations deliver a result related to the register content. Only the first write access to this register after a reset will have an effect on the register content.
    • +
+		accessType 0..1
resetValue Defines the default value for all registers at RESET. The default register value can be redefined on any lower level using the resetValue element there. The actual reset value is calculated from the resetValue and the resetMask. The mask is used to specify bits with an undefined reset value. scaledNonNegativeInteger 0..1
resetMask Identifies which register bits have a defined reset value. These bit positions are set to one. Bit positions with an undefined reset value are set to zero. scaledNonNegativeInteger 0..1
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html new file mode 100644 index 000000000..e4fdd3085 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html @@ -0,0 +1,146 @@ + + + + + +CMSIS-SVD: Extensions to the Register Section + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Extensions to the Register Section
SVD Extension in Version 1.1
+
+
+

The following elements have been added to the register section. All new elements are optional.

+ + + + + + + +
Element Name Description Type Occurrence
alternateRegister This tag can reference a register that has been defined above to current location in the description and that describes the memory location already. This tells the SVDConv's address checker that the redefinition of this particular register is intentional. The register name needs to be unique within the scope of the current peripheral. A register description is defined either for a unique address location or could be a redefinition of an already described address. In the latter case, the register can be either marked alternateRegister and needs to have a unique name, or it can have the same register name but is assigned to a register subgroup through the tag alternateGroup (specified in version 1.0). identifierType 0..1
dataType It can be useful to assign a specific native C datatype to a register. This helps avoiding type casts. For example, if a 32 bit register shall act as a pointer to a 32 bit unsigned data item, then dataType can be set to "uint32_t *". The following simple data types are predefined:
    +
  • uint8_t: unsigned byte
    • +
  • uint16_t: unsigned half word
    • +
  • uint32_t: unsigned word
    • +
  • uint64_t: unsigned double word
    • +
  • int8_t: signed byte
    • +
  • int16_t: signed half word
    • +
  • int32_t: signed world
    • +
  • int64_t: signed double word
    • +
  • uint8_t *: pointer to unsigned byte
    • +
  • uint16_t *: pointer to unsigned half word
    • +
  • uint32_t *: pointer to unsigned word
    • +
  • uint64_t *: pointer to unsigned double word
    • +
  • int8_t *: pointer to signed byte
    • +
  • int16_t *: pointer to signed half word
    • +
  • int32_t *: pointer to signed world
    • +
  • int64_t *: pointer to signed double word
    • +
+		dataTypeType 0..1
+

+Example:

+
...
+
<register>
+
<name>TIM_MODEA</name>
+
<description>In mode A this register acts as a reload value</description>
+
<addressOffset>0xC</addressOffset>
+
</register>
+
<register>
+
<name>TIM_MODEB</name>
+
<description>In mode B this register acts as the compare value</description>
+
<alternateRegister>TIM_MODEA</alternateRegister>
+
<addressOffset>0xC</addressOffset>
+
</register>
+
<register>
+
<name>DMA_DATA</name>
+
<description>This register contains the address of the data being transferred</description>
+
<dataType>uint32_t *</dataType>
+
<addressOffset>0xf0</addressOffset>
+
</register>
+
...
+

This example describes two registers, TIM_MODEA and TIM_MODEB. Both have the same address offset. Based on the configured operation model being A or B, the register acts as reload or compare value. The register DMA_DATA is specified as a pointer to unsigned word data. The code generated for the device header file is:

+
typedef struct {
+
union {
+
__IO uint32_t TIM_MODEA;
+
__IO uint32_t TIM_MODEB;
+
};
+
__IO uint32_t * DMA_DATA;
+
...
+
} <peripheral:name>_Type;
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html new file mode 100644 index 000000000..943f13819 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html @@ -0,0 +1,612 @@ + + + + + +CMSIS-SVD: CMSIS-SVD Schema File Ver. 1.1 (draft) + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
CMSIS-SVD Schema File Ver. 1.1 (draft)
+
+
+
<?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  date: 04.07.2012
+
+  Copyright (C) 2011 - 2012 ARM Limited. All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used 
+     to endorse or promote products derived from this software without 
+     specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+
+  This is CMSIS-SVD version 1.1
+  For backward compatibility all additional tags have been made optional.
+  Extensions may be mandatory for successful device header file generation
+  Other changes are related to some restructuring of the schema.
+  
+  Note that the memory section has been removed since this would limit the
+  reuse of descriptions for a series of devices.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.1">
+  <!-- stringType requires a none empty string of a least one character length -->
+  <xs:simpleType name="stringType">
+    <xs:restriction base="xs:string">
+      <xs:minLength value="1"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->
+  <xs:simpleType name="cpuNameType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="CM0"/>
+      <xs:enumeration value="CM0PLUS"/>
+      <xs:enumeration value="CM0+"/>
+      <xs:enumeration value="SC000"/>
+      <xs:enumeration value="CM3"/>
+      <xs:enumeration value="SC300"/>
+      <xs:enumeration value="CM4"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) -->
+  <xs:simpleType name="revisionType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="r[0-9]p[0-9]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- EndianType pre-defines the tokens for specifying the endianess of the device -->
+  <xs:simpleType name="endianType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="little"/>
+      <xs:enumeration value="big"/>
+      <xs:enumeration value="selectable"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- dataType pre-defines the tokens in line with CMSIS data type definitions -->
+  <xs:simpleType name="dataTypeType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="uint8_t"/>
+      <xs:enumeration value="uint16_t"/>
+      <xs:enumeration value="uint32_t"/>
+      <xs:enumeration value="uint64_t"/>
+      <xs:enumeration value="int8_t"/>
+      <xs:enumeration value="int16_t"/>
+      <xs:enumeration value="int32_t"/>
+      <xs:enumeration value="int64_t"/>
+      <xs:enumeration value="uint8_t *"/>
+      <xs:enumeration value="uint16_t *"/>
+      <xs:enumeration value="uint32_t *"/>
+      <xs:enumeration value="uint64_t *"/>
+      <xs:enumeration value="int8_t *"/>
+      <xs:enumeration value="int16_t *"/>
+      <xs:enumeration value="int32_t *"/>
+      <xs:enumeration value="int64_t *"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- nvicPrioBitsType specifies the integer value range for the number of bits used in NVIC to encode priority levels -->
+  <xs:simpleType name="nvicPrioBitsType">
+    <xs:restriction base="xs:integer">
+      <xs:minInclusive value="2"/>
+      <xs:maxInclusive value="8"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- identifierType specifies the subset and sequence of characters used for specifying identifiers within the description. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="identifierType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumerationNameType specifies the subset and sequence of characters used for specifying names of enumeratedValues. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="enumerationNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[_A-Za-z0-9]*"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays -->
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimar format -->
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues -->
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- accessType specfies the pre-defined tokens for the available accesses -->
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects -->
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- readAction type specifies the pre-defined tokens for read side effects -->
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with -->
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 -->
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-4])?[0-9]:([0-4])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource -->
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+  <!-- addressBlockType specifies the elements to describe an address block -->
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- interruptType specifies how to describe an interrupt associated with a peripheral -->
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="stringType"/>
+      <xs:element name="description" type="xs:string" minOccurs="0"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- register properties group specifies register size, access permission and reset value 
+       this is used in multiple locations. Settings are inherited downstream. -->  
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register 
+       by specifying the least significant and the most significant bit position -->
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register
+       by specifying the least significant bit position and the bitWidth of the field -->
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+  <!-- dimElementGroup specifies the number of array elements (dim), the address offset
+       between to consecutive array elements and an a comma seperated list of strings 
+       being used for identifying each element in the array -->
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:complexType name="cpuType">
+    <xs:sequence>
+      <!-- V1.1: ARM processor name: Cortex-Mx / SCxxx -->
+      <xs:element name="name" type="cpuNameType"/>
+      <!-- V1.1: ARM defined revision of the cpu -->
+      <xs:element name="revision" type="revisionType"/>
+      <!-- V1.1: Endian specifies the endianess of the processor/device -->
+      <xs:element name="endian" type="endianType"/>
+      <!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->
+      <xs:element name="mpuPresent" type="xs:boolean"/>
+      <!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present -->
+      <xs:element name="fpuPresent" type="xs:boolean"/>
+      <!-- V1.1: vtorPresent is used for Cortex-M0+ based devices only. It indicates whether the Vector Table Offset
+                 Register is implemented in the device or not -->				   
+      <xs:element name="vtorPresent" type="xs:boolean" minOccurs="0"/>
+      <!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller
+                 for defining the priority level = # priority levels -->
+      <xs:element name="nvicPrioBits" type="scaledNonNegativeInteger"/>
+      <!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device 
+                   instead of the ARM specified SysTickTimer -->
+      <xs:element name="vendorSystickConfig" type="xs:boolean"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="enumeratedValuesType">
+    <xs:sequence>
+      <!-- name specfies a reference to this enumeratedValues section for reuse purposes
+           this name does not appear in the System Viewer nor the Header File. -->
+      <xs:element name="name" type="enumerationNameType" minOccurs="0"/>
+      <!-- usage specifies whether this enumeration is to be used for read or write or 
+                                                       (read and write) accesses -->
+      <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+      <!-- enumeratedValue derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+        <xs:complexType>
+          <xs:sequence>
+            <!-- name is a ANSI C indentifier representing the value (C Enumeration) -->
+            <xs:element name="name" type="enumerationNameType"/>
+            <!-- description contains the details about the semantics/behavior specified by this value -->
+            <xs:element name="description" type="stringType" minOccurs="0"/>
+            <xs:choice>
+              <xs:element name="value" type="enumeratedValueDataType"/>
+              <!-- isDefault specifies the name and description for all values that are not
+                   specifically described individually -->
+              <xs:element name="isDefault" type="xs:boolean"/>
+            </xs:choice>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="enumerationNameType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldType">
+    <xs:sequence>
+      <!-- name specifies a field's name. The System Viewer and the device header file will
+           use the name of the field as identifier -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- description contains reference manual level information about the function and 
+           options of a field -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- alternative specifications of the bit position of the field within the register -->
+      <xs:choice minOccurs="1" maxOccurs="1">
+        <!-- bit field described by lsb followed by msb tag -->
+        <xs:group ref="bitRangeLsbMsbStyle"/>
+        <!-- bit field described by bit offset relative to Bit0 + bit width of field -->
+        <xs:group ref="bitRangeOffsetWidthStyle"/>
+        <!-- bit field described by [<msb>:<lsb>] -->
+        <xs:element name="bitRange" type="bitRangeType"/>
+      </xs:choice>
+      <!-- access describes the predefined permissions for the field. -->
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <!-- predefined description of write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeContstraint specifies the subrange of allowed values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAction specifies the read side effects. -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- enumeratedValues derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValues" type="enumeratedValuesType" minOccurs="0" maxOccurs="2">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldsType">
+    <xs:sequence>
+      <!-- field derivedFrom=<identifierType> -->
+      <xs:element name="field" type="fieldType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="registerType">
+    <xs:sequence>
+      <xs:group    ref="dimElementGroup" minOccurs="0"/>
+      <!-- name specifies the name of the register. The register name is used by System Viewer and
+                                     device header file generator to represent a register -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- display name specifies a register name without the restritions of an ANSIS C identifier.
+                                     The use of this tag is discouraged because it does not allow consistency between
+                                     the System View and the device header file. -->
+      <xs:element name="displayName" type="stringType" minOccurs="0"/>
+      <!-- description contains a reference manual level description about the register and it's purpose -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <xs:choice>
+        <!-- alternateGroup specifies the identifier of the subgroup a register belongs to.
+                                       This is useful if a register has a different description per mode but a single name -->
+        <xs:element name="alternateGroup" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: alternateRegister specifies an alternate register description for an address that is
+                                       already fully described. In this case the register name must be unique within the peripheral -->
+        <xs:element name="alternateRegister" type="identifierType" minOccurs="0"/>
+      </xs:choice>
+      <!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral -->
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                                     reset value. These default values are inherited to all fields contained in this register -->
+      <xs:group    ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) -->
+      <xs:element name="dataType" type="dataTypeType" minOccurs="0"/>
+      <!-- modifiedWriteValues specifies the write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeConstraint specifies the subset of allowed write values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAcction specifies the read side effects -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- fields section contains all fields that belong to this register -->
+      <xs:element name="fields" type="fieldsType" minOccurs="0" maxOccurs="1"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file -->
+  <xs:complexType name="clusterType">
+    <xs:sequence>
+      <xs:group   ref="dimElementGroup" minOccurs="0"/>
+      <xs:element name="name" type="identifierType"/>
+      <xs:element name="description" type="xs:string"/>
+      <!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is
+                 already fully described. In this case the cluster name must be unique within the peripheral -->
+      <xs:element name="alternateCluster" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the cluster structure typedef
+                 used in the device header generation instead of the cluster name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="register" type="registerType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- the registers section can have an arbitrary list of cluster and register sections -->
+  <xs:complexType name="registersType">
+    <xs:choice minOccurs="1" maxOccurs="unbounded">
+      <xs:element name="cluster" type="clusterType"/>
+      <xs:element name="register" type="registerType"/>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="peripheralType">
+    <xs:sequence>
+      <!-- name specifies the name of a peripheral. This name is used for the System View and device header file -->
+      <xs:element name="name" type="xs:Name"/>
+      <!-- version specifies the version of the peripheral descriptions -->
+      <xs:element name="version" type="stringType" minOccurs="0"/>
+      <!-- description provides a high level functional description of the peripheral -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is
+           already fully by a peripheral described. In this case the peripheral name must be unique within the device description -->
+      <xs:element name="alternatePeripheral" type="identifierType" minOccurs="0"/>
+      <!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->
+      <xs:element name="groupName" type="xs:Name" minOccurs="0"/>
+      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral. 
+                         The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->
+      <xs:element name="prependToName" type="identifierType" minOccurs="0"/>
+      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header 
+                         file will sho the registers in a C-Struct of the peripheral without the postfix -->
+      <xs:element name="appendToName" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the peripheral structure typedef
+                         used in the device header generation instead of the peripheral name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <!-- disableCondition contains a logical expression based on constants and register or bit-field values 
+                         if the condition is evaluated to true, the peripheral display will be disabled -->
+      <xs:element name="disableCondition" type="stringType" minOccurs="0"/>
+      <!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory
+                         to specify a baseAddress. -->
+      <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                         reset value. These default values are inherited to all registers contained in this peripheral -->
+      <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral. 
+                         derived peripherals may have no addressBlock, however none-derived peripherals are required to specify
+                         at least one address block -->
+      <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- interrupt specifies can specify one or more interrtupts by name, description and value -->
+      <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does
+                        not have its own registers section, hence this section is optional. A unique peripheral without a 
+                        registers section is not allowed -->
+      <xs:element name="registers" type="registersType" minOccurs="0" maxOccurs="1">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+  
+  <!-- ==================================================== -->
+  <!-- The top level element of a description is the device -->
+  <!-- ==================================================== -->
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <!-- V1.1: Vendor Name -->
+        <xs:element name="vendor" type="stringType" minOccurs="0"/>
+        <!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) -->
+        <xs:element name="vendorID" type="identifierType" minOccurs="0"/>
+        <!-- name specifies the device name being described -->
+        <xs:element name="name" type="identifierType"/>
+        <!-- V1.1: series specifies the device series or family name -->
+        <xs:element name="series" type="stringType" minOccurs="0"/>
+        <!-- version specifies the version of the device description -->
+        <xs:element name="version" type="stringType"/>
+        <!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) -->
+        <xs:element name="description" type="stringType"/>
+        <!-- V1.1: licenseText specifies the file header section to be included in any derived file -->
+        <xs:element name="licenseText" type="stringType" minOccurs="0"/>
+        <!-- V1.1: cpu specifies the details of the processor included in the device -->
+        <xs:element name="cpu" type="cpuType" minOccurs="0"/>
+        <!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.
+             This tag is used by the header file generator for customizing the include statement referencing the
+             CMSIS system file within the CMSIS device header file. By default the filename is "system_<device.name>"
+             In cases a device series shares a single system header file, the name of the series shall be used 
+             instead of the individual device name. -->
+        <xs:element name="headerSystemFilename" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in
+             generated device header file -->
+        <xs:element name="headerDefinitionsPrefix" type="identifierType" minOccurs="0"/>
+        <!-- addressUnitBits specifies the size of the minimal addressable unit in bits -->
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.
+             This sets the maximum size of a single register that can be defined for an address space -->
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+             reset value -->
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+
+        <!-- peripherals is containing all peripherals -->
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" type="peripheralType" minOccurs="1" maxOccurs="unbounded"/>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+
+        <!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default -->
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.1"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html new file mode 100644 index 000000000..ef1b98fba --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html @@ -0,0 +1,375 @@ + + + + + +CMSIS-SVD: CMSIS-SVD Schema File Ver. 1.0 + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
CMSIS-SVD Schema File Ver. 1.0
+
+
+
<?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  date: 07.12.2011
+  
+  Copyright (C) 2011 - 2012 ARM Limited. All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used 
+     to endorse or promote products derived from this software without 
+     specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0">
+  
+  <xs:simpleType name="registerNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-3])?[0-9]:([0-3])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="xs:string"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <xs:element name="name" type="xs:string"/>
+        <xs:element name="version" type="xs:string"/>
+        <xs:element name="description" type="xs:string"/>
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded">
+                <xs:complexType>
+                  <xs:sequence>
+                    <xs:element name="name" type="xs:Name"/>
+                    <xs:element name="version" type="xs:string" minOccurs="0"/>
+                    <xs:element name="description" type="xs:string" minOccurs="0"/>
+                    <xs:element name="groupName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="prependToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="appendToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="disableCondition" type="xs:string" minOccurs="0"/>
+                    <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+                    <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                    <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="registers" minOccurs="0" maxOccurs="1">
+                      <xs:complexType>
+                        <xs:sequence>
+                          <xs:element name="register" minOccurs="1" maxOccurs="unbounded">
+                            <xs:complexType>
+                              <xs:sequence>
+                                <xs:group ref="dimElementGroup" minOccurs="0"/>
+                                <xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
+                                <xs:element name="displayName" type="xs:string" minOccurs="0"/>
+                                <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                <xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/>
+                                <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+                                <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                                <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                <xs:element name="fields" minOccurs="0" maxOccurs="1">
+                                  <xs:complexType>
+                                    <xs:sequence>
+                                      <xs:element name="field" minOccurs="1" maxOccurs="unbounded">
+                                      <xs:complexType>
+                                        <xs:sequence>
+                                          <xs:element name="name" type="xs:string"/>
+                                          <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                          <xs:choice>
+                                            <xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/>
+                                            <xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/>
+                                            <xs:element name="bitRange" type="bitRangeType" minOccurs="0"/>
+                                          </xs:choice>
+                                          <xs:element name="access" type="accessType" minOccurs="0"/>
+                                          <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                          <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                          <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                          <xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2">
+                                            <xs:complexType>
+                                              <xs:sequence>
+                                                <xs:element name="name" type="xs:Name" minOccurs="0"/>
+                                                <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+                                                <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+                                                  <xs:complexType>
+                                                    <xs:sequence>
+                                                      <xs:element name="name" type="xs:string"/>
+                                                      <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                                      <xs:choice>
+                                                        <xs:element name="value" type="enumeratedValueDataType"/>
+                                                        <xs:element name="isDefault" type="xs:boolean"/>
+                                                      </xs:choice>
+                                                    </xs:sequence>
+                                                  </xs:complexType>
+                                                </xs:element>
+                                              </xs:sequence>
+                                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                            </xs:complexType>
+                                          </xs:element>
+                                        </xs:sequence>
+                                        <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                      </xs:complexType>
+                                    </xs:element>
+                                    </xs:sequence>
+                                  </xs:complexType>
+                                </xs:element>
+                              </xs:sequence>
+                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                            </xs:complexType>
+                          </xs:element>
+                        </xs:sequence>
+                      </xs:complexType>
+                    </xs:element>
+                  </xs:sequence>
+                  <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                </xs:complexType>
+              </xs:element>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html new file mode 100644 index 000000000..a8214c87f --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html @@ -0,0 +1,107 @@ + + + + + +CMSIS-SVD: SVD Extension in Version 1.1 + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+Content
+
+
SVD Extension in Version 1.1
+
+
+ + + + + + + + + + + + +

+Content

 Extensions to the Device Section
 
 CPU Section (New)
 
 Extensions to the Peripheral Section
 
 Cluster Level (New)
 
 Extensions to the Register Section
 
+

Description

+

From a schema perspective, CMSIS-SVD Version 1.1 is fully backward compatible to version 1.0. Many of the features added in version 1.1 are required for generating CMSIS-Core device header files from a CMSIS SVD description. It is expected that over time all CMSIS-SVD descriptions will comply with version 1.1. Version 1.1 has not been finalized yet and is therefore currently marked draft.

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.js new file mode 100644 index 000000000..9c46ce6cd --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.js @@ -0,0 +1,8 @@ +var group__svd___format__1__1__gr = +[ + [ "Extensions to the Device Section", "group__device_section_extensions__gr.html", null ], + [ "CPU Section (New)", "group__cpu_section__gr.html", null ], + [ "Extensions to the Peripheral Section", "group__peripheral_section_extensions__gr.html", null ], + [ "Cluster Level (New)", "group__cluster_level__gr.html", null ], + [ "Extensions to the Register Section", "group__register_section_extensions__gr.html", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html new file mode 100644 index 000000000..f2b30d9af --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html @@ -0,0 +1,139 @@ + + + + + +CMSIS-SVD: SVD File Schema Levels + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+Content
+
+
SVD File Schema Levels
+
+
+ + + + + + + + + + + + +

+Content

 Device Level
 
 Peripherals Level
 
 Registers Level
 
 Fields Level
 
 Enumerated Values Level
 
+

Description

+

This section specifies the SVD file format Version 1.0. Each subsection defines one level of hierarchy and lists all mandatory and optional language elements as well as their type. A brief example description snippet demonstrates the usage of the elements.

+
Note
    +
  • The sequence of elements in CMSIS-SVD is mandatory.
    • +
  • Optional elements are highlighted in green.
    • +
  • Mandatory elements are highlighted in blue. Optional sections can contain mandatory elements, which must be specified when the optional section is used. In this case the mandatory elements are also highlighted in blue.
    • +
+
+

+Names

+

All name tags must comply with the ANSI C identifier naming restrictions (identifierType). In particular they must not contain any spaces or special characters. This is necessary to support the generation of device header files thus providing consistency between the names being shown by the debugger and the symbols being used in the CMSIS compliant target software.

+

+Constants

+

Number constants shall be entered in hexadecimal, decimal, or binary format.

+
    +
  • The Hexadecimal format is indicated by a leading "0x".
    • +
  • The Binary format is indicated by a leading "#".
    • +
  • All other formats are interpreted as decimal numbers.
    • +
  • The value tag in enumeratedValue accepts do not care bits represented by "x".
    • +
+

+Comments

+

Comments have the standard XML format.

+
    +
  • Start a comment with "<!–".
    • +
  • End a comment with "–>".
    • +
+

+Empty Tags

+
    +
  • Single tags are not supported (for example, <name>).
    • +
  • The tag content must not consist of an empty string (instead, omit optional tags).
    • +
+
Remarks
The CMSIS-SVD Schema File Ver. 1.0 and schema_1_1_gr are provided alongside this document.
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.js b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.js new file mode 100644 index 000000000..7ee06759b --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.js @@ -0,0 +1,8 @@ +var group__svd___format__gr = +[ + [ "Device Level", "group__svd__xml__device__gr.html", null ], + [ "Peripherals Level", "group__svd__xml__peripherals__gr.html", null ], + [ "Registers Level", "group__svd__xml__registers__gr.html", null ], + [ "Fields Level", "group__svd__xml__fields__gr.html", null ], + [ "Enumerated Values Level", "group__svd__xml__enum__gr.html", null ] +]; \ No newline at end of file diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html new file mode 100644 index 000000000..52cec3f03 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html @@ -0,0 +1,173 @@ + + + + + +CMSIS-SVD: Device Level + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Device Level
SVD File Schema Levels
+
+
+
<p>The element <b>device</b> provides the outermost frame of the description. 
+- Only one device section is allowed per file. All other elements like peripherals, registers, 
+fields, enumerated values, and vendor extensions are described within this scope. 
+- A device contains one or more peripherals. 
+- Optional elements like size, access, resetValue, and resetMask defined on this level are used 
+as default values throughout the device description, unless they get redefined at a lower level.
+    </p> 
+
+
+<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
    <name>identifierType</name>
+    <version>xs:string</version>
+    <description>xs:string</description>
+    <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>
+    <width>scaledNonNegativeInteger</width>
+
+    <!-- registerPropertiesGroup -->
+    <size>scaledNonNegativeInteger</size>
+    <access>accessType</access>
+    <resetValue>scaledNonNegativeInteger</resetValue>
+    <resetMask>scaledNonNegativeInteger</resetMask>
+    <!-- end of registerPropertiesGroup -->
+
+    <peripherals>
+        ...
+    </peripherals>
+
+    <vendorExtensions>
+        ...
+    </vendorExtensions>
</device>
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Attribute Name Description Type Occurrence
xmlns:xs Specifies the underlying XML schema to which the CMSIS-SVD schema is compliant. Has to be set to: "http://www.w3.org/2001/XMLSchema-instance". xs:decimal 1..1
xmlns:xs Specifies the file path and file name of the CMSIS-SVD Schema. For example, CMSIS-SVD_Schema_1_0.xsd. xs:string 1..1
schemaVersion Specifies the CMSIS-SVD schema version the description is compliant to (for example, 1.0). xs:decimal 1..1
Element Name Description Type Occurrence
name The name string is used to identify the device or device series. Device names are required to be unique. xs:string 1..1
version The string defines the version of the file. Silicon vendors maintain the description throughout the life-cycle of the device and ensure that all updated and released copies have a unique version string. Higher numbers indicate a more recent version. xs:string 1..1
description String for describing main features of a device (for example CPU, clock frequency, peripheral overview). xs:string 1..1
addressUnitBits Defines the number of data bits uniquely selected by each address. The value for Cortex-M based devices is 8 (byte-addressable). scaledNonNegativeInteger 1..1
width Defines the number of data bit-width of the maximum single data transfer supported by the bus infrastructure. This information is relevant for debuggers when accessing registers, because it might be required to issue multiple accesses for accessing a resource of a bigger size. The expected value for Cortex-M based devices is 32. scaledNonNegativeInteger 1..1
See registerPropertiesGroup for details.
size Defines the default bit-width of any register contained in the device (implicit inheritance). scaledNonNegativeInteger 0..1
access Defines the default access rights for all registers. accessType 0..1
resetValue Defines the default value for all registers at RESET. scaledNonNegativeInteger 0..1
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1
peripherals Next level of description. see Peripherals Level for details.   1..1
vendorExtensions The content and format of this section of the description is unspecified. Silicon vendors may choose to provide additional information. By default, this section is ignored for constructing the CMSIS files. It is up to the silicon vendor to specify a schema for this section. xs:anyType (restriction) 0..1
+

+Example:

+
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
+
<name>ARM_Cortex_M3</name>
+
<version>0.1</version>
+
<description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+
<addressUnitBits>8</addressUnitBits>
+
<width>32</width>
+
<size>32</size>
+
<access>read-write</access>
+
<resetValue>0</resetValue>
+
<resetMask>0xffffffff</resetMask>
+
+
<peripherals>
+
...
+
</peripherals>
+
</device>
+

The device description above is at version 0.1 and uniquely identifies the device by the name "ARM_Cortex_M3". The peripherals are memory mapped in a byte-addressable address space with a bus width of 32 bits. The default size of the registers contained in the peripherals is set to 32 bits. Unless redefined for specific peripherals, all registers or fields are read-write accessible. A reset value of 0, valid for all 32 bits as specified by the reset mask, is set for all registers unless redefined at a lower level.

+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html new file mode 100644 index 000000000..576bbd653 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html @@ -0,0 +1,193 @@ + + + + + +CMSIS-SVD: Enumerated Values Level + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Enumerated Values Level
SVD File Schema Levels
+
+
+
Enumerated Values

The concept of enumerated values creates a map between unsigned integers and an identifier string. In addition, a description string can be associated with each entry in the map.

+
+        0 <-> disabled -> "the clock source clk0 is turned off"
+        1 <-> enabled  -> "the clock source clk1 is running"
+

This information is used for generating an enum in the device header file. The debugger may use this information to display the identifier string as well as the description. Just like symbolic constants making source code more readable, the system view in the debugger becomes more instructive. The detailed description can provide reference manual level details within the debugger.

+
+
+
+<enumeratedValues derivedFrom="xs:Name">
+
+    <name>enumerationNameType</name>
+    <usage>usageType</usage>
+
+    <enumeratedValue>
+        ...
+    </enumeratedValue>
+
+    ...
+    <enumeratedValue>
+        ...
+    </enumeratedValue>
+
+</enumeratedValues>
+
+
+ + + + + + + + + + + + +
Attribute Name Description Type Occurrence
derivedFrom Makes a copy from a previously defined enumeratedValues section. No modifications are allowed. An enumeratedValues entry is referenced by its name. If the name is not unique throughout the description, it needs to be further qualified by specifying the associated field, register, and peripheral as required. For example: 
+        field:                           clk.dis_en_enum
+        register + field:                ctrl.clk.dis_en_enum
+        peripheral + register + field:   timer0.ctrl.clk.dis_en_enum
+
xs:Name 0..1
Element Name Description Type Occurrence
name Identifier for the whole enumeration section. xs:Name 0..1
usage Possible values are read, write, or read-write. This allows specifying two different enumerated values depending whether it is to be used for a read or a write access. If not specified, the default value read-write is used. enumUsageType 0..1
enumeratedValue Describes a single entry in the enumeration. The number of required items depends on the bit width of the associated field. See section below for details.   1..*
+
Enumerated Value

An enumeratedValue defines a map between an unsigned integer and a human readable string.

+
+ 
+
+<enumeratedValue>
    <name>identifierType</name>
+    <description>xs:string</description>
    <choice>
+        <value>scaledNonNegativeInteger</value>
+        <isDefault>xs:boolean</isDefault>
+    </choice>
</enumeratedValue>
+
+
+ + + + + + + + + + + + +
Element Name Description Type Occurrence
name String describing the semantics of the value. Can be displayed instead of the value. identifierType 0..1
description Extended string describing the value. xs:string 0..1
choice of 1..1
value Defines the constant of the bit-field that the name corresponds to. scaledNonNegativeInteger 0..1
isDefault Defines the name and description for all other values that are not listed explicitly. xs:boolean 0..1
+

+Example:

+
<enumeratedValues>
+
+
<name>TimerIntSelect</name>
+
<usage>read-write</usage>
+
+
<enumeratedValue>
+
<name>disabled</name>
+
<description>The clock source clk0 is turned off.</description>
+
<value>0</value>
+
</enumeratedValue>
+
+
<enumeratedValue>
+
<name>reserved</name>
+
<description>Reserved values. Do not use.</description>
+
<isDefault>true</isDefault>
+
</enumeratedValue>
+
+
</enumeratedValues>
+
<enumeratedValues>
+
+
<name>TimerIntSelect</name>
+
<usage>read-write</usage>
+
+
<enumeratedValue>
+
<name>disabled</name>
+
<description>Timer does not generate interrupts.</description>
+
<value>0</value>
+
</enumeratedValue>
+
+
<enumeratedValue>
+
<name>enabled</name>
+
<description>Timer generates interrupts.</description>
+
<isDefault>true</isDefault>
+
</enumeratedValue>
+
+
</enumeratedValues>
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html new file mode 100644 index 000000000..22329b1c7 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html @@ -0,0 +1,211 @@ + + + + + +CMSIS-SVD: Fields Level + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Fields Level
SVD File Schema Levels
+
+
+

All fields of a register are enclosed between the <fields> opening and closing tags

+

A bit-field has a name that is unique within the register. The position and size within the register is either described by the combination of the least significant bit's position (lsb) and the most significant bit's position (msb), or the lsb and the bit-width of the field. A field may define an enumeratedValue in order to make the display more intuitive to read.

+
+ 

+<fields>
    <field derivedFrom="identifierType">
        <name>xs:Name</name>
+        <description>xs:string</description>
        <choice>
+             <!-- bitRangeLsbMsbStyle --> 
+            <bitOffset>scaledNonNegativeInteger<bitOffset>
+            <bitWidth>scaledNonNegativeInteger</bitWidth>
+            or
+             <!-- bitRangeOffsetWidthStyle --> 
+            <lsb>scaledNonNegativeInteger</lsb> 
+            <msb>scaledNonNegativeInteger</msb>
+            or
+             <!-- bitRangePattern --> 
+            <bitRange>pattern</bitRange>
+        </choice>
+        
+        <access>accessType</access>
+        <modifiedWriteValues>writeValueType</modifiedWriteValues>
+        <writeConstraint>writeConstraintType</writeConstraint>
+        <readAction>readActionType</readAction>
        <enumeratedValues>
+            ...
+        </enumeratedValues>
    </field>
+    ...
+    <field>
+       ...
+    </field>
+    
+<fields>
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Attribute Name Description Type Occurrence
derivedFrom The field is cloned from a previously defined field with a unique name. xs:Name 0..1
Element Name Description Type Occurrence
name Name string used to identify the field. Field names must be unique within a register. xs:string 1..1
description String describing the details of the register. xs:string 0..1
Choice of Three options exist to describe the field's bit-range. The options are to be used mutually exclusive: 1..1
1. bitRangeLsbMsbStyle
bitOffset Value defining the position of the least significant bit of the field within the register it belongs to. scaledNonNegativeInteger 1..1
bitWidth Value defining the bit-width of the bitfield within the register it belongs to. scaledNonNegativeInteger 0..1
2. bitRangeOffsetWidthStyle
lsb Value defining the bit position of the least significant bit within the register it belongs to. scaledNonNegativeInteger 1..1
msb Value defining the bit position of the most significant bit within the register it belongs to. scaledNonNegativeInteger 1..1
3. bitRangePattern
bitRange A string in the format: "[<msb>:<lsb>]" bitRangeType 0..1
access Predefined strings can be used to define the allowed access types for this field: read-only, write-only, read-write, writeOnce, and read-writeOnce. Can be omitted if it matches the access permission set for the parent register. accessType 0..1
modifiedWriteValues Describe the manipulation of data written to a field. If not specified, the value written to the field is the value stored in the field. The other options are bitwise operations:
    +
  • oneToClear: write data bit of one shall clear (set to zero) the corresponding bit in the field.
    • +
  • oneToSet: write data bit of one shall set (set to one) the corresponding bit in the field.
    • +
  • oneToToggle: write data bit of one shall toggle (invert) the corresponding bit in the field.
    • +
  • zeroToClear: write data bit of zero shall clear (set to zero) the corresponding bit in the field.
    • +
  • zeroToSet: write data bit of zero shall set (set to one) the corresponding bit in the field.
    • +
  • zeroToToggle: write data bit of zero shall toggle (invert) the corresponding bit in the field.
    • +
  • clear: after a write operation all bits in the field are cleared (set to zero).
    • +
  • set: after a write operation all bits in the field are set (set to one).
    • +
  • modify: after a write operation all bit in the field may be modified (default).
    • +
+		modifiedWriteValuesType 0..1
writeConstraint Three options exist to set write-constraints: 0..1
1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1
2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1
3. range Consists of the following two elements:   0..1
minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1
maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1
readAction If set, it specifies the side effect following a read operation. If not set, the field is not modified after a read. The defined side effects are:
    +
  • clear: The field is cleared (set to zero) following a read operation.
    • +
  • set: The field is set (set to ones) following a read operation.
    • +
  • modify: The field is modified in some way after a read operation.
    • +
  • modifyExternal: One or more dependent resources other than the current field are immediately affected by a read operation (it is recommended that the field description specifies these dependencies). Debuggers are not expected to read this field location unless explicitly instructed by the user.
    • +
+		readActionType 0..1 register
enumeratedValues Next lower level of description. See section Enumerated Values Level for details.   0..2
+

+Example:

+
...
+
<field>
+
<name>TimerCtrl0_IntSel</name>
+
<description>Select interrupt line that is triggered by timer overflow.</description>
+
<bitOffset>1</bitOffset>
+
<bitWidth>3</bitWidth>
+
<access>read-write</access>
+
<resetValue>0x0</resetValue>
+
<modifiedWriteValues>oneToSet</modifiedWriteValues>
+
<writeConstraint>
+
<range>
+
<minimum>0</minimum>
+
<maximum>5</maximum>
+
</range>
+
</writeConstraint>
+
<readAction>clear</readAction>
+
+
<enumeratedValues>
+
...
+
</enumeratedValues>
+
</field>
+
...
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html new file mode 100644 index 000000000..25af95477 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html @@ -0,0 +1,218 @@ + + + + + +CMSIS-SVD: Peripherals Level + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Peripherals Level
SVD File Schema Levels
+
+
+

All peripherals of a device are enclosed within the tag <peripherals>. At least one peripheral has to be defined. Each peripheral is enclosed in the tag <peripheral>.

+
    +
  • Each peripheral describes all registers belonging to that peripheral.
    • +
  • The address range allocated by a peripheral is defined through one or more address blocks.
    • +
  • An address block and register addresses are specified relative to the base address of a peripheral. The address block information can be used for constructing a memory map for the device peripherals.
    • +
+
Remarks
The memory map does not contain any information about RAM, ROM, or FLASH memory.
+
+
+ <peripherals> 
    <peripheral derivedFrom=identifierType>
        <name>identifierType</name>
+        <version>xs:string</version>
+        <description>xs:string</description>
+    
+        <groupName>identifierType</groupName>
+        <prependToName>identifierType</prependToName>
+        <appendToName>identifierType</appendToName>
+        <disableCondition>xs:string</disableCondition>
+    
+        <baseAddress>scaledNonNegativeInteger</baseAddress>
+    
+         <!-- registerPropertiesGroup -->
+        <size>scaledNonNegativeInteger</size>
+        <access>accessType</access>
+        <resetValue>scaledNonNegativeInteger</resetValue>
+        <resetMask>scaledNonNegativeInteger</resetMask>
+         <!-- end of registerPropertiesGroup -->
+    
+        <addressBlock>
+            <offset>scaledNonNegativeInteger</offset>
+            <size>scaledNonNegativeInteger</size>
+            <usage>usageType</usage>
+        </addressBlock>
+        ...
+        <addressBlock>
+            <offset>scaledNonNegativeInteger</offset>
+            <size>scaledNonNegativeInteger</size>
+            <usage>usageType</usage>
+        </addressBlock>
+    
+        <interrupt>
+            <name>identifierType</name>
+            <value>scaledNonNegativeInteger</value>
+        </interrupt>
        <registers>
+            ...
+        </registers>
    </peripheral>
+    ...
+    <peripheral>
+       ...
+    </peripheral>
+    
+</peripherals>
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Attribute Name Description Type Occurrence
derivedFrom Specifies the name of a peripheral from which this peripheral will be derived. Values are inherit. Elements specified underneath will override inherited values. xs:Name 0..1
Element Name Description Type Occurrence
name The name string is used to identify the peripheral. Peripheral names are required to be unique for a device. The name needs to be an ANSI C identifier to allow header file generation. xs:Name 1..1
version The string specifies the version of this peripheral description. xs:string 0..1
description The string provides an overview of the purpose and functionality of the peripheral. xs:string 0..1
groupName xs:string 0..1
prependToName All register names of this peripheral have their names prefixed with this string. xs:string 0..1
appendToName All register names of this peripheral have their names suffixed with this string. xs:string 0..1
disableCondition Is a C-language compliant logical expression returning a TRUE or FALSE result. If TRUE, refreshing the display for this peripheral is disabled and related accesses by the debugger are suppressed.
+
+ Only constants and references to other registers contained in the description are allowed: <peripheral>-><register>-><field>, for example, (System->ClockControl->apbEnable == 0). The following operators are allowed in the expression [&&,||, ==, !=, >>, <<, &, |].
Attention
Use this feature only in cases where accesses from the debugger to registers of un-clocked peripherals result in severe debugging failures. SVD is intended to provide static information and does not include any run-time computation or functions. Such capabilities can be added by the tools, and is beyond the scope of this description language.
+		xs:string 0..1
baseAddress Lowest address reserved or used by the peripheral. scaledNonNegativeInteger 1..1
See registerPropertiesGroup for details.
size Defines the default bit-width of any register contained in the device (implicit inheritance). scaledNonNegativeInteger 0..1
access Defines the default access rights for all registers. accessType 0..1
resetValue Defines the default value for all registers at RESET. scaledNonNegativeInteger 0..1
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1
addressBlock Specifies an address range uniquely mapped to this peripheral. A peripheral must have at least one address block, but may allocate multiple distinct address ranges. If a peripheral is derived form another peripheral, the addressBlock is not mandatory. addressBlockType 1..*
offset Specifies the start address of an address block relative to the peripheral baseAddress. scaledNonNegativeInteger 1..1
size Specifies the number of addressUnitBits being covered by this address block. The end address of an address block results from the sum of baseAddress, offset, and (size - 1). scaledNonNegativeInteger 1..1
usage The following predefined values can be used: registers, buffer, or reserved. scaledNonNegativeInteger 1..1
interrupt A peripheral can have multiple associated interrupts. This entry allows the debugger to show interrupt names instead of interrupt numbers. interruptType 0..*
name The string represents the interrupt name. XS:string 1..1
value Is the enumeration index value associated to the interrupt. xs:integer 1..1
registers See Registers Level for details.   0..1
+

+Example:

+
...
+
<peripheral>
+
<name>Timer0</name>
+
<version>1.0.32</version>
+
<description>Timer 0 is a simple 16 bit timer counting down ... </description>
+
<baseAddress>0x40000000</baseAddress>
+
<addressBlock>
+
<offset>0x0</offset>
+
<size>0x400</size>
+
<usage>registers</usage>
+
</addressBlock>
+
<interrupt><name>TIM0_INT</name><value>34</value></interrupt>
+
<registers>
+
...
+
</registers>
+
</peripheral>
+
+
<peripheral derivedFrom="Timer0">
+
<name>Timer1</name>
+
<baseAddress>0x40000400</baseAddress>
+
</peripheral>
+
...
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html new file mode 100644 index 000000000..9b8352dec --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html @@ -0,0 +1,229 @@ + + + + + +CMSIS-SVD: Registers Level + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
Registers Level
SVD File Schema Levels
+
+
+

All registers of a peripheral are enclosed between the <registers> opening and closing tags.

+

The description of registers is the most essential part of the SVD description. The register's name, detailed description, and the address-offset relative to the peripheral base address are the mandatory elements. If the size, access, reset value, and reset mask have not been specified on the device or peripheral level, or if the default values need to be redefined locally, these fields become mandatory.

+

A register can represent a single value or can be subdivided into individual bit-fields of specific functionality and semantics. In schema-terms the fields section is optional, however, from a specification perspective, fields are mandatory when they are described in the device documentation.

+

The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index specific substring define in <dimIndex>. The <dimIncrement> specifies the address offset between two registers.

+
+
+<registers> 
    <register derivedFrom=identifierType>
+    
+        <!-- dimElementGroup --> 
+        <dim>scaledNonNegativeInteger</dim>
+        <dimIncrement>scaledNonNegativeInteger</dimIncrement>
+        <dimIndex>xs:string</dimIndex>
+        <!-- end of dimElementGroup --> 
+   
+        <name>identifierType</name>
+    
+        <displayName>xs:string</displayName>
+    
+        <description>xs:string</description>
+    
+        <alternateGroup>xs:Name</alternateGroup>
+    
+        <addressOffset>scaledNonNegativeInteger</addressOffset>
+    
+        <!-- registerPropertiesGroup --> 
+        <size>scaledNonNegativeInteger</size>
+        <access>accessType</access>
+        <resetValue>scaledNonNegativeInteger</resetValue>
+        <resetMask>scaledNonNegativeInteger</resetMask>
+        <!-- end of registerPropertiesGroup --> 
+    
+        <modifiedWriteValues>writeValueType</modifiedWriteValues>
+        <writeConstraint>writeConstraintType</writeConstraint>
+        <readAction>readActionType</readAction>
        <fields>
+            ...
+        </fields>
+    
+    </register>
+    ...
+    <register>
+        ...
+    </register>
+    
+<registers> 
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Attribute Name Description Type Occurrence
derivedFrom Specifies the name of the register from which to inherit the data. Elements being specified underneath will override the inherited values.
+Remarks: When deriving a register, it is mandatory to specify at least the name, the description, and the addressOffset. 		xs:Name 0..1
Element Name Description Type Occurrence
See dimElementGroup for details.
dimIncrement The value defines the number of elements in an array of registers. scaledNonNegativeInteger 1..1
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger 1..1
dimIndex Specifies the substrings that replaces the %s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register. dimIndexType 0..1
name Name string used to identify the register. Register names are required to be unique within the scope of a peripheral. registerNameType 1..1
displayName When specified, the string is being used by a graphical frontend to visualize the register. Otherwise the name element is displayed. The displayName may contain special characters and white spaces. The place holder s can be used and is replaced by the dimIndex substring. xs:string 0..1
description String describing the details of the register. xs:string 0..1
alternateGroup Specifies a group name associated with all alternate register that have the same name. At the same time, it indicates that there is a register definition allocating the same absolute address in the address space. xs:Name 0..1
addressOffset Value defining the address of the register relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1
See registerPropertiesGroup for details.
size Defines the default bit-width of any register contained in the device (implicit inheritance). scaledNonNegativeInteger 0..1
access Defines the default access rights for all registers. accessType 0..1
resetValue Defines the default value for all registers at RESET. scaledNonNegativeInteger 0..1
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1
modifiedWriteValues Element to describe the manipulation of data written to a register. If not specified, the value written to the field is the value stored in the field. The other options define bitwise operations:
    +
  • oneToClear: write data bits of one shall clear (set to zero) the corresponding bit in the register.
    • +
  • oneToSet: write data bits of one shall set (set to one) the corresponding bit in the register.
    • +
  • oneToToggle: write data bits of one shall toggle (invert) the corresponding bit in the register.
    • +
  • zeroToClear: write data bits of zero shall clear (set to zero) the corresponding bit in the register.
    • +
  • zeroToSet: write data bits of zero shall set (set to one) the corresponding bit in the register.
    • +
  • zeroToToggle: write data bits of zero shall toggle (invert) the corresponding bit in the register.
    • +
  • clear: after a write operation all bits in the field are cleared (set to zero).
    • +
  • set: after a write operation all bits in the field are set (set to one).
    • +
  • modify: after a write operation all bit in the field may be modified (default).
    • +
+		modifiedWriteValuesType 0..1
writeConstraint Three options exist to set write-constraints: 0..1
1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1
2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1
3. range Consists of the following two elements:   0..1
minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1
maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1
readAction If set, it specifies the side effect following a read operation. If not set, the register is not modified. The defined side effects are:
    +
  • clear: The register is cleared (set to zero) following a read operation.
    • +
  • set: The register is set (set to ones) following a read operation.
    • +
  • modify: The register is modified in some way after a read operation.
    • +
  • modifyExternal: One or more dependent resources other than the current register are immediately affected by a read operation (it is recommended that the register description specifies these dependencies). Debuggers are not expected to read this register location unless explicitly instructed by the user.
    • +
+		readActionType

0..1

+

+
fields Next lower level of description (see Fields Level for details). Not all registers are further divided into fields, therefore, this level is optional. In case a register is subdivided into bit fields, it should be reflected in the description. The device header file can only contain bit access macros and bit-field structures if this information is contained in the description.   0..1
+

+Example:

+
...
+
<register>
+
<name>TimerCtrl0</name>
+
<description>Timer Control Register</description>
+
<addressOffset>0x0</addressOffset>
+
<access>read-write</access>
+
<resetValue>0x00008001</resetValue>
+
<resetMask>0x0000ffff</resetMask>
+
<size>32</size>
+
<fields>
+
...
+
</fields>
+
</register>
+
+
<register derivedFrom="TimerCtrl0">
+
<name>TimerCtrl1</name>
+
<description>Derived Timer</description>
+
<addressOffset>0x4</addressOffset>
+
</register>
+
...
+
+
+ + + + diff --git a/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/index.html b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/index.html new file mode 100644 index 000000000..76eb85152 --- /dev/null +++ b/flight/pios/stm32f0x/libraries/CMSIS/Documentation/SVD/html/index.html @@ -0,0 +1,148 @@ + + + + + +CMSIS-SVD: System View Description + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-SVD +  Version 1.10 +
+
CMSIS System View Description
+
+
+ +
+ +
+ + +
+
+ +
+
+
+ +
+
+
+
System View Description
+
+
+

This chapter contains the introduction and specification of the CMSIS System View Description format (CMSIS-SVD). The introduction section outlines the objectives and benefits CMSIS-SVD.

+

Introduction

+

CMSIS-SVD formalizes the description of the programmer's view for the system contained in ARM Cortex-M processor-based microcontrollers, in particular the memory mapped registers of the peripherals. The detail contained in system view descriptions is comparable to what is found in device reference manuals published by silicon vendors. The information ranges from a high level functional description of a peripheral all the way down to the definition and purpose of an individual bit field in a memory mapped register. CMSIS-SVD files are developed and maintained by the silicon vendors. Silicon vendors manage their descriptions in a central, web-based Device Database and the CMSIS-SVD files are downloadable via a public web interface once they have been released by the silicon vendor. Tool vendors use these descriptions for providing device-specific debug views of peripherals in their debugger. Last but not least CMSIS compliant device header files are generated from CMSIS-SVD files.

+

CMSIS-SVD Benefits

+
    +
  • The benefits for the Software Developer:
      +
    • Consistency between device header file and what is being displayed by the debugger.
      • +
    • Detailed information about peripherals, registers, fields, and bit values from within the debugger, without the need to reference device documentation.
      • +
    • Public access via a web interface to new and updated descriptions as they become available from silicon vendors.
      • +
    • Improved software development efficiency.
      • +
    +
    • +
+
    +
  • The benefits for the Silicon Vendor:
      +
    • A tool vendor independent file format enables early device support by a wide range of toolchains with limited effort.
      • +
    • The XML-based format helps ease the integration into in-house design flows.
      • +
    • Automated generation of CMSIS compliant device header files.
      • +
    • Full control throughout the life cycle of the CMSIS-SVD files from creation to maintenance via the web-based Device Database.
      • +
    +
    • +
+
    +
  • The benefits for the Tool Vendor:
      +
    • Unified file format across silicon vendors helps the efficiency of supporting a wide range of new devices in a timely manner.
      • +
    • Silicon vendors provide early review access to individuals ahead of the publishing date.
      • +
    • Updated descriptions are available over the web simplifying the maintenance of device support.
      • +
    +
    • +
+

The Web Infrastructure

+
+CMSIS_SVD_WEB_DATABASE.png +
+CMSIS-SVD Management Processes
+

The diagram illustrates the management process steps for uploading, validating, reviewing, publishing, and downloading CMSIS-SVD files.

+
    +
  • Managing Files: A CMSIS-SVD file is uploaded by a silicon vendor via the web interface (Device Database). The system performs a check against the CMSIS-SVD Schema and runs the SVDConv consistency checker. Only if both checks have been successful the file will be stored in the SVD Storage. Files can be added, replaced and deleted.
    • +
+
    +
  • Managing Devices: The silicon vendor creates an entry for each of his devices in the database by defining a name and associating it with a CMSIS-SVD file from the SVD Storage. The publishing date set forth for a device is used by the system to determine when this device becomes visible in the public device database. Prior to the publishing date, the silicon vendor can grant review access to individuals for an individual device. Reviewers get notified by e-mail about a device being made available for review.
    • +
+
    +
  • Public Download: Public access to the silicon vendor specific CMSIS-SVD download pages is provided from cmsis.arm.com or www.arm.com/cmsis. Select the CMSIS-SVD tab and select the Silicon Vendor of interest from the list. For the public download of the CMSIS-SVD files of published devices it is mandatory to:
      +
    • Be logged in on the ARM web site.
      • +
    • Have accepted a silicon vendor specific End Users License Agreement (EULA).
      • +
    +
    • +
+

More information about the web infrastructure can be found in the CMSIS-SVD Web Interface User Guide

+

Language Outline

+ +

Language Specification

+ +
+
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b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+".preventClickEvent",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery); +/* + * jQuery UI Resizable 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * jquery.ui.core.js + * jquery.ui.mouse.js + * jquery.ui.widget.js + */ +(function(a,b){a.widget("ui.resizable",a.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:!1,animate:!1,animateDuration:"slow",animateEasing:"swing",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:"e,s,se",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass("ui-resizable"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||"ui-resizable-helper":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
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');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),"se"==f&&h.addClass("ui-icon ui-icon-gripsmall-diagonal-se"),this.handles[f]=".ui-resizable-"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=["padding",/ne|nw|n/.test(c)?"Top":/se|sw|s/.test(c)?"Bottom":/^e$/.test(c)?"Right":"Left"].join("");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(".ui-resizable-handle",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:"se"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass("ui-resizable-autohide").hover(function(){c.disabled||(a(this).removeClass("ui-resizable-autohide"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass("ui-resizable-autohide"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css("position"),width:c.outerWidth(),height:c.outerHeight(),top:c.css("top"),left:c.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(".ui-draggable")||/absolute/.test(f.css("position")))&&f.css({position:"absolute",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css("left")),h=c(this.helper.css("top"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio=="number"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(".ui-resizable-"+this.axis).css("cursor");a("body").css("cursor",i=="auto"?this.axis+"-resize":i),f.addClass("ui-resizable-resizing"),this._propagate("start",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate("resize",b),c.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger("resize",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],"left")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css("left"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css("top"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a("body").css("cursor","auto"),this.element.removeClass("ui-resizable-resizing"),this._propagate("stop",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:"absolute",left:this.elementOffset.left-e+"px",top:this.elementOffset.top-e+"px",zIndex:++c.zIndex}),this.helper.appendTo("body").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!="resize"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:"1.8.18"}),a.ui.plugin.add("resizable","alsoResize",{start:function(b,c){var d=a(this).data("resizable"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data("resizable-alsoresize",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css("left"),10),top:parseInt(b.css("top"),10)})})};typeof e.alsoResize=="object"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data("resizable-alsoresize"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?["width","height"]:["width","height","top","left"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof e.alsoResize=="object"&&!e.alsoResize.nodeType?a.each(e.alsoResize,function(a,b){i(a,b)}):i(e.alsoResize)},stop:function(b,c){a(this).removeData("resizable-alsoresize")}}),a.ui.plugin.add("resizable","animate",{stop:function(b,c){var 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a?h.get(0):/parent/.test(h)?g.parent().get(0):h;if(!!i){e.containerElement=a(i);if(/document/.test(h)||h==document)e.containerOffset={left:0,top:0},e.containerPosition={left:0,top:0},e.parentData={element:a(document),left:0,top:0,width:a(document).width(),height:a(document).height()||document.body.parentNode.scrollHeight};else{var j=a(i),k=[];a(["Top","Right","Left","Bottom"]).each(function(a,b){k[a]=c(j.css("padding"+b))}),e.containerOffset=j.offset(),e.containerPosition=j.position(),e.containerSize={height:j.innerHeight()-k[3],width:j.innerWidth()-k[1]};var l=e.containerOffset,m=e.containerSize.height,n=e.containerSize.width,o=a.ui.hasScroll(i,"left")?i.scrollWidth:n,p=a.ui.hasScroll(i)?i.scrollHeight:m;e.parentData={element:i,left:l.left,top:l.top,width:o,height:p}}}},resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.containerSize,g=d.containerOffset,h=d.size,i=d.position,j=d._aspectRatio||b.shiftKey,k={top:0,left:0},l=d.containerElement;l[0]!=document&&/static/.test(l.css("position"))&&(k=g),i.left<(d._helper?g.left:0)&&(d.size.width=d.size.width+(d._helper?d.position.left-g.left:d.position.left-k.left),j&&(d.size.height=d.size.width/e.aspectRatio),d.position.left=e.helper?g.left:0),i.top<(d._helper?g.top:0)&&(d.size.height=d.size.height+(d._helper?d.position.top-g.top:d.position.top),j&&(d.size.width=d.size.height*e.aspectRatio),d.position.top=d._helper?g.top:0),d.offset.left=d.parentData.left+d.position.left,d.offset.top=d.parentData.top+d.position.top;var m=Math.abs((d._helper?d.offset.left-k.left:d.offset.left-k.left)+d.sizeDiff.width),n=Math.abs((d._helper?d.offset.top-k.top:d.offset.top-g.top)+d.sizeDiff.height),o=d.containerElement.get(0)==d.element.parent().get(0),p=/relative|absolute/.test(d.containerElement.css("position"));o&&p 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d=a(this).data("resizable"),e=d.options,f=d.size;d.ghost=d.originalElement.clone(),d.ghost.css({opacity:.25,display:"block",position:"relative",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof e.ghost=="string"?e.ghost:""),d.ghost.appendTo(d.helper)},resize:function(b,c){var d=a(this).data("resizable"),e=d.options;d.ghost&&d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})},stop:function(b,c){var d=a(this).data("resizable"),e=d.options;d.ghost&&d.helper&&d.helper.get(0).removeChild(d.ghost.get(0))}}),a.ui.plugin.add("resizable","grid",{resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.size,g=d.originalSize,h=d.originalPosition,i=d.axis,j=e._aspectRatio||b.shiftKey;e.grid=typeof e.grid=="number"?[e.grid,e.grid]:e.grid;var k=Math.round((f.width-g.width)/(e.grid[0]||1))*(e.grid[0]||1),l=Math.round((f.height-g.height)/(e.grid[1]||1))*(e.grid[1]||1);/^(se|s|e)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l):/^(ne)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l):/^(sw)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.left=h.left-k):(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l,d.position.left=h.left-k)}});var c=function(a){return parseInt(a,10)||0},d=function(a){return!isNaN(parseInt(a,10))}})(jQuery); +/* + * jQuery hashchange event - v1.3 - 7/21/2010 + * http://benalman.com/projects/jquery-hashchange-plugin/ + * + * Copyright (c) 2010 "Cowboy" Ben Alman + * Dual licensed under the MIT and GPL licenses. + * http://benalman.com/about/license/ + */ +(function($,e,b){var c="hashchange",h=document,f,g=$.event.special,i=h.documentMode,d="on"+c in e&&(i===b||i>7);function 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