From 575010169a07525d1d79733c6d0bcda2a55223e0 Mon Sep 17 00:00:00 2001 From: Stacey Sheldon Date: Sat, 14 May 2011 20:32:17 -0400 Subject: [PATCH 1/2] build: add pios_board_info_blob struct to bootloader flash image The board info blob is stored in the last 128 bytes of the bootloader's flash bank. You can access this data from the application firmware like this: #include if (pios_board_info_blob.magic == PIOS_BOARD_INFO_BLOB_MAGIC) { /* Check some other fields */ } DO NOT link pios_board_info.c into your application firmware. Only bootloaders should provide the content for the board info structure. The application firmware is only a user of the data. --- flight/Bootloaders/AHRS/Makefile | 1 + flight/Bootloaders/CopterControl/Makefile | 1 + flight/Bootloaders/OpenPilot/Makefile | 1 + flight/Bootloaders/PipXtreme/Makefile | 1 + flight/PiOS/Boards/STM32103CB_CC_Rev1.h | 2 -- flight/PiOS/Boards/STM32103CB_PIPXTREME_Rev1.h | 2 +- flight/PiOS/Common/pios_board_info.c | 16 ++++++++++++++++ .../link_STM32103CB_AHRS_BL_sections.ld | 7 +++++++ .../STM32F10x/link_STM32103CB_AHRS_memory.ld | 7 ++++--- .../STM32F10x/link_STM32103CB_AHRS_sections.ld | 6 ++++++ .../link_STM32103CB_CC_Rev1_BL_sections.ld | 6 ++++++ .../STM32F10x/link_STM32103CB_CC_Rev1_memory.ld | 7 ++++--- .../link_STM32103CB_CC_Rev1_sections.ld | 6 ++++++ .../link_STM32103CB_PIPXTREME_BL_sections.ld | 7 +++++++ .../link_STM32103CB_PIPXTREME_memory.ld | 7 ++++--- .../link_STM32103CB_PIPXTREME_sections.ld | 6 ++++++ .../STM32F10x/link_STM3210E_OP_BL_sections.ld | 8 +++++++- .../PiOS/STM32F10x/link_STM3210E_OP_memory.ld | 17 +++++++++-------- .../PiOS/STM32F10x/link_STM3210E_OP_sections.ld | 8 ++++++-- flight/PiOS/inc/pios_board_info.h | 15 +++++++++++++++ 20 files changed, 108 insertions(+), 23 deletions(-) create mode 100644 flight/PiOS/Common/pios_board_info.c create mode 100644 flight/PiOS/inc/pios_board_info.h diff --git a/flight/Bootloaders/AHRS/Makefile b/flight/Bootloaders/AHRS/Makefile index ada1b99e3..4a43a6081 100644 --- a/flight/Bootloaders/AHRS/Makefile +++ b/flight/Bootloaders/AHRS/Makefile @@ -100,6 +100,7 @@ SRC += $(PIOSSTM32F10X)/pios_spi.c ## PIOS Hardware (Common) #SRC += $(PIOSCOMMON)/pios_com.c #SRC += $(PIOSCOMMON)/pios_hmc5843.c +SRC += $(PIOSCOMMON)/pios_board_info.c SRC += $(PIOSCOMMON)/pios_opahrs_proto.c SRC += $(PIOSCOMMON)/printf-stdarg.c SRC += $(PIOSCOMMON)/pios_bl_helper.c diff --git a/flight/Bootloaders/CopterControl/Makefile b/flight/Bootloaders/CopterControl/Makefile index 955d948d0..08b97701c 100644 --- a/flight/Bootloaders/CopterControl/Makefile +++ b/flight/Bootloaders/CopterControl/Makefile @@ -123,6 +123,7 @@ SRC += $(PIOSSTM32F10X)/pios_usb_hid_prop.c SRC += $(PIOSSTM32F10X)/pios_usb_hid_pwr.c ## PIOS Hardware (Common) +SRC += $(PIOSCOMMON)/pios_board_info.c SRC += $(PIOSCOMMON)/pios_com.c SRC += $(PIOSCOMMON)/pios_bl_helper.c SRC += $(PIOSCOMMON)/pios_iap.c diff --git a/flight/Bootloaders/OpenPilot/Makefile b/flight/Bootloaders/OpenPilot/Makefile index 735a63003..33a7f8705 100644 --- a/flight/Bootloaders/OpenPilot/Makefile +++ b/flight/Bootloaders/OpenPilot/Makefile @@ -124,6 +124,7 @@ SRC += $(PIOSSTM32F10X)/pios_usb_hid_prop.c SRC += $(PIOSSTM32F10X)/pios_usb_hid_pwr.c ## PIOS Hardware (Common) +SRC += $(PIOSCOMMON)/pios_board_info.c SRC += $(PIOSCOMMON)/pios_com.c SRC += $(PIOSCOMMON)/pios_opahrs_v0.c SRC += $(PIOSCOMMON)/pios_bl_helper.c diff --git a/flight/Bootloaders/PipXtreme/Makefile b/flight/Bootloaders/PipXtreme/Makefile index e1d2e8156..00fa37f81 100644 --- a/flight/Bootloaders/PipXtreme/Makefile +++ b/flight/Bootloaders/PipXtreme/Makefile @@ -122,6 +122,7 @@ SRC += $(PIOSSTM32F10X)/pios_usb_hid_prop.c SRC += $(PIOSSTM32F10X)/pios_usb_hid_pwr.c ## PIOS Hardware (Common) +SRC += $(PIOSCOMMON)/pios_board_info.c SRC += $(PIOSCOMMON)/pios_com.c SRC += $(PIOSCOMMON)/pios_bl_helper.c SRC += $(PIOSCOMMON)/pios_iap.c diff --git a/flight/PiOS/Boards/STM32103CB_CC_Rev1.h b/flight/PiOS/Boards/STM32103CB_CC_Rev1.h index a39b8b457..09405bfa3 100644 --- a/flight/PiOS/Boards/STM32103CB_CC_Rev1.h +++ b/flight/PiOS/Boards/STM32103CB_CC_Rev1.h @@ -66,8 +66,6 @@ TIM4 | RC In 1 | Servo 3 | Servo 2 | Servo 1 #define BOOTLOADER_VERSION 0 #define BOARD_TYPE 0x04 #define BOARD_REVISION 0x01 -//#define HW_VERSION (BOARD_TYPE << 8) | BOARD_REVISION - #define MEM_SIZE 0x20000 //128K #define SIZE_OF_DESCRIPTION 100 #define START_OF_USER_CODE (uint32_t)0x08003000 diff --git a/flight/PiOS/Boards/STM32103CB_PIPXTREME_Rev1.h b/flight/PiOS/Boards/STM32103CB_PIPXTREME_Rev1.h index 3234b8014..a4792a717 100644 --- a/flight/PiOS/Boards/STM32103CB_PIPXTREME_Rev1.h +++ b/flight/PiOS/Boards/STM32103CB_PIPXTREME_Rev1.h @@ -61,7 +61,7 @@ TIM4 | STOPWATCH | #define BOOTLOADER_VERSION 0 #define BOARD_TYPE 0x03 #define BOARD_REVISION 0x01 -#define MEM_SIZE ((uint32_t)(*((volatile uint16_t *)(0x1FFFF7E0))) * 1024 - 1024) //128K +#define MEM_SIZE (0x20000 - 0x00400) // 128K - 1K (reserved for config data) #define SIZE_OF_DESCRIPTION 100 #define START_OF_USER_CODE (uint32_t)0x08003000 #define SIZE_OF_CODE (uint32_t)(MEM_SIZE-(START_OF_USER_CODE-0x08000000)-SIZE_OF_DESCRIPTION) diff --git a/flight/PiOS/Common/pios_board_info.c b/flight/PiOS/Common/pios_board_info.c new file mode 100644 index 000000000..db9e72f9e --- /dev/null +++ b/flight/PiOS/Common/pios_board_info.c @@ -0,0 +1,16 @@ +#include +#include + +#include "pios_board_info.h" + +const struct pios_board_info __attribute__((__used__)) __attribute__((__section__(".boardinfo"))) pios_board_info_blob = { + .magic = PIOS_BOARD_INFO_BLOB_MAGIC, + .board_type = BOARD_TYPE, + .board_rev = BOARD_REVISION, + .bl_rev = BOOTLOADER_VERSION, + .hw_type = HW_TYPE, + .fw_base = START_OF_USER_CODE, + .fw_size = SIZE_OF_CODE, + .desc_base = START_OF_USER_CODE + SIZE_OF_CODE, + .desc_size = SIZE_OF_DESCRIPTION, +}; diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_BL_sections.ld b/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_BL_sections.ld index ccc2cfe7a..4f3c77d4c 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_BL_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_BL_sections.ld @@ -45,4 +45,11 @@ SECTIONS . = ALIGN(4); _end = . ; + + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(4); + } > BD_INFO } diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_memory.ld b/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_memory.ld index 50823e432..9f7bf0f19 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_memory.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_memory.ld @@ -1,6 +1,7 @@ MEMORY { - BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 8K - FLASH (rx) : ORIGIN = 0x08000000 + 8K, LENGTH = 128K - 8K - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K + BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x02000 - 0x00080 + BD_INFO (r) : ORIGIN = 0x08002000 - 0x80, LENGTH = 0x00080 + FLASH (rx) : ORIGIN = 0x08002000, LENGTH = 0x20000 - 0x02000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x05000 } diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_sections.ld b/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_sections.ld index 207956b53..82a8ae7f4 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_AHRS_sections.ld @@ -3,6 +3,12 @@ _estack = 0x20004FF0; /* Section Definitions */ SECTIONS { + .boardinfo : + { + . = ALIGN(4); + PROVIDE(pios_board_info_blob = .); + } > BD_INFO + .text : { KEEP(*(.isr_vector .isr_vector.*)) diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_BL_sections.ld b/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_BL_sections.ld index b5b4e07d0..13cd35df6 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_BL_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_BL_sections.ld @@ -61,6 +61,12 @@ SECTIONS . = ALIGN(4); _end = . ; + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + } > BD_INFO + /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_memory.ld b/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_memory.ld index 57146d7d6..fd36c31ba 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_memory.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_memory.ld @@ -1,6 +1,7 @@ MEMORY { - BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 12K - FLASH (rx) : ORIGIN = 0x08000000 + 12K, LENGTH = 128K - 12K - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K + BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x03000 - 0x00080 + BD_INFO (r) : ORIGIN = 0x08003000 - 0x80, LENGTH = 0x00080 + FLASH (rx) : ORIGIN = 0x08003000, LENGTH = 0x20000 - 0x03000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x05000 } diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_sections.ld b/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_sections.ld index 17534b780..6e46c43c5 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_CC_Rev1_sections.ld @@ -8,6 +8,12 @@ _estack = 0x20004FF0; /* Section Definitions */ SECTIONS { + .boardinfo : + { + . = ALIGN(4); + PROVIDE(pios_board_info_blob = .); + } > BD_INFO + .text : { KEEP(*(.isr_vector .isr_vector.*)) diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_BL_sections.ld b/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_BL_sections.ld index de9efa6fc..4b35cd71b 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_BL_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_BL_sections.ld @@ -50,4 +50,11 @@ SECTIONS . = ALIGN(4); _end = . ; + + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(4); + } > BD_INFO } diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_memory.ld b/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_memory.ld index 57146d7d6..fd36c31ba 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_memory.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_memory.ld @@ -1,6 +1,7 @@ MEMORY { - BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 12K - FLASH (rx) : ORIGIN = 0x08000000 + 12K, LENGTH = 128K - 12K - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K + BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x03000 - 0x00080 + BD_INFO (r) : ORIGIN = 0x08003000 - 0x80, LENGTH = 0x00080 + FLASH (rx) : ORIGIN = 0x08003000, LENGTH = 0x20000 - 0x03000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x05000 } diff --git a/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_sections.ld b/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_sections.ld index 678f164c8..dc09e6f1c 100644 --- a/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM32103CB_PIPXTREME_sections.ld @@ -8,6 +8,12 @@ _estack = 0x20004FF0; /* Section Definitions */ SECTIONS { + .boardinfo : + { + . = ALIGN(4); + PROVIDE(pios_board_info_blob = .); + } > BD_INFO + .text : { KEEP(*(.isr_vector .isr_vector.*)) diff --git a/flight/PiOS/STM32F10x/link_STM3210E_OP_BL_sections.ld b/flight/PiOS/STM32F10x/link_STM3210E_OP_BL_sections.ld index 120a2ba1b..3add614d6 100644 --- a/flight/PiOS/STM32F10x/link_STM3210E_OP_BL_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM3210E_OP_BL_sections.ld @@ -163,7 +163,6 @@ PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ; SECTIONS { - /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ .isr_vector : { @@ -313,6 +312,13 @@ SECTIONS __exidx_start = .; __exidx_end = .; + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(4); + } > BD_INFO + /* after that it's only debugging information. */ /* remove the debugging information from the standard libraries */ diff --git a/flight/PiOS/STM32F10x/link_STM3210E_OP_memory.ld b/flight/PiOS/STM32F10x/link_STM3210E_OP_memory.ld index 72ed542d2..ce70e2e5c 100644 --- a/flight/PiOS/STM32F10x/link_STM3210E_OP_memory.ld +++ b/flight/PiOS/STM32F10x/link_STM3210E_OP_memory.ld @@ -1,11 +1,12 @@ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K - BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 20K - FLASH (rx) : ORIGIN = 0x08000000 + 20K, LENGTH = 512K - 20K - FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 - EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 - EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 - EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 - EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x10000 + BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x05000 - 0x00080 + BD_INFO (r) : ORIGIN = 0x08005000 - 0x80, LENGTH = 0x00080 + FLASH (rx) : ORIGIN = 0x08005000, LENGTH = 0x80000 - 0x05000 + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 } diff --git a/flight/PiOS/STM32F10x/link_STM3210E_OP_sections.ld b/flight/PiOS/STM32F10x/link_STM3210E_OP_sections.ld index 97e60b135..2292a40e2 100644 --- a/flight/PiOS/STM32F10x/link_STM3210E_OP_sections.ld +++ b/flight/PiOS/STM32F10x/link_STM3210E_OP_sections.ld @@ -163,7 +163,12 @@ PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ; SECTIONS { - + .boardinfo : + { + . = ALIGN(4); + PROVIDE(pios_board_info_blob = .); + } > BD_INFO + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ .isr_vector : { @@ -208,7 +213,6 @@ SECTIONS _sidata = _etext; } >FLASH - /* * This stack is used both as the initial sp during early init as well as ultimately * being used as the STM32's MSP (Main Stack Pointer) which is the same stack that diff --git a/flight/PiOS/inc/pios_board_info.h b/flight/PiOS/inc/pios_board_info.h new file mode 100644 index 000000000..579a3ec2b --- /dev/null +++ b/flight/PiOS/inc/pios_board_info.h @@ -0,0 +1,15 @@ +#define PIOS_BOARD_INFO_BLOB_MAGIC 0xBDBDBDBD + +struct pios_board_info { + uint32_t magic; + uint8_t board_type; + uint8_t board_rev; + uint8_t bl_rev; + uint8_t hw_type; + uint32_t fw_base; + uint32_t fw_size; + uint32_t desc_base; + uint32_t desc_size; +} __attribute__((packed)); + +extern const struct pios_board_info pios_board_info_blob; From 2044d777e621b386e12d142c1bffa24073740487 Mon Sep 17 00:00:00 2001 From: Stacey Sheldon Date: Sat, 14 May 2011 20:41:08 -0400 Subject: [PATCH 2/2] coptercontrol: always enable -g debug symbols This does not affect the size of the image or the RAM used by the firmware image. All debugging symbols are stripped from the elf file during the conversion to a .bin file. --- flight/CopterControl/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/flight/CopterControl/Makefile b/flight/CopterControl/Makefile index c158a04fa..627882539 100644 --- a/flight/CopterControl/Makefile +++ b/flight/CopterControl/Makefile @@ -420,9 +420,10 @@ CSTANDARD = -std=gnu99 # Flags for C and C++ (arm-elf-gcc/arm-elf-g++) ifeq ($(DEBUG),YES) -CFLAGS = -g$(DEBUGF) -DDEBUG +CFLAGS = -DDEBUG endif +CFLAGS += -g$(DEBUGF) CFLAGS += -O$(OPT) CFLAGS += -mcpu=$(MCU) CFLAGS += $(CDEFS)