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Merged in physicsboy0709/librepilot/add_stm32f427family_support (pull request #91)

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LP-149 Add STM32F427/429/437/439 chip support, preparation for brand new board. and minor fixes
This commit is contained in:
Alessio Morale 2015-12-13 19:11:25 +01:00
commit 48653de561
8 changed files with 539 additions and 3 deletions
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14
flight/pios/stm32f4xx/library.mk
View File

@ -16,12 +16,26 @@ LINKER_SCRIPTS_COMPAT = $(PIOS_DEVLIB)link_$(BOARD)_fw_memory.ld \
# Compiler options implied by the F4xx # Compiler options implied by the F4xx
CDEFS += -DSTM32F4XX CDEFS += -DSTM32F4XX
ifeq ($(CHIPFAMILY),STM32F427_437xx)
CDEFS += -DPIOS_TARGET_PROVIDES_FAST_HEAP
#large heap support must be enabled if SRAM > 128K
CDEFS += -DHEAP_SUPPORT_LARGE
CDEFS += -DSTM32F427_437xx
else
ifeq ($(CHIPFAMILY),STM32F429_439xx)
CDEFS += -DPIOS_TARGET_PROVIDES_FAST_HEAP
#large heap support must be enabled if SRAM > 128K
CDEFS += -DHEAP_SUPPORT_LARGE
CDEFS += -DSTM32F429_439xx
else
ifneq ($(CHIPFAMILY),STM32F411xx) ifneq ($(CHIPFAMILY),STM32F411xx)
CDEFS += -DPIOS_TARGET_PROVIDES_FAST_HEAP CDEFS += -DPIOS_TARGET_PROVIDES_FAST_HEAP
CDEFS += -DSTM32F40_41xxx CDEFS += -DSTM32F40_41xxx
else else
CDEFS += -DSTM32F411xE CDEFS += -DSTM32F411xE
endif endif
endif #STM32F429_439xx
endif #STM32F427_437xx
CDEFS += -DSYSCLK_FREQ=$(SYSCLK_FREQ) CDEFS += -DSYSCLK_FREQ=$(SYSCLK_FREQ)
CDEFS += -DHSE_VALUE=$(OSCILLATOR_FREQ) CDEFS += -DHSE_VALUE=$(OSCILLATOR_FREQ)
CDEFS += -DUSE_STDPERIPH_DRIVER CDEFS += -DUSE_STDPERIPH_DRIVER

9
flight/pios/stm32f4xx/link_STM32F4xx_RQ_bl_memory.ld Normal file
View File

@ -0,0 +1,9 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x008000 - 0x000080
BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080
RSVD (rx) : ORIGIN = 0x08008000, LENGTH = 0x020000 - 0x008000
FW (rx) : ORIGIN = 0x08020000, LENGTH = 0x1e0000
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x030000
}

9
flight/pios/stm32f4xx/link_STM32F4xx_RQ_fw_memory.ld Normal file
View File

@ -0,0 +1,9 @@
MEMORY
{
BL (rx) : ORIGIN = 0x08000000, LENGTH = 0x008000 - 0x000080
BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080
RSVD (rx) : ORIGIN = 0x08008000, LENGTH = 0x020000 - 0x008000
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 0x1e0000
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x030000
}

193
flight/pios/stm32f4xx/link_STM32F4xx_RQ_sections.ld Normal file
View File

@ -0,0 +1,193 @@
/* Section Definitions */
SECTIONS
{
/*
* Vectors, code and constant data.
*/
.text :
{
PROVIDE (pios_isr_vector_table_base = .);
KEEP(*(.cpu_vectors)) /* CPU exception vectors */
KEEP(*(.io_vectors)) /* I/O interrupt vectors */
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
} > FLASH
/*
* Init section for UAVObjects.
*/
.initcalluavobj.init :
{
. = ALIGN(4);
__uavobj_initcall_start = .;
KEEP(*(.initcalluavobj.init))
. = ALIGN(4);
__uavobj_initcall_end = .;
} >FLASH
/*
* Module init section section
*/
.initcallmodule.init :
{
. = ALIGN(4);
__module_initcall_start = .;
KEEP(*(.initcallmodule.init))
. = ALIGN(4);
__module_initcall_end = .;
} >FLASH
/*
* C++ exception handling.
*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/*
* Markers for the end of the 'text' section and the in-flash start of
* non-constant data
*/
. = ALIGN(4);
_etext = .;
_sidata = .;
/*
* Board info structure, normally only generated by the bootloader but can
* be read by the application.
*/
PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
.boardinfo :
{
. = ALIGN(4);
KEEP(*(.boardinfo))
. = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO));
} > BD_INFO
/*
* Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow
* results in a hard fault.
*/
.istack (NOLOAD) :
{
. = ALIGN(4);
_irq_stack_end = . ;
*(.irqstack)
_irq_stack_top = . ;
} > CCSRAM
/*
* Non-const initialised data.
*/
.data : AT (_sidata)
{
. = ALIGN(4);
_sdata = .;
*(.data .data.*)
. = ALIGN(4);
_edata = . ;
} > SRAM
/*
* Uninitialised data (BSS + commons).
*/
.bss (NOLOAD) :
{
_sbss = . ;
*(.bss .bss.*)
*(COMMON)
_ebss = . ;
PROVIDE ( _end = _ebss ) ;
} > SRAM
/*
* The heap consumes the remainder of the SRAM.
*/
.heap (NOLOAD) :
{
. = ALIGN(4);
_sheap = . ;
/*
* This allows us to declare an object or objects up to the minimum acceptable
* heap size and receive a linker error if the space available for the heap is
* not sufficient.
*/
*(.heap)
/* extend the heap up to the top of SRAM */
. = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap);
_eheap = .;
} > SRAM
/*
* 'Fast' memory goes in the CCM SRAM
*/
.fast (NOLOAD) :
{
_sfast = . ;
*(.fast)
_efast = . ;
} > CCSRAM
.fastheap (NOLOAD) :
{
. = ALIGN(4);
_sfastheap = . ;
/*
* This allows us to declare an object or objects up to the minimum acceptable
* heap size and receive a linker error if the space available for the heap is
* not sufficient.
*/
*(.fastheap)
/* extend the fastheap up to the top of CCSRAM */
. = ORIGIN(CCSRAM) + LENGTH(CCSRAM) - ABSOLUTE(_sfastheap);
_efastheap = .;
} > CCSRAM
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

176
flight/pios/stm32f4xx/link_STM32F4xx_RQ_sections_compat.ld Normal file
View File

@ -0,0 +1,176 @@
/* Section Definitions */
SECTIONS
{
/*
* Vectors, code and constant data.
*/
.text :
{
PROVIDE (pios_isr_vector_table_base = .);
KEEP(*(.cpu_vectors)) /* CPU exception vectors */
KEEP(*(.io_vectors)) /* I/O interrupt vectors */
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
} > FLASH
/*
* Init section for UAVObjects.
*/
.initcalluavobj.init :
{
. = ALIGN(4);
__uavobj_initcall_start = .;
KEEP(*(.initcalluavobj.init))
. = ALIGN(4);
__uavobj_initcall_end = .;
} >FLASH
/*
* Module init section section
*/
.initcallmodule.init :
{
. = ALIGN(4);
__module_initcall_start = .;
KEEP(*(.initcallmodule.init))
. = ALIGN(4);
__module_initcall_end = .;
} >FLASH
/*
* C++ exception handling.
*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/*
* Markers for the end of the 'text' section and the in-flash start of
* non-constant data
*/
. = ALIGN(4);
_etext = .;
_sidata = .;
/*
* Board info structure, normally only generated by the bootloader but can
* be read by the application.
*/
PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
.boardinfo :
{
. = ALIGN(4);
KEEP(*(.boardinfo))
. = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO));
} > BD_INFO
/*
* Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow
* results in a hard fault.
*/
.istack (NOLOAD) :
{
. = ALIGN(4);
_irq_stack_end = . ;
*(.irqstack)
_irq_stack_top = . ;
} > SRAM
/*
* Non-const initialised data.
*/
.data : AT (_sidata)
{
. = ALIGN(4);
_sdata = .;
*(.data .data.*)
. = ALIGN(4);
_edata = . ;
} > SRAM
/*
* Uninitialised data (BSS + commons).
*/
.bss (NOLOAD) :
{
_sbss = . ;
*(.bss .bss.*)
*(COMMON)
_ebss = . ;
PROVIDE ( _end = _ebss ) ;
} > SRAM
/*
* The heap consumes the remainder of the SRAM.
*/
.heap (NOLOAD) :
{
. = ALIGN(4);
_sheap = . ;
/*
* This allows us to declare an object or objects up to the minimum acceptable
* heap size and receive a linker error if the space available for the heap is
* not sufficient.
*/
*(.heap)
/* extend the heap up to the top of SRAM */
. = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap);
_eheap = .;
} > SRAM
/*
* 'Fast' memory goes in the CCM SRAM
*/
.fast (NOLOAD) :
{
_sfast = . ;
*(.fast)
_efast = . ;
} > CCSRAM
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

74
flight/pios/stm32f4xx/pios_bl_helper.c
View File

@ -119,6 +119,66 @@ static struct device_flash_sector flash_sectors[] = {
.size = 128 * 1024, .size = 128 * 1024,
.st_sector = FLASH_Sector_11, .st_sector = FLASH_Sector_11,
}, },
[12] = {
.start = 0x08100000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_12,
},
[13] = {
.start = 0x08104000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_13,
},
[14] = {
.start = 0x08108000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_14,
},
[15] = {
.start = 0x0810C000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_15,
},
[16] = {
.start = 0x08110000,
.size = 64 * 1024,
.st_sector = FLASH_Sector_16,
},
[17] = {
.start = 0x08120000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_17,
},
[18] = {
.start = 0x08140000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_18,
},
[19] = {
.start = 0x08160000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_19,
},
[20] = {
.start = 0x08180000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_20,
},
[21] = {
.start = 0x081A0000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_21,
},
[22] = {
.start = 0x081C0000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_22,
},
[23] = {
.start = 0x081E0000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_23,
},
}; };
static bool PIOS_BL_HELPER_FLASH_GetSectorInfo(uint32_t address, uint8_t *sector_number, uint32_t *sector_start, uint32_t *sector_size) static bool PIOS_BL_HELPER_FLASH_GetSectorInfo(uint32_t address, uint8_t *sector_number, uint32_t *sector_start, uint32_t *sector_size)
@ -178,7 +238,19 @@ static bool erase_flash(uint32_t startAddress, uint32_t endAddress)
PIOS_Assert(0); PIOS_Assert(0);
} }
for (int retry = 0; retry < MAX_DEL_RETRYS; ++retry) { for (int retry = 0; retry < MAX_DEL_RETRYS; ++retry) {
if (FLASH_EraseSector(sector_number, VoltageRange_3) == FLASH_COMPLETE) { //if erasing area contain whole bank2 area, using bank erase
//bank2: sector 12 to sector 23
if (sector_start == flash_sectors[12].start &&
endAddress >= (flash_sectors[23].start + flash_sectors[23].size)){
if (FLASH_EraseAllBank2Sectors(VoltageRange_3) == FLASH_COMPLETE) {
fail = false;
//using bank2 total size substitute sector_size
sector_size = flash_sectors[23].start - flash_sectors[12].start + flash_sectors[23].size;
break;
} else {
fail = true;
}
} else if (FLASH_EraseSector(sector_number, VoltageRange_3) == FLASH_COMPLETE) {
fail = false; fail = false;
break; break;
} else { } else {

60
flight/pios/stm32f4xx/pios_flash_internal.c
View File

@ -100,6 +100,66 @@ static struct device_flash_sector flash_sectors[] = {
.size = 128 * 1024, .size = 128 * 1024,
.st_sector = FLASH_Sector_11, .st_sector = FLASH_Sector_11,
}, },
[12] = {
.start = 0x08100000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_12,
},
[13] = {
.start = 0x08104000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_13,
},
[14] = {
.start = 0x08108000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_14,
},
[15] = {
.start = 0x0810C000,
.size = 16 * 1024,
.st_sector = FLASH_Sector_15,
},
[16] = {
.start = 0x08110000,
.size = 64 * 1024,
.st_sector = FLASH_Sector_16,
},
[17] = {
.start = 0x08120000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_17,
},
[18] = {
.start = 0x08140000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_18,
},
[19] = {
.start = 0x08160000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_19,
},
[20] = {
.start = 0x08180000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_20,
},
[21] = {
.start = 0x081A0000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_21,
},
[22] = {
.start = 0x081C0000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_22,
},
[23] = {
.start = 0x081E0000,
.size = 128 * 1024,
.st_sector = FLASH_Sector_23,
},
}; };
static bool PIOS_Flash_Internal_GetSectorInfo(uint32_t address, uint8_t *sector_number, uint32_t *sector_start, uint32_t *sector_size) static bool PIOS_Flash_Internal_GetSectorInfo(uint32_t address, uint8_t *sector_number, uint32_t *sector_start, uint32_t *sector_size)

7
flight/pios/stm32f4xx/pios_sys.c
View File

@ -74,7 +74,7 @@ void PIOS_SYS_Init(void)
RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOC |
RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOD |
RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOE |
#ifdef STM32F40_41xxx #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOF |
RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOG |
RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOH |
@ -85,6 +85,9 @@ void PIOS_SYS_Init(void)
RCC_AHB1Periph_SRAM1 | RCC_AHB1Periph_SRAM1 |
RCC_AHB1Periph_SRAM2 | RCC_AHB1Periph_SRAM2 |
RCC_AHB1Periph_BKPSRAM | RCC_AHB1Periph_BKPSRAM |
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
RCC_AHB1Periph_SRAM3 |
#endif
RCC_AHB1Periph_DMA1 | RCC_AHB1Periph_DMA1 |
RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_DMA2 |
// RCC_AHB1Periph_ETH_MAC | No ethernet // RCC_AHB1Periph_ETH_MAC | No ethernet
@ -171,7 +174,7 @@ void PIOS_SYS_Init(void)
GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_Init(GPIOE, &GPIO_InitStructure); GPIO_Init(GPIOE, &GPIO_InitStructure);
#ifdef STM32F40_41xxx #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
GPIO_Init(GPIOF, &GPIO_InitStructure); GPIO_Init(GPIOF, &GPIO_InitStructure);
GPIO_Init(GPIOG, &GPIO_InitStructure); GPIO_Init(GPIOG, &GPIO_InitStructure);
GPIO_Init(GPIOH, &GPIO_InitStructure); GPIO_Init(GPIOH, &GPIO_InitStructure);