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PIOS SPI: Added a function to detect if the channel is busy
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1829 ebee16cc-31ac-478f-84a7-5cbb03baadba
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les
les
parent
d2c1014e29
commit
498f3d0fa6
@ -1,452 +1,487 @@
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/**
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/**
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******************************************************************************
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @{
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* @addtogroup PIOS_SPI SPI Functions
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* @addtogroup PIOS_SPI SPI Functions
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* @brief PIOS interface to read and write from SPI ports
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* @brief PIOS interface to read and write from SPI ports
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* @{
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* @{
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*
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*
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* @file pios_spi.c
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* @file pios_spi.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* Parts by Thorsten Klose (tk@midibox.org) (tk@midibox.org)
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* Parts by Thorsten Klose (tk@midibox.org) (tk@midibox.org)
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* @brief Hardware Abstraction Layer for SPI ports of STM32
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* @brief Hardware Abstraction Layer for SPI ports of STM32
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* @see The GNU Public License (GPL) Version 3
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* @see The GNU Public License (GPL) Version 3
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* @notes
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* @notes
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*
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*
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* Note that additional chip select lines can be easily added by using
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* Note that additional chip select lines can be easily added by using
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* the remaining free GPIOs of the core module. Shared SPI ports should be
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* the remaining free GPIOs of the core module. Shared SPI ports should be
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* arbitrated with (FreeRTOS based) Mutexes to avoid collisions!
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* arbitrated with (FreeRTOS based) Mutexes to avoid collisions!
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*
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*
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*****************************************************************************/
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*****************************************************************************/
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/*
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/*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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* (at your option) any later version.
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*
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*
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* This program is distributed in the hope that it will be useful, but
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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* for more details.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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*/
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#include <pios.h>
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#include <pios.h>
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#if defined(PIOS_INCLUDE_SPI)
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#if defined(PIOS_INCLUDE_SPI)
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#include <pios_spi_priv.h>
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#include <pios_spi_priv.h>
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static struct pios_spi_dev *find_spi_dev_by_id(uint8_t spi)
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static struct pios_spi_dev *find_spi_dev_by_id(uint8_t spi)
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{
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{
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if (spi >= pios_spi_num_devices) {
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if (spi >= pios_spi_num_devices) {
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/* Undefined SPI port for this board (see pios_board.c) */
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/* Undefined SPI port for this board (see pios_board.c) */
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return NULL;
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return NULL;
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}
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}
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/* Get a handle for the device configuration */
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/* Get a handle for the device configuration */
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return &(pios_spi_devs[spi]);
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return &(pios_spi_devs[spi]);
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}
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}
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/**
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/**
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* Initialises SPI pins
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* Initialises SPI pins
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* \param[in] mode currently only mode 0 supported
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* \param[in] mode currently only mode 0 supported
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* \return < 0 if initialisation failed
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* \return < 0 if initialisation failed
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*/
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*/
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int32_t PIOS_SPI_Init(void)
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int32_t PIOS_SPI_Init(void)
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{
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{
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struct pios_spi_dev *spi_dev;
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struct pios_spi_dev *spi_dev;
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uint8_t i;
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uint8_t i;
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for (i = 0; i < pios_spi_num_devices; i++) {
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for (i = 0; i < pios_spi_num_devices; i++) {
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/* Get a handle for the device configuration */
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(i);
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spi_dev = find_spi_dev_by_id(i);
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PIOS_DEBUG_Assert(spi_dev);
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PIOS_DEBUG_Assert(spi_dev);
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/* Disable callback function */
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/* Disable callback function */
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spi_dev->callback = NULL;
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spi_dev->callback = NULL;
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/* Set rx/tx dummy bytes to a known value */
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/* Set rx/tx dummy bytes to a known value */
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spi_dev->rx_dummy_byte = 0xFF;
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spi_dev->rx_dummy_byte = 0xFF;
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spi_dev->tx_dummy_byte = 0xFF;
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spi_dev->tx_dummy_byte = 0xFF;
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switch (spi_dev->cfg->init.SPI_NSS) {
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switch (spi_dev->cfg->init.SPI_NSS) {
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case SPI_NSS_Soft:
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case SPI_NSS_Soft:
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if (spi_dev->cfg->init.SPI_Mode == SPI_Mode_Master) {
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if (spi_dev->cfg->init.SPI_Mode == SPI_Mode_Master) {
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/* We're a master in soft NSS mode, make sure we see NSS high at all times. */
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/* We're a master in soft NSS mode, make sure we see NSS high at all times. */
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Set);
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Set);
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/* Since we're driving the SSEL pin in software, ensure that the slave is deselected */
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/* Since we're driving the SSEL pin in software, ensure that the slave is deselected */
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GPIO_SetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
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GPIO_SetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
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GPIO_Init(spi_dev->cfg->ssel.gpio, &(spi_dev->cfg->ssel.init));
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GPIO_Init(spi_dev->cfg->ssel.gpio, &(spi_dev->cfg->ssel.init));
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} else {
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} else {
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/* We're a slave in soft NSS mode, make sure we see NSS low at all times. */
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/* We're a slave in soft NSS mode, make sure we see NSS low at all times. */
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Reset);
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Reset);
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}
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}
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break;
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break;
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case SPI_NSS_Hard:
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case SPI_NSS_Hard:
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/* FIXME: Should this also call SPI_SSOutputCmd()? */
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/* FIXME: Should this also call SPI_SSOutputCmd()? */
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GPIO_Init(spi_dev->cfg->ssel.gpio, &(spi_dev->cfg->ssel.init));
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GPIO_Init(spi_dev->cfg->ssel.gpio, &(spi_dev->cfg->ssel.init));
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break;
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break;
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default:
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default:
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PIOS_DEBUG_Assert(0);
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PIOS_DEBUG_Assert(0);
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}
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}
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/* Initialize the GPIO pins */
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/* Initialize the GPIO pins */
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GPIO_Init(spi_dev->cfg->sclk.gpio, &(spi_dev->cfg->sclk.init));
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GPIO_Init(spi_dev->cfg->sclk.gpio, &(spi_dev->cfg->sclk.init));
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GPIO_Init(spi_dev->cfg->mosi.gpio, &(spi_dev->cfg->mosi.init));
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GPIO_Init(spi_dev->cfg->mosi.gpio, &(spi_dev->cfg->mosi.init));
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GPIO_Init(spi_dev->cfg->miso.gpio, &(spi_dev->cfg->miso.init));
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GPIO_Init(spi_dev->cfg->miso.gpio, &(spi_dev->cfg->miso.init));
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/* Enable the associated peripheral clock */
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/* Enable the associated peripheral clock */
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switch ((uint32_t) spi_dev->cfg->regs) {
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switch ((uint32_t) spi_dev->cfg->regs) {
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case (uint32_t) SPI1:
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case (uint32_t) SPI1:
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/* Enable SPI peripheral clock (APB2 == high speed) */
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/* Enable SPI peripheral clock (APB2 == high speed) */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
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break;
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break;
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case (uint32_t) SPI2:
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case (uint32_t) SPI2:
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/* Enable SPI peripheral clock (APB1 == slow speed) */
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/* Enable SPI peripheral clock (APB1 == slow speed) */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
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break;
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break;
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case (uint32_t) SPI3:
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case (uint32_t) SPI3:
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/* Enable SPI peripheral clock (APB1 == slow speed) */
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/* Enable SPI peripheral clock (APB1 == slow speed) */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
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break;
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break;
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}
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}
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/* Enable DMA clock */
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/* Enable DMA clock */
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RCC_AHBPeriphClockCmd(spi_dev->cfg->dma.ahb_clk, ENABLE);
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RCC_AHBPeriphClockCmd(spi_dev->cfg->dma.ahb_clk, ENABLE);
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/* Configure DMA for SPI Rx */
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/* Configure DMA for SPI Rx */
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DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Init(spi_dev->cfg->dma.rx.channel, &(spi_dev->cfg->dma.rx.init));
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DMA_Init(spi_dev->cfg->dma.rx.channel, &(spi_dev->cfg->dma.rx.init));
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/* Configure DMA for SPI Tx */
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/* Configure DMA for SPI Tx */
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DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
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DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
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DMA_Init(spi_dev->cfg->dma.tx.channel, &(spi_dev->cfg->dma.tx.init));
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DMA_Init(spi_dev->cfg->dma.tx.channel, &(spi_dev->cfg->dma.tx.init));
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/* Initialize the SPI block */
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/* Initialize the SPI block */
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SPI_Init(spi_dev->cfg->regs, &(spi_dev->cfg->init));
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SPI_Init(spi_dev->cfg->regs, &(spi_dev->cfg->init));
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/* Configure CRC calculation */
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/* Configure CRC calculation */
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if (spi_dev->cfg->use_crc) {
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if (spi_dev->cfg->use_crc) {
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SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
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SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
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} else {
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} else {
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SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
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SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
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}
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}
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/* Enable SPI */
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/* Enable SPI */
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SPI_Cmd(spi_dev->cfg->regs, ENABLE);
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SPI_Cmd(spi_dev->cfg->regs, ENABLE);
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/* Enable SPI interrupts to DMA */
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(spi_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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SPI_I2S_DMACmd(spi_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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/* Configure DMA interrupt */
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/* Configure DMA interrupt */
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NVIC_Init(&(spi_dev->cfg->dma.irq.init));
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NVIC_Init(&(spi_dev->cfg->dma.irq.init));
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}
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}
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return 0;
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return 0;
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}
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}
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/**
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/**
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* (Re-)initialises SPI peripheral clock rate
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* (Re-)initialises SPI peripheral clock rate
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*
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*
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* \param[in] spi SPI number (0 or 1)
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* \param[in] spi SPI number (0 or 1)
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* \param[in] spi_prescaler configures the SPI speed:
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* \param[in] spi_prescaler configures the SPI speed:
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* <UL>
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* <UL>
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* <LI>PIOS_SPI_PRESCALER_2: sets clock rate 27.7~ nS @ 72 MHz (36 MBit/s) (only supported for spi==0, spi1 uses 4 instead)
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* <LI>PIOS_SPI_PRESCALER_2: sets clock rate 27.7~ nS @ 72 MHz (36 MBit/s) (only supported for spi==0, spi1 uses 4 instead)
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* <LI>PIOS_SPI_PRESCALER_4: sets clock rate 55.5~ nS @ 72 MHz (18 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_4: sets clock rate 55.5~ nS @ 72 MHz (18 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_8: sets clock rate 111.1~ nS @ 72 MHz (9 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_8: sets clock rate 111.1~ nS @ 72 MHz (9 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_16: sets clock rate 222.2~ nS @ 72 MHz (4.5 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_16: sets clock rate 222.2~ nS @ 72 MHz (4.5 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_32: sets clock rate 444.4~ nS @ 72 MHz (2.25 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_32: sets clock rate 444.4~ nS @ 72 MHz (2.25 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_64: sets clock rate 888.8~ nS @ 72 MHz (1.125 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_64: sets clock rate 888.8~ nS @ 72 MHz (1.125 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_128: sets clock rate 1.7~ nS @ 72 MHz (0.562 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_128: sets clock rate 1.7~ nS @ 72 MHz (0.562 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_256: sets clock rate 3.5~ nS @ 72 MHz (0.281 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_256: sets clock rate 3.5~ nS @ 72 MHz (0.281 MBit/s)
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* </UL>
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* </UL>
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* \return 0 if no error
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* \return 0 if no error
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* \return -1 if disabled SPI port selected
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* \return -1 if disabled SPI port selected
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* \return -2 if unsupported SPI port selected
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* \return -2 if unsupported SPI port selected
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* \return -3 if invalid spi_prescaler selected
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* \return -3 if invalid spi_prescaler selected
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*/
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*/
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int32_t PIOS_SPI_SetClockSpeed(uint8_t spi, SPIPrescalerTypeDef spi_prescaler)
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int32_t PIOS_SPI_SetClockSpeed(uint8_t spi, SPIPrescalerTypeDef spi_prescaler)
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{
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{
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struct pios_spi_dev *spi_dev;
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struct pios_spi_dev *spi_dev;
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SPI_InitTypeDef SPI_InitStructure;
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SPI_InitTypeDef SPI_InitStructure;
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/* Get a handle for the device configuration */
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(spi);
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spi_dev = find_spi_dev_by_id(spi);
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if (!spi_dev) {
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if (!spi_dev) {
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/* Undefined SPI port for this board (see pios_board.c) */
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/* Undefined SPI port for this board (see pios_board.c) */
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return -2;
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return -2;
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}
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}
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if (spi_prescaler >= 8) {
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if (spi_prescaler >= 8) {
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/* Invalid prescaler selected */
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/* Invalid prescaler selected */
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return -3;
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return -3;
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}
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}
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/* Start with a copy of the default configuration for the peripheral */
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/* Start with a copy of the default configuration for the peripheral */
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SPI_InitStructure = spi_dev->cfg->init;
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SPI_InitStructure = spi_dev->cfg->init;
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/* Adjust the prescaler for the peripheral's clock */
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/* Adjust the prescaler for the peripheral's clock */
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SPI_InitStructure.SPI_BaudRatePrescaler = ((uint16_t) spi_prescaler & 7) << 3;
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SPI_InitStructure.SPI_BaudRatePrescaler = ((uint16_t) spi_prescaler & 7) << 3;
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/* Write back the new configuration */
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/* Write back the new configuration */
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SPI_Init(spi_dev->cfg->regs, &SPI_InitStructure);
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SPI_Init(spi_dev->cfg->regs, &SPI_InitStructure);
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PIOS_SPI_TransferByte(spi, 0xFF);
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PIOS_SPI_TransferByte(spi, 0xFF);
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return 0;
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return 0;
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}
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}
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/**
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/**
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* Controls the RC (Register Clock alias Chip Select) pin of a SPI port
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* Controls the RC (Register Clock alias Chip Select) pin of a SPI port
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* \param[in] spi SPI number (0 or 1)
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* \param[in] spi SPI number (0 or 1)
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* \param[in] pin_value 0 or 1
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* \param[in] pin_value 0 or 1
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* \return 0 if no error
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* \return 0 if no error
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* \return -1 if disabled SPI port selected
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* \return -1 if disabled SPI port selected
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* \return -2 if unsupported SPI port selected
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* \return -2 if unsupported SPI port selected
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*/
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*/
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int32_t PIOS_SPI_RC_PinSet(uint8_t spi, uint8_t pin_value)
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int32_t PIOS_SPI_RC_PinSet(uint8_t spi, uint8_t pin_value)
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{
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{
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struct pios_spi_dev *spi_dev;
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struct pios_spi_dev *spi_dev;
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/* Get a handle for the device configuration */
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(spi);
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spi_dev = find_spi_dev_by_id(spi);
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if (!spi_dev) {
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if (!spi_dev) {
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/* Undefined SPI port for this board (see pios_board.c) */
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/* Undefined SPI port for this board (see pios_board.c) */
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return -2;
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return -2;
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}
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}
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if (pin_value) {
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if (pin_value) {
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GPIO_SetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
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GPIO_SetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
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} else {
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} else {
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GPIO_ResetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
|
GPIO_ResetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Transfers a byte to SPI output and reads back the return value from SPI input
|
* Transfers a byte to SPI output and reads back the return value from SPI input
|
||||||
* \param[in] spi SPI number (0 or 1)
|
* \param[in] spi SPI number (0 or 1)
|
||||||
* \param[in] b the byte which should be transfered
|
* \param[in] b the byte which should be transfered
|
||||||
*/
|
*/
|
||||||
int32_t PIOS_SPI_TransferByte(uint8_t spi, uint8_t b)
|
int32_t PIOS_SPI_TransferByte(uint8_t spi, uint8_t b)
|
||||||
{
|
{
|
||||||
struct pios_spi_dev *spi_dev;
|
struct pios_spi_dev *spi_dev;
|
||||||
uint8_t dummy;
|
uint8_t dummy;
|
||||||
uint8_t rx_byte;
|
uint8_t rx_byte;
|
||||||
|
|
||||||
/* Get a handle for the device configuration */
|
/* Get a handle for the device configuration */
|
||||||
spi_dev = find_spi_dev_by_id(spi);
|
spi_dev = find_spi_dev_by_id(spi);
|
||||||
PIOS_DEBUG_Assert(spi_dev);
|
PIOS_DEBUG_Assert(spi_dev);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Procedure taken from STM32F10xxx Reference Manual section 23.3.5
|
* Procedure taken from STM32F10xxx Reference Manual section 23.3.5
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Make sure the RXNE flag is cleared by reading the DR register */
|
/* Make sure the RXNE flag is cleared by reading the DR register */
|
||||||
dummy = spi_dev->cfg->regs->DR;
|
dummy = spi_dev->cfg->regs->DR;
|
||||||
|
|
||||||
/* Start the transfer */
|
/* Start the transfer */
|
||||||
spi_dev->cfg->regs->DR = b;
|
spi_dev->cfg->regs->DR = b;
|
||||||
|
|
||||||
/* Wait until there is a byte to read */
|
/* Wait until there is a byte to read */
|
||||||
while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_RXNE)) ;
|
while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_RXNE)) ;
|
||||||
|
|
||||||
/* Read the rx'd byte */
|
/* Read the rx'd byte */
|
||||||
rx_byte = spi_dev->cfg->regs->DR;
|
rx_byte = spi_dev->cfg->regs->DR;
|
||||||
|
|
||||||
/* Wait until the TXE goes high */
|
/* Wait until the TXE goes high */
|
||||||
while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_TXE)) ;
|
while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_TXE)) ;
|
||||||
|
|
||||||
/* Wait for SPI transfer to have fully completed */
|
/* Wait for SPI transfer to have fully completed */
|
||||||
while (spi_dev->cfg->regs->SR & SPI_I2S_FLAG_BSY) ;
|
while (spi_dev->cfg->regs->SR & SPI_I2S_FLAG_BSY) ;
|
||||||
|
|
||||||
/* Return received byte */
|
/* Return received byte */
|
||||||
return rx_byte;
|
return rx_byte;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Transfers a block of bytes via DMA.
|
* Transfers a block of bytes via DMA.
|
||||||
* \param[in] spi SPI number (0 or 1)
|
* \param[in] spi SPI number (0 or 1)
|
||||||
* \param[in] send_buffer pointer to buffer which should be sent.<BR>
|
* \param[in] send_buffer pointer to buffer which should be sent.<BR>
|
||||||
* If NULL, 0xff (all-one) will be sent.
|
* If NULL, 0xff (all-one) will be sent.
|
||||||
* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
|
* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
|
||||||
* If NULL, received bytes will be discarded.
|
* If NULL, received bytes will be discarded.
|
||||||
* \param[in] len number of bytes which should be transfered
|
* \param[in] len number of bytes which should be transfered
|
||||||
* \param[in] callback pointer to callback function which will be executed
|
* \param[in] callback pointer to callback function which will be executed
|
||||||
* from DMA channel interrupt once the transfer is finished.
|
* from DMA channel interrupt once the transfer is finished.
|
||||||
* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
|
* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
|
||||||
* block until the transfer is finished.
|
* block until the transfer is finished.
|
||||||
* \return >= 0 if no error during transfer
|
* \return >= 0 if no error during transfer
|
||||||
* \return -1 if disabled SPI port selected
|
* \return -1 if disabled SPI port selected
|
||||||
* \return -2 if unsupported SPI port selected
|
* \return -2 if unsupported SPI port selected
|
||||||
* \return -3 if function has been called during an ongoing DMA transfer
|
* \return -3 if function has been called during an ongoing DMA transfer
|
||||||
*/
|
*/
|
||||||
int32_t PIOS_SPI_TransferBlock(uint8_t spi, const uint8_t * send_buffer, uint8_t * receive_buffer, uint16_t len, void *callback)
|
int32_t PIOS_SPI_TransferBlock(uint8_t spi, const uint8_t * send_buffer, uint8_t * receive_buffer, uint16_t len, void *callback)
|
||||||
{
|
{
|
||||||
struct pios_spi_dev *spi_dev;
|
struct pios_spi_dev *spi_dev;
|
||||||
DMA_InitTypeDef dma_init;
|
DMA_InitTypeDef dma_init;
|
||||||
|
|
||||||
/* Get a handle for the device configuration */
|
/* Get a handle for the device configuration */
|
||||||
spi_dev = find_spi_dev_by_id(spi);
|
spi_dev = find_spi_dev_by_id(spi);
|
||||||
|
|
||||||
if (!spi_dev) {
|
if (!spi_dev) {
|
||||||
/* Undefined SPI port for this board (see pios_board.c) */
|
/* Undefined SPI port for this board (see pios_board.c) */
|
||||||
return -2;
|
return -2;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Exit if ongoing transfer */
|
/* Exit if ongoing transfer */
|
||||||
if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) {
|
if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) {
|
||||||
return -3;
|
return -3;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Disable the SPI peripheral */
|
/* Disable the SPI peripheral */
|
||||||
SPI_Cmd(spi_dev->cfg->regs, DISABLE);
|
SPI_Cmd(spi_dev->cfg->regs, DISABLE);
|
||||||
|
|
||||||
/* Disable the DMA channels */
|
/* Disable the DMA channels */
|
||||||
DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
|
DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
|
||||||
DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
|
DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
|
||||||
|
|
||||||
/* Set callback function */
|
/* Set callback function */
|
||||||
spi_dev->callback = callback;
|
spi_dev->callback = callback;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Configure Rx channel
|
* Configure Rx channel
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Start with the default configuration for this peripheral */
|
/* Start with the default configuration for this peripheral */
|
||||||
dma_init = spi_dev->cfg->dma.rx.init;
|
dma_init = spi_dev->cfg->dma.rx.init;
|
||||||
|
|
||||||
if (receive_buffer != NULL) {
|
if (receive_buffer != NULL) {
|
||||||
/* Enable memory addr. increment - bytes written into receive buffer */
|
/* Enable memory addr. increment - bytes written into receive buffer */
|
||||||
dma_init.DMA_MemoryBaseAddr = (uint32_t) receive_buffer;
|
dma_init.DMA_MemoryBaseAddr = (uint32_t) receive_buffer;
|
||||||
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||||
} else {
|
} else {
|
||||||
/* Disable memory addr. increment - bytes written into dummy buffer */
|
/* Disable memory addr. increment - bytes written into dummy buffer */
|
||||||
spi_dev->rx_dummy_byte = 0xFF;
|
spi_dev->rx_dummy_byte = 0xFF;
|
||||||
dma_init.DMA_MemoryBaseAddr = (uint32_t) & spi_dev->rx_dummy_byte;
|
dma_init.DMA_MemoryBaseAddr = (uint32_t) & spi_dev->rx_dummy_byte;
|
||||||
dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
|
dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||||
}
|
}
|
||||||
if (spi_dev->cfg->use_crc) {
|
if (spi_dev->cfg->use_crc) {
|
||||||
/* Make sure the CRC error flag is cleared before we start */
|
/* Make sure the CRC error flag is cleared before we start */
|
||||||
SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
|
SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
|
||||||
}
|
}
|
||||||
|
|
||||||
dma_init.DMA_BufferSize = len;
|
dma_init.DMA_BufferSize = len;
|
||||||
DMA_Init(spi_dev->cfg->dma.rx.channel, &(dma_init));
|
DMA_Init(spi_dev->cfg->dma.rx.channel, &(dma_init));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Configure Tx channel
|
* Configure Tx channel
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Start with the default configuration for this peripheral */
|
/* Start with the default configuration for this peripheral */
|
||||||
dma_init = spi_dev->cfg->dma.tx.init;
|
dma_init = spi_dev->cfg->dma.tx.init;
|
||||||
|
|
||||||
if (send_buffer != NULL) {
|
if (send_buffer != NULL) {
|
||||||
/* Enable memory addr. increment - bytes written into receive buffer */
|
/* Enable memory addr. increment - bytes written into receive buffer */
|
||||||
dma_init.DMA_MemoryBaseAddr = (uint32_t) send_buffer;
|
dma_init.DMA_MemoryBaseAddr = (uint32_t) send_buffer;
|
||||||
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||||
} else {
|
} else {
|
||||||
/* Disable memory addr. increment - bytes written into dummy buffer */
|
/* Disable memory addr. increment - bytes written into dummy buffer */
|
||||||
spi_dev->tx_dummy_byte = 0xFF;
|
spi_dev->tx_dummy_byte = 0xFF;
|
||||||
dma_init.DMA_MemoryBaseAddr = (uint32_t) & spi_dev->tx_dummy_byte;
|
dma_init.DMA_MemoryBaseAddr = (uint32_t) & spi_dev->tx_dummy_byte;
|
||||||
dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
|
dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (spi_dev->cfg->use_crc) {
|
if (spi_dev->cfg->use_crc) {
|
||||||
/* The last byte of the payload will be replaced with the CRC8 */
|
/* The last byte of the payload will be replaced with the CRC8 */
|
||||||
dma_init.DMA_BufferSize = len - 1;
|
dma_init.DMA_BufferSize = len - 1;
|
||||||
} else {
|
} else {
|
||||||
dma_init.DMA_BufferSize = len;
|
dma_init.DMA_BufferSize = len;
|
||||||
}
|
}
|
||||||
|
|
||||||
DMA_Init(spi_dev->cfg->dma.tx.channel, &(dma_init));
|
DMA_Init(spi_dev->cfg->dma.tx.channel, &(dma_init));
|
||||||
|
|
||||||
/* Enable DMA interrupt if callback function active */
|
/* Enable DMA interrupt if callback function active */
|
||||||
DMA_ITConfig(spi_dev->cfg->dma.rx.channel, DMA_IT_TC, (callback != NULL) ? ENABLE : DISABLE);
|
DMA_ITConfig(spi_dev->cfg->dma.rx.channel, DMA_IT_TC, (callback != NULL) ? ENABLE : DISABLE);
|
||||||
|
|
||||||
/* Flush out the CRC registers */
|
/* Flush out the CRC registers */
|
||||||
SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
|
SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
|
||||||
(void)SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
|
(void)SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
|
||||||
SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
|
SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
|
||||||
|
|
||||||
/* Make sure to flush out the receive buffer */
|
/* Make sure to flush out the receive buffer */
|
||||||
(void)SPI_I2S_ReceiveData(spi_dev->cfg->regs);
|
(void)SPI_I2S_ReceiveData(spi_dev->cfg->regs);
|
||||||
|
|
||||||
if (spi_dev->cfg->use_crc) {
|
if (spi_dev->cfg->use_crc) {
|
||||||
/* Need a 0->1 transition to reset the CRC logic */
|
/* Need a 0->1 transition to reset the CRC logic */
|
||||||
SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
|
SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Start DMA transfers */
|
/* Start DMA transfers */
|
||||||
DMA_Cmd(spi_dev->cfg->dma.rx.channel, ENABLE);
|
DMA_Cmd(spi_dev->cfg->dma.rx.channel, ENABLE);
|
||||||
DMA_Cmd(spi_dev->cfg->dma.tx.channel, ENABLE);
|
DMA_Cmd(spi_dev->cfg->dma.tx.channel, ENABLE);
|
||||||
|
|
||||||
/* Reenable the SPI device */
|
/* Reenable the SPI device */
|
||||||
SPI_Cmd(spi_dev->cfg->regs, ENABLE);
|
SPI_Cmd(spi_dev->cfg->regs, ENABLE);
|
||||||
|
|
||||||
if (callback) {
|
if (callback) {
|
||||||
/* User has requested a callback, don't wait for the transfer to complete. */
|
/* User has requested a callback, don't wait for the transfer to complete. */
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Wait until all bytes have been transmitted/received */
|
/* Wait until all bytes have been transmitted/received */
|
||||||
while (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) ;
|
while (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) ;
|
||||||
|
|
||||||
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
||||||
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
|
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
|
||||||
|
|
||||||
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
||||||
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
|
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
|
||||||
|
|
||||||
/* Check the CRC on the transfer if enabled. */
|
/* Check the CRC on the transfer if enabled. */
|
||||||
if (spi_dev->cfg->use_crc) {
|
if (spi_dev->cfg->use_crc) {
|
||||||
/* Check the SPI CRC error flag */
|
/* Check the SPI CRC error flag */
|
||||||
if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
|
if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
|
||||||
return -4;
|
return -4;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* No error */
|
/* No error */
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void PIOS_SPI_IRQ_Handler(uint8_t spi)
|
/**
|
||||||
{
|
* Check if a transfer is in progress
|
||||||
struct pios_spi_dev *spi_dev;
|
* \param[in] spi SPI number (0 or 1)
|
||||||
|
* \return >= 0 if no transfer is in progress
|
||||||
spi_dev = find_spi_dev_by_id(spi);
|
* \return -1 if disabled SPI port selected
|
||||||
PIOS_DEBUG_Assert(spi_dev);
|
* \return -2 if unsupported SPI port selected
|
||||||
|
* \return -3 if function has been called during an ongoing DMA transfer
|
||||||
DMA_ClearFlag(spi_dev->cfg->dma.irq.flags);
|
*/
|
||||||
|
int32_t PIOS_SPI_Busy(uint8_t spi)
|
||||||
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
{
|
||||||
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
|
struct pios_spi_dev * spi_dev;
|
||||||
|
|
||||||
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
/* Get a handle for the device configuration */
|
||||||
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
|
spi_dev = find_spi_dev_by_id(spi);
|
||||||
|
|
||||||
if (spi_dev->callback != NULL) {
|
if (!spi_dev) {
|
||||||
bool crc_ok = TRUE;
|
/* Undefined SPI port for this board (see pios_board.c) */
|
||||||
uint8_t crc_val;
|
return -2;
|
||||||
|
}
|
||||||
if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
|
|
||||||
crc_ok = FALSE;
|
/* DMA buffer has data or SPI transmit register not empty or SPI is busy*/
|
||||||
SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
|
if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel) ||
|
||||||
}
|
!SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE) ||
|
||||||
crc_val = SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
|
SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY))
|
||||||
spi_dev->callback(crc_ok, crc_val);
|
{
|
||||||
}
|
return -3;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
return(0);
|
||||||
|
}
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
void PIOS_SPI_IRQ_Handler(uint8_t spi)
|
||||||
|
{
|
||||||
|
struct pios_spi_dev *spi_dev;
|
||||||
|
|
||||||
|
spi_dev = find_spi_dev_by_id(spi);
|
||||||
|
PIOS_DEBUG_Assert(spi_dev);
|
||||||
|
|
||||||
|
DMA_ClearFlag(spi_dev->cfg->dma.irq.flags);
|
||||||
|
|
||||||
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
||||||
|
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
|
||||||
|
|
||||||
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
||||||
|
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
|
||||||
|
|
||||||
|
if (spi_dev->callback != NULL) {
|
||||||
|
bool crc_ok = TRUE;
|
||||||
|
uint8_t crc_val;
|
||||||
|
|
||||||
|
if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
|
||||||
|
crc_ok = FALSE;
|
||||||
|
SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
|
||||||
|
}
|
||||||
|
crc_val = SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
|
||||||
|
spi_dev->callback(crc_ok, crc_val);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|||||||
@ -1,59 +1,60 @@
|
|||||||
/**
|
/**
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @addtogroup PIOS PIOS Core hardware abstraction layer
|
* @addtogroup PIOS PIOS Core hardware abstraction layer
|
||||||
* @{
|
* @{
|
||||||
* @addtogroup PIOS_SPI SPI Functions
|
* @addtogroup PIOS_SPI SPI Functions
|
||||||
* @{
|
* @{
|
||||||
*
|
*
|
||||||
* @file pios_spi.h
|
* @file pios_spi.h
|
||||||
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
|
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
|
||||||
* Parts by Thorsten Klose (tk@midibox.org)
|
* Parts by Thorsten Klose (tk@midibox.org)
|
||||||
* @brief SPI functions header.
|
* @brief SPI functions header.
|
||||||
* @see The GNU Public License (GPL) Version 3
|
* @see The GNU Public License (GPL) Version 3
|
||||||
*
|
*
|
||||||
*****************************************************************************/
|
*****************************************************************************/
|
||||||
/*
|
/*
|
||||||
* This program is free software; you can redistribute it and/or modify
|
* This program is free software; you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU General Public License as published by
|
* it under the terms of the GNU General Public License as published by
|
||||||
* the Free Software Foundation; either version 3 of the License, or
|
* the Free Software Foundation; either version 3 of the License, or
|
||||||
* (at your option) any later version.
|
* (at your option) any later version.
|
||||||
*
|
*
|
||||||
* This program is distributed in the hope that it will be useful, but
|
* This program is distributed in the hope that it will be useful, but
|
||||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||||
* for more details.
|
* for more details.
|
||||||
*
|
*
|
||||||
* You should have received a copy of the GNU General Public License along
|
* You should have received a copy of the GNU General Public License along
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef PIOS_SPI_H
|
#ifndef PIOS_SPI_H
|
||||||
#define PIOS_SPI_H
|
#define PIOS_SPI_H
|
||||||
|
|
||||||
/* Global types */
|
/* Global types */
|
||||||
typedef enum {
|
typedef enum {
|
||||||
PIOS_SPI_PRESCALER_2 = 0,
|
PIOS_SPI_PRESCALER_2 = 0,
|
||||||
PIOS_SPI_PRESCALER_4 = 1,
|
PIOS_SPI_PRESCALER_4 = 1,
|
||||||
PIOS_SPI_PRESCALER_8 = 2,
|
PIOS_SPI_PRESCALER_8 = 2,
|
||||||
PIOS_SPI_PRESCALER_16 = 3,
|
PIOS_SPI_PRESCALER_16 = 3,
|
||||||
PIOS_SPI_PRESCALER_32 = 4,
|
PIOS_SPI_PRESCALER_32 = 4,
|
||||||
PIOS_SPI_PRESCALER_64 = 5,
|
PIOS_SPI_PRESCALER_64 = 5,
|
||||||
PIOS_SPI_PRESCALER_128 = 6,
|
PIOS_SPI_PRESCALER_128 = 6,
|
||||||
PIOS_SPI_PRESCALER_256 = 7
|
PIOS_SPI_PRESCALER_256 = 7
|
||||||
} SPIPrescalerTypeDef;
|
} SPIPrescalerTypeDef;
|
||||||
|
|
||||||
/* Public Functions */
|
/* Public Functions */
|
||||||
extern int32_t PIOS_SPI_Init(void);
|
extern int32_t PIOS_SPI_Init(void);
|
||||||
extern int32_t PIOS_SPI_SetClockSpeed(uint8_t spi, SPIPrescalerTypeDef spi_prescaler);
|
extern int32_t PIOS_SPI_SetClockSpeed(uint8_t spi, SPIPrescalerTypeDef spi_prescaler);
|
||||||
extern int32_t PIOS_SPI_RC_PinSet(uint8_t spi, uint8_t pin_value);
|
extern int32_t PIOS_SPI_RC_PinSet(uint8_t spi, uint8_t pin_value);
|
||||||
extern int32_t PIOS_SPI_TransferByte(uint8_t spi, uint8_t b);
|
extern int32_t PIOS_SPI_TransferByte(uint8_t spi, uint8_t b);
|
||||||
extern int32_t PIOS_SPI_TransferBlock(uint8_t spi, const uint8_t * send_buffer, uint8_t * receive_buffer, uint16_t len, void *callback);
|
extern int32_t PIOS_SPI_TransferBlock(uint8_t spi, const uint8_t * send_buffer, uint8_t * receive_buffer, uint16_t len, void *callback);
|
||||||
extern void PIOS_SPI_IRQ_Handler(uint8_t spi);
|
extern int32_t PIOS_SPI_Busy(uint8_t spi);
|
||||||
|
extern void PIOS_SPI_IRQ_Handler(uint8_t spi);
|
||||||
#endif /* PIOS_SPI_H */
|
|
||||||
|
#endif /* PIOS_SPI_H */
|
||||||
/**
|
|
||||||
* @}
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
* @}
|
||||||
|
*/
|
||||||
|
|||||||
Loading…
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Reference in New Issue
Block a user