mirror of
https://bitbucket.org/librepilot/librepilot.git
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LP-96 - remove unused files
This commit is contained in:
Alessio Morale
a*morale
parent
b88681c69f
commit
4c2557c29a
@ -1,356 +0,0 @@
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/* This is the size of the stack for early init and for all FreeRTOS IRQs */
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_irq_stack_size = 0x800;
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/* Check valid alignment for VTOR */
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ASSERT(ORIGIN(BL_FLASH) == ALIGN(ORIGIN(BL_FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
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/*
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this sends all unreferenced IRQHandlers to reset
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*/
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PROVIDE ( Undefined_Handler = 0 ) ;
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PROVIDE ( SWI_Handler = 0 ) ;
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PROVIDE ( IRQ_Handler = 0 ) ;
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PROVIDE ( Prefetch_Handler = 0 ) ;
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PROVIDE ( Abort_Handler = 0 ) ;
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PROVIDE ( FIQ_Handler = 0 ) ;
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PROVIDE ( NMI_Handler = 0 ) ;
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PROVIDE ( HardFault_Handler = 0 ) ;
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PROVIDE ( MemManage_Handler = 0 ) ;
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PROVIDE ( BusFault_Handler = 0 ) ;
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PROVIDE ( UsageFault_Handler = 0 ) ;
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PROVIDE ( vPortSVCHandler = 0 ) ;
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PROVIDE ( DebugMon_Handler = 0 ) ;
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PROVIDE ( xPortPendSVHandler = 0 ) ;
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PROVIDE ( xPortSysTickHandler = 0 ) ;
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PROVIDE ( WWDG_IRQHandler = 0 ) ;
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PROVIDE ( PVD_IRQHandler = 0 ) ;
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PROVIDE ( TAMPER_IRQHandler = 0 ) ;
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PROVIDE ( RTC_IRQHandler = 0 ) ;
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PROVIDE ( FLASH_IRQHandler = 0 ) ;
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PROVIDE ( RCC_IRQHandler = 0 ) ;
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PROVIDE ( EXTI0_IRQHandler = 0 ) ;
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PROVIDE ( EXTI1_IRQHandler = 0 ) ;
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PROVIDE ( EXTI2_IRQHandler = 0 ) ;
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PROVIDE ( EXTI3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
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PROVIDE ( ADC_IRQHandler = 0 ) ;
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PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
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PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
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PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
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PROVIDE ( TIM2_IRQHandler = 0 ) ;
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PROVIDE ( TIM3_IRQHandler = 0 ) ;
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PROVIDE ( TIM4_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
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PROVIDE ( SPI1_IRQHandler = 0 ) ;
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PROVIDE ( SPI2_IRQHandler = 0 ) ;
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PROVIDE ( USART1_IRQHandler = 0 ) ;
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PROVIDE ( USART2_IRQHandler = 0 ) ;
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PROVIDE ( USART3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
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PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
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PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
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PROVIDE ( ADC3_IRQHandler = 0 ) ;
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PROVIDE ( FSMC_IRQHandler = 0 ) ;
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PROVIDE ( SDIO_IRQHandler = 0 ) ;
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PROVIDE ( TIM5_IRQHandler = 0 ) ;
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PROVIDE ( SPI3_IRQHandler = 0 ) ;
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PROVIDE ( UART4_IRQHandler = 0 ) ;
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PROVIDE ( UART5_IRQHandler = 0 ) ;
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PROVIDE ( TIM6_IRQHandler = 0 ) ;
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PROVIDE ( TIM7_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/*this allows to compile the ST lib in "non-debug" mode*/
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/* Peripheral and SRAM base address in the alias region */
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PERIPH_BB_BASE = 0x42000000;
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SRAM_BB_BASE = 0x22000000;
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/* Peripheral and SRAM base address in the bit-band region */
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SRAM_BASE = 0x20000000;
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PERIPH_BASE = 0x40000000;
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/* Flash registers base address */
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PROVIDE ( FLASH_BASE = 0x40022000);
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/* Flash Option Bytes base address */
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PROVIDE ( OB_BASE = 0x1FFFF800);
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/* Peripheral memory map */
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APB1PERIPH_BASE = PERIPH_BASE ;
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APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
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AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
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PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
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PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
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PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
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PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
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PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
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PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
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PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
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PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
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PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
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PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
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PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
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PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
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PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
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PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
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PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
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PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
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PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
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PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
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PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
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PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
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PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
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/* System Control Space memory map */
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SCS_BASE = 0xE000E000;
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PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
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PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
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PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
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/* Sections Definitions */
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SECTIONS
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{
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/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
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.isr_vector :
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{
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PROVIDE (pios_isr_vector_table_base = .);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
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.flashtext :
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{
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. = ALIGN(4);
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*(.flashtext) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* the program code is stored in the .text section, which goes to Flash */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* remaining code */
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*(.text.*) /* remaining code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(4);
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_etext = .;
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/* This is used by the startup in order to initialize the .data secion */
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_sidata = _etext;
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} > BL_FLASH
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/*
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* This stack is used both as the initial sp during early init as well as ultimately
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* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
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* is used for _all_ interrupt handlers. The end of this stack should be placed
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* against the lowest address in RAM so that a stack overrun results in a hard fault
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* at the first access beyond the end of the stack.
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*/
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.irq_stack :
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{
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. = ALIGN(4);
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_irq_stack_end = . ;
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. = . + _irq_stack_size ;
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. = ALIGN(4);
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_irq_stack_top = . - 4 ;
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_init_stack_top = _irq_stack_top;
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. = ALIGN(4);
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} >RAM
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/* This is the initialized data section
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The program executes knowing that the data is in the RAM
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but the loader puts the initial values in the FLASH (inidata).
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It is one task of the startup to copy the initial values from FLASH to RAM. */
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.data : AT ( _sidata )
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_sdata = . ;
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*(.data)
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*(.data.*)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM
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/* This is the uninitialized data section */
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.bss :
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .;
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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} >RAM
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PROVIDE ( end = _ebss );
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PROVIDE ( _end = _ebss );
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/* this is the FLASH Bank1 */
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/* the C or assembly source must explicitly place the code or data there
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using the "section" attribute */
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.b1text :
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{
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*(.b1text) /* remaining code */
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*(.b1rodata) /* read-only data (constants) */
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*(.b1rodata*)
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} >FLASHB1
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/* this is the EXTMEM */
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/* the C or assembly source must explicitly place the code or data there
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using the "section" attribute */
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/* EXTMEM Bank0 */
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.eb0text :
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{
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*(.eb0text) /* remaining code */
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*(.eb0rodata) /* read-only data (constants) */
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*(.eb0rodata*)
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} >EXTMEMB0
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/* EXTMEM Bank1 */
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.eb1text :
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{
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*(.eb1text) /* remaining code */
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*(.eb1rodata) /* read-only data (constants) */
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*(.eb1rodata*)
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} >EXTMEMB1
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/* EXTMEM Bank2 */
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.eb2text :
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{
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*(.eb2text) /* remaining code */
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*(.eb2rodata) /* read-only data (constants) */
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*(.eb2rodata*)
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} >EXTMEMB2
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/* EXTMEM Bank0 */
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.eb3text :
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{
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*(.eb3text) /* remaining code */
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*(.eb3rodata) /* read-only data (constants) */
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*(.eb3rodata*)
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} >EXTMEMB3
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__exidx_start = .;
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__exidx_end = .;
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.boardinfo :
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{
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. = ALIGN(4);
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KEEP(*(.boardinfo))
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. = ALIGN(4);
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} > BD_INFO
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/* after that it's only debugging information. */
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/* remove the debugging information from the standard libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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Symbols in the DWARF debugging sections are relative to the beginning
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of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
|
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.debug_loc 0 : { *(.debug_loc) }
|
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
|
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.debug_typenames 0 : { *(.debug_typenames) }
|
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.debug_varnames 0 : { *(.debug_varnames) }
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}
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@ -1,12 +0,0 @@
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x10000
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BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x05000 - 0x00080
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BD_INFO (r) : ORIGIN = 0x08005000 - 0x80, LENGTH = 0x00080
|
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FLASH (rx) : ORIGIN = 0x08005000, LENGTH = 0x80000 - 0x05000
|
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FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
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EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
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EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
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EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
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EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
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}
|
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@ -1,383 +0,0 @@
|
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/* This is the size of the stack for early init and for all FreeRTOS IRQs */
|
||||
_irq_stack_size = 0x800;
|
||||
/* This is the size of the stack for early init: life span is until scheduler starts */
|
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_init_stack_size = 0x800;
|
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|
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/* Check valid alignment for VTOR */
|
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ASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
|
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|
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/*
|
||||
this sends all unreferenced IRQHandlers to reset
|
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*/
|
||||
|
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|
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PROVIDE ( Undefined_Handler = 0 ) ;
|
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PROVIDE ( SWI_Handler = 0 ) ;
|
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PROVIDE ( IRQ_Handler = 0 ) ;
|
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PROVIDE ( Prefetch_Handler = 0 ) ;
|
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PROVIDE ( Abort_Handler = 0 ) ;
|
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PROVIDE ( FIQ_Handler = 0 ) ;
|
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|
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PROVIDE ( NMI_Handler = 0 ) ;
|
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PROVIDE ( HardFault_Handler = 0 ) ;
|
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PROVIDE ( MemManage_Handler = 0 ) ;
|
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PROVIDE ( BusFault_Handler = 0 ) ;
|
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PROVIDE ( UsageFault_Handler = 0 ) ;
|
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PROVIDE ( vPortSVCHandler = 0 ) ;
|
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PROVIDE ( DebugMon_Handler = 0 ) ;
|
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PROVIDE ( xPortPendSVHandler = 0 ) ;
|
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PROVIDE ( xPortSysTickHandler = 0 ) ;
|
||||
|
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PROVIDE ( WWDG_IRQHandler = 0 ) ;
|
||||
PROVIDE ( PVD_IRQHandler = 0 ) ;
|
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PROVIDE ( TAMPER_IRQHandler = 0 ) ;
|
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PROVIDE ( RTC_IRQHandler = 0 ) ;
|
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PROVIDE ( FLASH_IRQHandler = 0 ) ;
|
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PROVIDE ( RCC_IRQHandler = 0 ) ;
|
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PROVIDE ( EXTI0_IRQHandler = 0 ) ;
|
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PROVIDE ( EXTI1_IRQHandler = 0 ) ;
|
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PROVIDE ( EXTI2_IRQHandler = 0 ) ;
|
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PROVIDE ( EXTI3_IRQHandler = 0 ) ;
|
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PROVIDE ( EXTI4_IRQHandler = 0 ) ;
|
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PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
|
||||
PROVIDE ( ADC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
|
||||
PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM4_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SPI1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SPI2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USART1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USART2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USART3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
|
||||
PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( ADC3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( FSMC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SDIO_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SPI3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( UART4_IRQHandler = 0 ) ;
|
||||
PROVIDE ( UART5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM6_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM7_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
/*this allows to compile the ST lib in "non-debug" mode*/
|
||||
|
||||
|
||||
/* Peripheral and SRAM base address in the alias region */
|
||||
PERIPH_BB_BASE = 0x42000000;
|
||||
SRAM_BB_BASE = 0x22000000;
|
||||
|
||||
/* Peripheral and SRAM base address in the bit-band region */
|
||||
SRAM_BASE = 0x20000000;
|
||||
PERIPH_BASE = 0x40000000;
|
||||
|
||||
/* Flash registers base address */
|
||||
PROVIDE ( FLASH_BASE = 0x40022000);
|
||||
/* Flash Option Bytes base address */
|
||||
PROVIDE ( OB_BASE = 0x1FFFF800);
|
||||
|
||||
/* Peripheral memory map */
|
||||
APB1PERIPH_BASE = PERIPH_BASE ;
|
||||
APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
|
||||
AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
|
||||
|
||||
PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
|
||||
PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
|
||||
PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
|
||||
PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
|
||||
PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
|
||||
PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
|
||||
PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
|
||||
PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
|
||||
PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
|
||||
PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
|
||||
PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
|
||||
PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
|
||||
PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
|
||||
PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
|
||||
|
||||
PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
|
||||
PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
|
||||
PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
|
||||
PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
|
||||
PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
|
||||
PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
|
||||
PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
|
||||
PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
|
||||
PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
|
||||
PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
|
||||
PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
|
||||
PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
|
||||
|
||||
PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
|
||||
PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
|
||||
PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
|
||||
PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
|
||||
PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
|
||||
PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
|
||||
PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
|
||||
PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
|
||||
PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
|
||||
|
||||
/* System Control Space memory map */
|
||||
SCS_BASE = 0xE000E000;
|
||||
|
||||
PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
|
||||
PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
|
||||
PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
|
||||
|
||||
PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
|
||||
|
||||
/* Sections Definitions */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
PROVIDE (pios_isr_vector_table_base = .);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
|
||||
.flashtext :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.flashtext) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* module sections */
|
||||
.initcallmodule.init :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__module_initcall_start = .;
|
||||
KEEP(*(.initcallmodule.init))
|
||||
. = ALIGN(4);
|
||||
__module_initcall_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* the program code is stored in the .text section, which goes to Flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = _etext;
|
||||
} >FLASH
|
||||
|
||||
/*
|
||||
* This stack is used both as the initial sp during early init as well as ultimately
|
||||
* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
|
||||
* is used for _all_ interrupt handlers. The end of this stack should be placed
|
||||
* against the lowest address in RAM so that a stack overrun results in a hard fault
|
||||
* at the first access beyond the end of the stack.
|
||||
*/
|
||||
.irq_stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_irq_stack_end = . ;
|
||||
. = . + _irq_stack_size ;
|
||||
. = ALIGN(4);
|
||||
_irq_stack_top = . - 4 ;
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
|
||||
|
||||
/* This is the initialized data section
|
||||
The program executes knowing that the data is in the RAM
|
||||
but the loader puts the initial values in the FLASH (inidata).
|
||||
It is one task of the startup to copy the initial values from FLASH to RAM. */
|
||||
.data : AT ( _sidata )
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >RAM
|
||||
|
||||
|
||||
|
||||
/* This is the uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
} >RAM
|
||||
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sheap = . ;
|
||||
_sheap_pre_rtos = . ;
|
||||
*(.heap)
|
||||
. = ALIGN(4);
|
||||
_eheap = . ;
|
||||
_eheap_pre_rtos = . ;
|
||||
_init_stack_end = . ;
|
||||
_sheap_post_rtos = . ;
|
||||
. = . + _init_stack_size ;
|
||||
. = ALIGN(4);
|
||||
_eheap_post_rtos = . ;
|
||||
_init_stack_top = . - 4 ;
|
||||
} > RAM
|
||||
|
||||
_eram = ORIGIN(RAM) + LENGTH(RAM) ;
|
||||
_ebss = _eram ;
|
||||
|
||||
/* keep the heap section at the end of the SRAM
|
||||
* this will allow to claim the remaining bytes not used
|
||||
* at run time! (done by the reset vector).
|
||||
*/
|
||||
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
|
||||
/* this is the FLASH Bank1 */
|
||||
/* the C or assembly source must explicitly place the code or data there
|
||||
using the "section" attribute */
|
||||
.b1text :
|
||||
{
|
||||
*(.b1text) /* remaining code */
|
||||
*(.b1rodata) /* read-only data (constants) */
|
||||
*(.b1rodata*)
|
||||
} >FLASHB1
|
||||
|
||||
/* this is the EXTMEM */
|
||||
/* the C or assembly source must explicitly place the code or data there
|
||||
using the "section" attribute */
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb0text :
|
||||
{
|
||||
*(.eb0text) /* remaining code */
|
||||
*(.eb0rodata) /* read-only data (constants) */
|
||||
*(.eb0rodata*)
|
||||
} >EXTMEMB0
|
||||
|
||||
/* EXTMEM Bank1 */
|
||||
.eb1text :
|
||||
{
|
||||
*(.eb1text) /* remaining code */
|
||||
*(.eb1rodata) /* read-only data (constants) */
|
||||
*(.eb1rodata*)
|
||||
} >EXTMEMB1
|
||||
|
||||
/* EXTMEM Bank2 */
|
||||
.eb2text :
|
||||
{
|
||||
*(.eb2text) /* remaining code */
|
||||
*(.eb2rodata) /* read-only data (constants) */
|
||||
*(.eb2rodata*)
|
||||
} >EXTMEMB2
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb3text :
|
||||
{
|
||||
*(.eb3text) /* remaining code */
|
||||
*(.eb3rodata) /* read-only data (constants) */
|
||||
*(.eb3rodata*)
|
||||
} >EXTMEMB3
|
||||
|
||||
__exidx_start = .;
|
||||
__exidx_end = .;
|
||||
|
||||
/* after that it's only debugging information. */
|
||||
|
||||
/* remove the debugging information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
||||
|
||||
@ -1,477 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f10x_hd.s
|
||||
* @author MCD Application Team / David Ankers: Vector table for FreeRTOS
|
||||
* @version V3.1.2
|
||||
* @date 09/28/2009
|
||||
* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||
* to be used as data memory (optional, to be enabled by user)
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @copy
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global SystemInit_ExtMemCtl_Dummy
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
.equ Initial_spTop, 0x20000400
|
||||
.equ BootRAM, 0xF1E0F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief Dummy SystemInit_ExtMemCtl function
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits
|
||||
SystemInit_ExtMemCtl_Dummy:
|
||||
bx lr
|
||||
.size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word TAMPER_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_2_IRQHandler
|
||||
.word USB_HP_CAN1_TX_IRQHandler
|
||||
.word USB_LP_CAN1_RX0_IRQHandler
|
||||
.word CAN1_RX1_IRQHandler
|
||||
.word CAN1_SCE_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTCAlarm_IRQHandler
|
||||
.word USBWakeUp_IRQHandler
|
||||
.word TIM8_BRK_IRQHandler
|
||||
.word TIM8_UP_IRQHandler
|
||||
.word TIM8_TRG_COM_IRQHandler
|
||||
.word TIM8_CC_IRQHandler
|
||||
.word ADC3_IRQHandler
|
||||
.word FSMC_IRQHandler
|
||||
.word SDIO_IRQHandler
|
||||
.word TIM5_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_5_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||
STM32F10x High Density devices. */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_CAN1_TX_IRQHandler
|
||||
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.thumb_set RTCAlarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBWakeUp_IRQHandler
|
||||
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_5_IRQHandler
|
||||
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit_ExtMemCtl
|
||||
.thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy
|
||||
|
||||
@ -1,541 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f10x_hd.s
|
||||
* @author MCD Application Team / David Ankers: Vector table for FreeRTOS
|
||||
* @version V3.1.2
|
||||
* @date 09/28/2009
|
||||
* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||
* to be used as data memory (optional, to be enabled by user)
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @copy
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global SystemInit_ExtMemCtl_Dummy
|
||||
.global Default_Handler
|
||||
.global xPortIncreaseHeapSize
|
||||
.global Stack_Change
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
.equ BootRAM, 0xF1E0F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
|
||||
required, then adjust the Register Addresses */
|
||||
bl SystemInit_ExtMemCtl
|
||||
/* restore original stack pointer */
|
||||
LDR r0, =_irq_stack_top
|
||||
MSR msp, r0
|
||||
LDR r2, =_init_stack_top
|
||||
MSR psp, r2
|
||||
/* check if irq and init stack are the same */
|
||||
/* if they are, we don't do stack swap */
|
||||
/* and lets bypass the monitoring as well for now */
|
||||
cmp r0, r2
|
||||
beq SectionBssInit
|
||||
/* DO
|
||||
* - stay in thread process mode
|
||||
* - stay in privilege level
|
||||
* - use process stack
|
||||
*/
|
||||
movs r0, #2
|
||||
MSR control, r0
|
||||
ISB
|
||||
/* Fill IRQ stack for watermark monitoring */
|
||||
ldr r2, =_irq_stack_end
|
||||
b LoopFillIRQStack
|
||||
|
||||
FillIRQStack:
|
||||
movw r3, #0xA5A5
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillIRQStack:
|
||||
ldr r3, = _irq_stack_top
|
||||
cmp r2, r3
|
||||
bcc FillIRQStack
|
||||
|
||||
SectionBssInit:
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
/* will never return here */
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that swaps stack (from end of heap to irq_stack).
|
||||
* Also reclaim the heap that was used as a stack.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Stack_Change
|
||||
.weak Stack_Change
|
||||
.type Stack_Change, %function
|
||||
Stack_Change:
|
||||
mov r4, lr
|
||||
/* Switches stack back momentarily to MSP */
|
||||
movs r0, #0
|
||||
msr control, r0
|
||||
Heap_Reclaim:
|
||||
/* add heap_post_rtos to the heap (if the capability/function exist) */
|
||||
/* Also claim the unused memory (between end of heap to end of memory */
|
||||
/* CAREFULL: the heap section must be the last section in RAM in order this to work */
|
||||
ldr r0, = _init_stack_size
|
||||
ldr r1, = _eheap_post_rtos
|
||||
ldr r2, = _eram
|
||||
subs r2, r2, r1
|
||||
adds r0, r0, r2
|
||||
bl xPortIncreaseHeapSize
|
||||
bx r4
|
||||
.size Stack_Change, .-Stack_Change
|
||||
|
||||
/**
|
||||
* @brief Dummy SystemInit_ExtMemCtl function
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits
|
||||
SystemInit_ExtMemCtl_Dummy:
|
||||
bx lr
|
||||
.size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _irq_stack_top
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word vPortSVCHandler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word xPortPendSVHandler
|
||||
.word xPortSysTickHandler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word TAMPER_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_2_IRQHandler
|
||||
.word USB_HP_CAN1_TX_IRQHandler
|
||||
.word USB_LP_CAN1_RX0_IRQHandler
|
||||
.word CAN1_RX1_IRQHandler
|
||||
.word CAN1_SCE_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTCAlarm_IRQHandler
|
||||
.word USBWakeUp_IRQHandler
|
||||
.word TIM8_BRK_IRQHandler
|
||||
.word TIM8_UP_IRQHandler
|
||||
.word TIM8_TRG_COM_IRQHandler
|
||||
.word TIM8_CC_IRQHandler
|
||||
.word ADC3_IRQHandler
|
||||
.word FSMC_IRQHandler
|
||||
.word SDIO_IRQHandler
|
||||
.word TIM5_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_5_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||
STM32F10x High Density devices. */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_CAN1_TX_IRQHandler
|
||||
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.thumb_set RTCAlarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBWakeUp_IRQHandler
|
||||
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_5_IRQHandler
|
||||
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit_ExtMemCtl
|
||||
.thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy
|
||||
|
||||
@ -1,355 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f10x_md.s
|
||||
* @author MCD Application Team / Angus Peart
|
||||
* @version V3.1.2
|
||||
* @date 09/28/2009
|
||||
* @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
*******************************************************************************
|
||||
* @copy
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF108F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word TAMPER_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_2_IRQHandler
|
||||
.word USB_HP_CAN1_TX_IRQHandler
|
||||
.word USB_LP_CAN1_RX0_IRQHandler
|
||||
.word CAN1_RX1_IRQHandler
|
||||
.word CAN1_SCE_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTCAlarm_IRQHandler
|
||||
.word USBWakeUp_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||
STM32F10x Medium Density devices. */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_CAN1_TX_IRQHandler
|
||||
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.thumb_set RTCAlarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBWakeUp_IRQHandler
|
||||
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user