From aadd17d1b47e07daa6406819a1afcafbcc66ef4c Mon Sep 17 00:00:00 2001 From: Vladimir Zidar Date: Sun, 4 Jun 2017 22:38:34 +0200 Subject: [PATCH 1/2] LP-527 Remove peripheral clock managing code --- flight/pios/stm32f0x/pios_adc.c | 3 -- flight/pios/stm32f0x/pios_bkp.c | 6 ---- flight/pios/stm32f0x/pios_bl_helper.c | 4 +-- flight/pios/stm32f0x/pios_delay.c | 4 +-- flight/pios/stm32f0x/pios_gpio.c | 16 ---------- flight/pios/stm32f0x/pios_i2c.c | 4 --- flight/pios/stm32f0x/pios_rtc.c | 1 - flight/pios/stm32f0x/pios_spi.c | 16 +--------- flight/pios/stm32f0x/pios_sys.c | 19 ++++++++++- flight/pios/stm32f0x/pios_tim.c | 45 --------------------------- flight/pios/stm32f0x/pios_usart.c | 3 -- flight/pios/stm32f0x/pios_wdg.c | 1 - 12 files changed, 22 insertions(+), 100 deletions(-) diff --git a/flight/pios/stm32f0x/pios_adc.c b/flight/pios/stm32f0x/pios_adc.c index 3f5701449..1c33422a1 100644 --- a/flight/pios/stm32f0x/pios_adc.c +++ b/flight/pios/stm32f0x/pios_adc.c @@ -244,9 +244,6 @@ void PIOS_ADC_Config(uint32_t oversampling) pios_adc_dev->fir_coeffs[i] = 1; } pios_adc_dev->fir_coeffs[pios_adc_dev->adc_oversample] = pios_adc_dev->adc_oversample; - - /* Enable DMA1 clock */ - RCC_AHBPeriphClockCmd(pios_adc_dev->cfg->dma.ahb_clk, ENABLE); } /** diff --git a/flight/pios/stm32f0x/pios_bkp.c b/flight/pios/stm32f0x/pios_bkp.c index d15063ff8..a20a199bd 100644 --- a/flight/pios/stm32f0x/pios_bkp.c +++ b/flight/pios/stm32f0x/pios_bkp.c @@ -57,12 +57,6 @@ const uint32_t pios_bkp_registers_map[] = { void PIOS_BKP_Init(void) { - /* Enable CRC clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE); - - /* Enable PWR and BKP clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - /* Clear Tamper pin Event(TE) pending flag */ RTC_ClearFlag(RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F); } diff --git a/flight/pios/stm32f0x/pios_bl_helper.c b/flight/pios/stm32f0x/pios_bl_helper.c index af96880e4..755268191 100644 --- a/flight/pios/stm32f0x/pios_bl_helper.c +++ b/flight/pios/stm32f0x/pios_bl_helper.c @@ -119,8 +119,6 @@ void PIOS_BL_HELPER_FLASH_Read_Description(uint8_t *array, uint8_t size) } void PIOS_BL_HELPER_CRC_Ini() -{ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE); -} +{} #endif /* PIOS_INCLUDE_BL_HELPER */ diff --git a/flight/pios/stm32f0x/pios_delay.c b/flight/pios/stm32f0x/pios_delay.c index 1a27f182d..90ae0975b 100644 --- a/flight/pios/stm32f0x/pios_delay.c +++ b/flight/pios/stm32f0x/pios_delay.c @@ -47,8 +47,7 @@ int32_t PIOS_DELAY_Init(void) { // unfortunately F0 does not allow access to DWT and CoreDebug functionality from CPU side - // thus we are going to use timer3 for timing measurement - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); + // thus we are going to use timer2 for timing measurement const TIM_TimeBaseInitTypeDef timerInit = { .TIM_Prescaler = (48000000 / 1000000), @@ -57,6 +56,7 @@ int32_t PIOS_DELAY_Init(void) .TIM_Period = 0xFFFFFFFF, .TIM_RepetitionCounter = 0x0000, }; + // Stop timer TIM_Cmd(TIM2, DISABLE); // Configure timebase and internal clock diff --git a/flight/pios/stm32f0x/pios_gpio.c b/flight/pios/stm32f0x/pios_gpio.c index 17830d2cd..eb42c9711 100644 --- a/flight/pios/stm32f0x/pios_gpio.c +++ b/flight/pios/stm32f0x/pios_gpio.c @@ -45,22 +45,6 @@ int32_t PIOS_GPIO_Init(uint32_t *gpios_dev_id, const struct pios_gpio_cfg *cfg) for (uint8_t i = 0; i < cfg->num_gpios; i++) { const struct pios_gpio *gpio = &(cfg->gpios[i]); - /* Enable the peripheral clock for the GPIO */ - switch ((uint32_t)gpio->pin.gpio) { - case (uint32_t)GPIOA: - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); - break; - case (uint32_t)GPIOB: - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); - break; - case (uint32_t)GPIOC: - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE); - break; - default: - PIOS_Assert(0); - break; - } - if (gpio->remap) { GPIO_PinAFConfig(gpio->pin.gpio, gpio->pin.init.GPIO_Pin, gpio->remap); } diff --git a/flight/pios/stm32f0x/pios_i2c.c b/flight/pios/stm32f0x/pios_i2c.c index 385c5295e..80299e32d 100644 --- a/flight/pios/stm32f0x/pios_i2c.c +++ b/flight/pios/stm32f0x/pios_i2c.c @@ -541,13 +541,9 @@ int32_t PIOS_I2C_Init(uint32_t *i2c_id, const struct pios_i2c_adapter_cfg *cfg) /* Enable the associated peripheral clock */ switch ((uint32_t)i2c_adapter->cfg->regs) { case (uint32_t)I2C1: - /* Enable I2C peripheral clock (APB1 == slow speed) */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); RCC_I2CCLKConfig(RCC_I2C1CLK_HSI); break; case (uint32_t)I2C2: - /* Enable I2C peripheral clock (APB1 == slow speed) */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE); break; } diff --git a/flight/pios/stm32f0x/pios_rtc.c b/flight/pios/stm32f0x/pios_rtc.c index 8fe758145..bfa567021 100644 --- a/flight/pios/stm32f0x/pios_rtc.c +++ b/flight/pios/stm32f0x/pios_rtc.c @@ -51,7 +51,6 @@ void PIOS_RTC_Init(const struct pios_rtc_cfg *cfg) { RCC_BackupResetCmd(ENABLE); RCC_BackupResetCmd(DISABLE); - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); PWR_BackupAccessCmd(ENABLE); // Divide external 8 MHz clock to 1 MHz RCC_RTCCLKConfig(cfg->clksrc); diff --git a/flight/pios/stm32f0x/pios_spi.c b/flight/pios/stm32f0x/pios_spi.c index 5758ce742..f408ab798 100644 --- a/flight/pios/stm32f0x/pios_spi.c +++ b/flight/pios/stm32f0x/pios_spi.c @@ -91,22 +91,8 @@ int32_t PIOS_SPI_Init(uint32_t *spi_id, const struct pios_spi_cfg *cfg) vSemaphoreCreateBinary(spi_dev->busy); xSemaphoreGive(spi_dev->busy); #else - spi_dev->busy = 0; + spi_dev->busy = 0; #endif - /* Enable the associated peripheral clock */ - switch ((uint32_t)spi_dev->cfg->regs) { - case (uint32_t)SPI1: - /* Enable SPI peripheral clock (APB2 == high speed) */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); - break; - case (uint32_t)SPI2: - /* Enable SPI peripheral clock (APB1 == slow speed) */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); - break; - } - /* Enable DMA clock */ - RCC_AHBPeriphClockCmd(spi_dev->cfg->dma.ahb_clk, ENABLE); - /* Disable callback function */ spi_dev->callback = NULL; diff --git a/flight/pios/stm32f0x/pios_sys.c b/flight/pios/stm32f0x/pios_sys.c index aae142302..275b6cc02 100644 --- a/flight/pios/stm32f0x/pios_sys.c +++ b/flight/pios/stm32f0x/pios_sys.c @@ -72,13 +72,30 @@ void PIOS_SYS_Init(void) RCC_AHBPeriphClockCmd( RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | + RCC_AHBPeriph_GPIOC | RCC_AHBPeriph_FLITF | RCC_AHBPeriph_SRAM | - RCC_AHBPeriph_DMA1 + RCC_AHBPeriph_DMA1 | + RCC_AHBPeriph_CRC + , ENABLE); + + RCC_APB1PeriphClockCmd( + RCC_APB1Periph_USART2 | + RCC_APB1Periph_USART3 | + RCC_APB1Periph_WWDG | + RCC_APB1Periph_PWR | + RCC_APB1Periph_TIM2 | + RCC_APB1Periph_TIM3 | + RCC_APB1Periph_I2C1 | + RCC_APB1Periph_I2C2 | + RCC_APB1Periph_SPI2 , ENABLE); RCC_APB2PeriphClockCmd( RCC_APB2Periph_SYSCFG | + RCC_APB2Periph_USART1 | + RCC_APB2Periph_SPI1 | + RCC_APB2Periph_TIM1 | 0, ENABLE); /* diff --git a/flight/pios/stm32f0x/pios_tim.c b/flight/pios/stm32f0x/pios_tim.c index a519240ee..7a9b649c8 100644 --- a/flight/pios/stm32f0x/pios_tim.c +++ b/flight/pios/stm32f0x/pios_tim.c @@ -61,36 +61,6 @@ int32_t PIOS_TIM_InitClock(const struct pios_tim_clock_cfg *cfg) { PIOS_DEBUG_Assert(cfg); - /* Enable appropriate clock to timer module */ - switch ((uint32_t)cfg->timer) { - case (uint32_t)TIM1: - RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); - break; - case (uint32_t)TIM2: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); - break; - case (uint32_t)TIM3: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); - break; - case (uint32_t)TIM4: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); - break; -#ifdef STM32F10X_HD - case (uint32_t)TIM5: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE); - break; - case (uint32_t)TIM6: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE); - break; - case (uint32_t)TIM7: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE); - break; - case (uint32_t)TIM8: - RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE); - break; -#endif - } - /* Configure the dividers for this timer */ TIM_TimeBaseInit(cfg->timer, cfg->time_base_init); @@ -127,21 +97,6 @@ int32_t PIOS_TIM_InitChannels(uint32_t *tim_id, const struct pios_tim_channel *c for (uint8_t i = 0; i < num_channels; i++) { const struct pios_tim_channel *chan = &(channels[i]); - /* Enable the peripheral clock for the GPIO */ - switch ((uint32_t)chan->pin.gpio) { - case (uint32_t)GPIOA: - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - break; - case (uint32_t)GPIOB: - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); - break; - case (uint32_t)GPIOC: - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); - break; - default: - PIOS_Assert(0); - break; - } GPIO_Init(chan->pin.gpio, &chan->pin.init); if (chan->remap) { diff --git a/flight/pios/stm32f0x/pios_usart.c b/flight/pios/stm32f0x/pios_usart.c index 3547c29fc..6154341c3 100644 --- a/flight/pios/stm32f0x/pios_usart.c +++ b/flight/pios/stm32f0x/pios_usart.c @@ -179,18 +179,15 @@ int32_t PIOS_USART_Init(uint32_t *usart_id, const struct pios_usart_cfg *cfg) /* Enable USART clock */ switch ((uint32_t)cfg->regs) { case (uint32_t)USART1: - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); local_id = &PIOS_USART_1_id; irq_channel = USART1_IRQn; break; case (uint32_t)USART2: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); local_id = &PIOS_USART_2_id; irq_channel = USART2_IRQn; break; #if defined(STM32F072) case (uint32_t)USART3: - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); local_id = &PIOS_USART_3_id; irq_channel = USART3_4_IRQn; break; diff --git a/flight/pios/stm32f0x/pios_wdg.c b/flight/pios/stm32f0x/pios_wdg.c index f87af420d..ef51e28e8 100644 --- a/flight/pios/stm32f0x/pios_wdg.c +++ b/flight/pios/stm32f0x/pios_wdg.c @@ -70,7 +70,6 @@ uint16_t PIOS_WDG_Init() delay = 0x0fff; } #if defined(PIOS_INCLUDE_WDG) - RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE); DBGMCU_APB1PeriphConfig(DBGMCU_IWDG_STOP, ENABLE); // make the watchdog stop counting in debug mode IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); IWDG_SetPrescaler(IWDG_Prescaler_32); From d991607aa5f9539d7dd150316b65fa4797b0da5c Mon Sep 17 00:00:00 2001 From: Vladimir Zidar Date: Mon, 5 Jun 2017 01:09:52 +0200 Subject: [PATCH 2/2] LP-527 Move PIOS_DELAY_Init() after the peripheral clocks have been started. F0 uses TIM2 for delays. --- flight/pios/stm32f0x/pios_sys.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flight/pios/stm32f0x/pios_sys.c b/flight/pios/stm32f0x/pios_sys.c index 275b6cc02..c4a774e06 100644 --- a/flight/pios/stm32f0x/pios_sys.c +++ b/flight/pios/stm32f0x/pios_sys.c @@ -61,9 +61,6 @@ void PIOS_SYS_Init(void) /* do this early to ensure that we take exceptions in the right place */ NVIC_Configuration(); - /* Init the delay system */ - PIOS_DELAY_Init(); - /* * Turn on all the peripheral clocks. * Micromanaging clocks makes no sense given the power situation in the system, so @@ -98,6 +95,9 @@ void PIOS_SYS_Init(void) RCC_APB2Periph_TIM1 | 0, ENABLE); + /* Init the delay system */ + PIOS_DELAY_Init(); + /* * Configure all pins as input / pullup to avoid issues with * uncommitted pins, excepting special-function pins that we need to