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Code Issues Releases Activity

INS: Almost got Bootloader compiling *sigh*

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This commit is contained in:
James Cotton 2011-08-06 20:40:06 -05:00
parent a0d77faf4b
commit 558bdddeaf
12 changed files with 1261 additions and 211 deletions
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47
flight/Bootloaders/INS/Makefile
View File

@ -1,8 +1,8 @@
#####
# Project: OpenPilot AHRS_BOOTLOADER
# Project: OpenPilot INS_BOOTLOADER
#
#
# Makefile for OpenPilot AHRS_BOOTLOADER project
# Makefile for OpenPilot INS project
#
# The OpenPilot Team, http://www.openpilot.org, Copyright (C) 2009.
#
@ -49,8 +49,8 @@ endif
FLASH_TOOL = OPENOCD
# Paths
AHRS_BL = ./
AHRS_BLINC = $(AHRS_BL)/inc
INS_BL = ./
INS_BLINC = $(INS_BL)/inc
PIOS = ../../PiOS
PIOSINC = $(PIOS)/inc
FLIGHTLIB = ../Libraries
@ -76,7 +76,7 @@ SRC += bl_fsm.c
#SRC += insgps.c
#SRC += $(FLIGHTLIB)/CoordinateConversions.c
## PIOS Hardware (STM32F10x)
## PIOS Hardware (STM32F2xx)
SRC += $(PIOSSTM32FXX)/pios_sys.c
SRC += $(PIOSSTM32FXX)/pios_led.c
SRC += $(PIOSSTM32FXX)/pios_delay.c
@ -86,6 +86,7 @@ SRC += $(PIOSSTM32FXX)/pios_irq.c
SRC += $(PIOSSTM32FXX)/pios_gpio.c
SRC += $(PIOSSTM32FXX)/pios_spi.c
SRC += $(PIOSSTM32FXX)/pios_iap.c
SRC += $(PIOSSTM32FXX)/pios_debug.c
## PIOS Hardware (Common)
#SRC += $(PIOSCOMMON)/pios_com.c
@ -97,24 +98,24 @@ SRC += $(PIOSCOMMON)/pios_bl_helper.c
## CMSIS for STM32
SRC += $(CMSISDIR)/core_cm3.c
SRC += $(CMSISDIR)/system_stm32f10x.c
SRC += $(CMSISDIR)/system_stm32f2xx.c
## Used parts of the STM-Library
SRC += $(STMSPDSRCDIR)/stm32f10x_adc.c
SRC += $(STMSPDSRCDIR)/stm32f10x_bkp.c
SRC += $(STMSPDSRCDIR)/stm32f10x_crc.c
SRC += $(STMSPDSRCDIR)/stm32f10x_dac.c
SRC += $(STMSPDSRCDIR)/stm32f10x_dma.c
SRC += $(STMSPDSRCDIR)/stm32f10x_exti.c
SRC += $(STMSPDSRCDIR)/stm32f10x_flash.c
SRC += $(STMSPDSRCDIR)/stm32f10x_gpio.c
SRC += $(STMSPDSRCDIR)/stm32f10x_i2c.c
SRC += $(STMSPDSRCDIR)/stm32f10x_pwr.c
SRC += $(STMSPDSRCDIR)/stm32f10x_rcc.c
SRC += $(STMSPDSRCDIR)/stm32f10x_rtc.c
SRC += $(STMSPDSRCDIR)/stm32f10x_spi.c
SRC += $(STMSPDSRCDIR)/stm32f10x_tim.c
SRC += $(STMSPDSRCDIR)/stm32f10x_usart.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_adc.c
# SRC += $(STMSPDSRCDIR)/stm32f2xx_bkp.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_crc.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_dac.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_dma.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_exti.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_flash.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_gpio.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_i2c.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_pwr.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_rcc.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_rtc.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_spi.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_tim.c
SRC += $(STMSPDSRCDIR)/stm32f2xx_usart.c
SRC += $(STMSPDSRCDIR)/misc.c
# List C source files here which must be compiled in ARM-Mode (no -mthumb).
@ -153,7 +154,7 @@ EXTRAINCDIRS += $(PIOSCOMMON)
EXTRAINCDIRS += $(PIOSBOARDS)
EXTRAINCDIRS += $(STMSPDINCDIR)
EXTRAINCDIRS += $(CMSISDIR)
EXTRAINCDIRS += $(AHRS_BLINC)
EXTRAINCDIRS += $(INS_BLINC)
# List any extra directories to look for library files here.
# Also add directories where the linker should search for
@ -236,6 +237,8 @@ ifeq ($(DEBUG),YES)
CFLAGS =
endif
CFLAGS += -DHSE_VALUE=$(OSCILLATOR_FREQ)
CFLAGS += -g$(DEBUGF)
CFLAGS += -O$(OPT)
ifeq ($(DEBUG),NO)

2
flight/Bootloaders/INS/inc/pios_config.h
View File

@ -28,7 +28,7 @@
#define PIOS_CONFIG_H
#define STM32F2XX
#define HSE_VALUE 8000000
#define MEM_SIZE 1024000000
/* Enable/Disable PiOS Modules */
#define PIOS_INCLUDE_DELAY

0
flight/PiOS/Boards/STM3210E_INS.h → flight/PiOS/Boards/STM32F2xx_INS.h
View File

4
flight/PiOS/Boards/pios_board.h
View File

@ -9,8 +9,8 @@
#include "STM32103CB_PIPXTREME_Rev1.h"
#elif USE_STM32103CB_CC_Rev1
#include "STM32103CB_CC_Rev1.h"
#elif USE_STM3210E_INS
#include "STM3210E_INS.h"
#elif USE_STM32F2xx_INS
#include "STM32F2xx_INS.h"
#else
#error Board definition has not been provided.
#endif

400
flight/PiOS/STM32F2xx/link_STM32F2xx_INS_BL_sections.ld
View File

@ -1,57 +1,367 @@
/* XXX should be based on the SRAM definition */
_estack = 0x2001fff0;
/* This is the size of the stack for early init and for all FreeRTOS IRQs */
_irq_stack_size = 0x400;
/* Check valid alignment for VTOR */
ASSERT(ORIGIN(BL_FLASH) == ALIGN(ORIGIN(BL_FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
/*
this sends all unreferenced IRQHandlers to reset
*/
PROVIDE ( Undefined_Handler = 0 ) ;
PROVIDE ( SWI_Handler = 0 ) ;
PROVIDE ( IRQ_Handler = 0 ) ;
PROVIDE ( Prefetch_Handler = 0 ) ;
PROVIDE ( Abort_Handler = 0 ) ;
PROVIDE ( FIQ_Handler = 0 ) ;
PROVIDE ( NMI_Handler = 0 ) ;
PROVIDE ( HardFault_Handler = 0 ) ;
PROVIDE ( MemManage_Handler = 0 ) ;
PROVIDE ( BusFault_Handler = 0 ) ;
PROVIDE ( UsageFault_Handler = 0 ) ;
PROVIDE ( vPortSVCHandler = 0 ) ;
PROVIDE ( DebugMon_Handler = 0 ) ;
PROVIDE ( xPortPendSVHandler = 0 ) ;
PROVIDE ( xPortSysTickHandler = 0 ) ;
PROVIDE ( WWDG_IRQHandler = 0 ) ;
PROVIDE ( PVD_IRQHandler = 0 ) ;
PROVIDE ( TAMPER_IRQHandler = 0 ) ;
PROVIDE ( RTC_IRQHandler = 0 ) ;
PROVIDE ( FLASH_IRQHandler = 0 ) ;
PROVIDE ( RCC_IRQHandler = 0 ) ;
PROVIDE ( EXTI0_IRQHandler = 0 ) ;
PROVIDE ( EXTI1_IRQHandler = 0 ) ;
PROVIDE ( EXTI2_IRQHandler = 0 ) ;
PROVIDE ( EXTI3_IRQHandler = 0 ) ;
PROVIDE ( EXTI4_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
PROVIDE ( ADC_IRQHandler = 0 ) ;
PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
PROVIDE ( TIM2_IRQHandler = 0 ) ;
PROVIDE ( TIM3_IRQHandler = 0 ) ;
PROVIDE ( TIM4_IRQHandler = 0 ) ;
PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
PROVIDE ( SPI1_IRQHandler = 0 ) ;
PROVIDE ( SPI2_IRQHandler = 0 ) ;
PROVIDE ( USART1_IRQHandler = 0 ) ;
PROVIDE ( USART2_IRQHandler = 0 ) ;
PROVIDE ( USART3_IRQHandler = 0 ) ;
PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
PROVIDE ( ADC3_IRQHandler = 0 ) ;
PROVIDE ( FSMC_IRQHandler = 0 ) ;
PROVIDE ( SDIO_IRQHandler = 0 ) ;
PROVIDE ( TIM5_IRQHandler = 0 ) ;
PROVIDE ( SPI3_IRQHandler = 0 ) ;
PROVIDE ( UART4_IRQHandler = 0 ) ;
PROVIDE ( UART5_IRQHandler = 0 ) ;
PROVIDE ( TIM6_IRQHandler = 0 ) ;
PROVIDE ( TIM7_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/*this allows to compile the ST lib in "non-debug" mode*/
/* Peripheral and SRAM base address in the alias region */
PERIPH_BB_BASE = 0x42000000;
SRAM_BB_BASE = 0x22000000;
/* Peripheral and SRAM base address in the bit-band region */
SRAM_BASE = 0x20000000;
PERIPH_BASE = 0x40000000;
/* Flash registers base address */
PROVIDE ( FLASH_BASE = 0x40022000);
/* Flash Option Bytes base address */
PROVIDE ( OB_BASE = 0x1FFFF800);
/* Peripheral memory map */
APB1PERIPH_BASE = PERIPH_BASE ;
APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
/* System Control Space memory map */
SCS_BASE = 0xE000E000;
PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
/* Sections Definitions */
/* Section Definitions */
SECTIONS
{
.text :
{
PROVIDE (pios_isr_vector_table_base = .);
KEEP(*(.isr_vector .isr_vector.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
} > BL_FLASH
/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
.isr_vector :
{
PROVIDE (pios_isr_vector_table_base = .);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > BL_FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
.flashtext :
{
. = ALIGN(4);
*(.flashtext) /* Startup code */
. = ALIGN(4);
} > BL_FLASH
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
. = ALIGN(4);
_etext = .;
_sidata = .;
/* init sections */
.initcalluavobj.init :
{
. = ALIGN(4);
__uavobj_initcall_start = .;
KEEP(*(.initcalluavobj.init))
. = ALIGN(4);
__uavobj_initcall_end = .;
} > BL_FLASH
.data : AT (_etext)
{
_sdata = .;
*(.data .data.*)
. = ALIGN(4);
_edata = . ;
} > SRAM
/* the program code is stored in the .text section, which goes to Flash */
.text :
{
. = ALIGN(4);
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
_sbss = . ;
*(.bss .bss.*)
*(COMMON)
_ebss = . ;
} > SRAM
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
. = ALIGN(4);
_end = . ;
. = ALIGN(4);
_etext = .;
/* This is used by the startup in order to initialize the .data secion */
_sidata = _etext;
} > BL_FLASH
.boardinfo :
{
. = ALIGN(4);
KEEP(*(.boardinfo))
} > BD_INFO
/*
* This stack is used both as the initial sp during early init as well as ultimately
* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
* is used for _all_ interrupt handlers. The end of this stack should be placed
* against the lowest address in RAM so that a stack overrun results in a hard fault
* at the first access beyond the end of the stack.
*/
.irq_stack :
{
. = ALIGN(4);
_irq_stack_end = . ;
. = . + _irq_stack_size ;
. = ALIGN(4);
_irq_stack_top = . - 4 ;
_init_stack_top = _irq_stack_top;
. = ALIGN(4);
} >RAM
/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data : AT ( _sidata )
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
/* This is the uninitialized data section */
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
} >RAM
PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );
/* this is the FLASH Bank1 */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */
.b1text :
{
*(.b1text) /* remaining code */
*(.b1rodata) /* read-only data (constants) */
*(.b1rodata*)
} >FLASHB1
/* this is the EXTMEM */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */
/* EXTMEM Bank0 */
.eb0text :
{
*(.eb0text) /* remaining code */
*(.eb0rodata) /* read-only data (constants) */
*(.eb0rodata*)
} >EXTMEMB0
/* EXTMEM Bank1 */
.eb1text :
{
*(.eb1text) /* remaining code */
*(.eb1rodata) /* read-only data (constants) */
*(.eb1rodata*)
} >EXTMEMB1
/* EXTMEM Bank2 */
.eb2text :
{
*(.eb2text) /* remaining code */
*(.eb2rodata) /* read-only data (constants) */
*(.eb2rodata*)
} >EXTMEMB2
/* EXTMEM Bank0 */
.eb3text :
{
*(.eb3text) /* remaining code */
*(.eb3rodata) /* read-only data (constants) */
*(.eb3rodata*)
} >EXTMEMB3
__exidx_start = .;
__exidx_end = .;
.boardinfo :
{
. = ALIGN(4);
KEEP(*(.boardinfo))
. = ALIGN(4);
} > BD_INFO
/* after that it's only debugging information. */
/* remove the debugging information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

15
flight/PiOS/STM32F2xx/link_STM32F2xx_INS_memory.ld
View File

@ -1,7 +1,12 @@
MEMORY
{
BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x008000 - 0x000080
BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080
FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 0x100000 - 0x008000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x020000
}
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x020000
BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x05000 - 0x00080
BD_INFO (r) : ORIGIN = 0x08005000 - 0x80, LENGTH = 0x00080
FLASH (rx) : ORIGIN = 0x08005000, LENGTH = 0x100000 - 0x05000
FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
}

506
flight/PiOS/STM32F2xx/link_STM32F2xx_INS_sections.ld
View File

@ -1,156 +1,400 @@
/* This is the size of the stack for all FreeRTOS IRQs */
/* This is the size of the stack for early init and for all FreeRTOS IRQs */
_irq_stack_size = 0x400;
/* This is the size of the stack for early init: life span is until scheduler starts */
_init_stack_size = 0x400;
/* Check valid alignment for VTOR */
ASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
/*
this sends all unreferenced IRQHandlers to reset
*/
PROVIDE ( Undefined_Handler = 0 ) ;
PROVIDE ( SWI_Handler = 0 ) ;
PROVIDE ( IRQ_Handler = 0 ) ;
PROVIDE ( Prefetch_Handler = 0 ) ;
PROVIDE ( Abort_Handler = 0 ) ;
PROVIDE ( FIQ_Handler = 0 ) ;
PROVIDE ( NMI_Handler = 0 ) ;
PROVIDE ( HardFault_Handler = 0 ) ;
PROVIDE ( MemManage_Handler = 0 ) ;
PROVIDE ( BusFault_Handler = 0 ) ;
PROVIDE ( UsageFault_Handler = 0 ) ;
PROVIDE ( vPortSVCHandler = 0 ) ;
PROVIDE ( DebugMon_Handler = 0 ) ;
PROVIDE ( xPortPendSVHandler = 0 ) ;
PROVIDE ( xPortSysTickHandler = 0 ) ;
PROVIDE ( WWDG_IRQHandler = 0 ) ;
PROVIDE ( PVD_IRQHandler = 0 ) ;
PROVIDE ( TAMPER_IRQHandler = 0 ) ;
PROVIDE ( RTC_IRQHandler = 0 ) ;
PROVIDE ( FLASH_IRQHandler = 0 ) ;
PROVIDE ( RCC_IRQHandler = 0 ) ;
PROVIDE ( EXTI0_IRQHandler = 0 ) ;
PROVIDE ( EXTI1_IRQHandler = 0 ) ;
PROVIDE ( EXTI2_IRQHandler = 0 ) ;
PROVIDE ( EXTI3_IRQHandler = 0 ) ;
PROVIDE ( EXTI4_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
PROVIDE ( ADC_IRQHandler = 0 ) ;
PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
PROVIDE ( TIM2_IRQHandler = 0 ) ;
PROVIDE ( TIM3_IRQHandler = 0 ) ;
PROVIDE ( TIM4_IRQHandler = 0 ) ;
PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
PROVIDE ( SPI1_IRQHandler = 0 ) ;
PROVIDE ( SPI2_IRQHandler = 0 ) ;
PROVIDE ( USART1_IRQHandler = 0 ) ;
PROVIDE ( USART2_IRQHandler = 0 ) ;
PROVIDE ( USART3_IRQHandler = 0 ) ;
PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
PROVIDE ( ADC3_IRQHandler = 0 ) ;
PROVIDE ( FSMC_IRQHandler = 0 ) ;
PROVIDE ( SDIO_IRQHandler = 0 ) ;
PROVIDE ( TIM5_IRQHandler = 0 ) ;
PROVIDE ( SPI3_IRQHandler = 0 ) ;
PROVIDE ( UART4_IRQHandler = 0 ) ;
PROVIDE ( UART5_IRQHandler = 0 ) ;
PROVIDE ( TIM6_IRQHandler = 0 ) ;
PROVIDE ( TIM7_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/*this allows to compile the ST lib in "non-debug" mode*/
/* Peripheral and SRAM base address in the alias region */
PERIPH_BB_BASE = 0x42000000;
SRAM_BB_BASE = 0x22000000;
/* Peripheral and SRAM base address in the bit-band region */
SRAM_BASE = 0x20000000;
PERIPH_BASE = 0x40000000;
/* Flash registers base address */
PROVIDE ( FLASH_BASE = 0x40022000);
/* Flash Option Bytes base address */
PROVIDE ( OB_BASE = 0x1FFFF800);
/* Peripheral memory map */
APB1PERIPH_BASE = PERIPH_BASE ;
APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
/* System Control Space memory map */
SCS_BASE = 0xE000E000;
PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
/* Section Definitions */
/* Sections Definitions */
SECTIONS
{
.text :
{
PROVIDE (pios_isr_vector_table_base = .);
KEEP(*(.isr_vector .isr_vector.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
} > FLASH
/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
.isr_vector :
{
PROVIDE (pios_isr_vector_table_base = .);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* init sections */
.initcalluavobj.init :
{
. = ALIGN(4);
__uavobj_initcall_start = .;
KEEP(*(.initcalluavobj.init))
. = ALIGN(4);
__uavobj_initcall_end = .;
} >FLASH
/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
.flashtext :
{
. = ALIGN(4);
*(.flashtext) /* Startup code */
. = ALIGN(4);
} >FLASH
/* module sections */
.initcallmodule.init :
{
. = ALIGN(4);
__module_initcall_start = .;
KEEP(*(.initcallmodule.init))
. = ALIGN(4);
__module_initcall_end = .;
} >FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
/* init sections */
.initcalluavobj.init :
{
. = ALIGN(4);
__uavobj_initcall_start = .;
KEEP(*(.initcalluavobj.init))
. = ALIGN(4);
__uavobj_initcall_end = .;
} >FLASH
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
/* module sections */
.initcallmodule.init :
{
. = ALIGN(4);
__module_initcall_start = .;
KEEP(*(.initcallmodule.init))
. = ALIGN(4);
__module_initcall_end = .;
} >FLASH
. = ALIGN(4);
_etext = .;
_sidata = .;
/* the program code is stored in the .text section, which goes to Flash */
.text :
{
. = ALIGN(4);
/*
* This stack is used both as the initial sp during early init as well as ultimately
* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
* is used for _all_ interrupt handlers. The end of this stack should be placed
* against the lowest address in RAM so that a stack overrun results in a hard fault
* at the first access beyond the end of the stack.
*/
.irq_stack :
{
. = ALIGN(4);
_irq_stack_end = . ;
. = . + _irq_stack_size ;
. = ALIGN(4);
_irq_stack_top = . - 4 ;
. = ALIGN(4);
} > SRAM
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
.data : AT (_etext)
{
_sdata = .;
*(.data .data.*)
. = ALIGN(4);
_edata = . ;
} > SRAM
. = ALIGN(4);
_etext = .;
/* This is used by the startup in order to initialize the .data secion */
_sidata = _etext;
} >FLASH
/*
* This stack is used both as the initial sp during early init as well as ultimately
* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
* is used for _all_ interrupt handlers. The end of this stack should be placed
* against the lowest address in RAM so that a stack overrun results in a hard fault
* at the first access beyond the end of the stack.
*/
.irq_stack :
{
. = ALIGN(4);
_irq_stack_end = . ;
. = . + _irq_stack_size ;
. = ALIGN(4);
_irq_stack_top = . - 4 ;
. = ALIGN(4);
} >RAM
/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data : AT ( _sidata )
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
_sbss = . ;
*(.bss .bss.*)
*(COMMON)
_ebss = . ;
} > SRAM
/* This is the uninitialized data section */
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss section */
_sbss = .;
.heap (NOLOAD) :
{
. = ALIGN(4);
_heap = ABSOLUTE(.);
_sheap = . ;
*(.heap)
/* fill to the end of SRAM */
. = ORIGIN(SRAM) + LENGTH(SRAM) - _heap ;
. = ALIGN(4) ;
/* place the init stack at the end of SRAM */
_init_stack_top = . - 4 ;
_init_stack_end = . - _init_stack_size ;
/* extend the heap up to the base of the init stack */
_eheap = _init_stack_end ;
} > SRAM
*(.bss)
*(COMMON)
} >RAM
.free_ram (NOLOAD) :
{
_eram = . ;
} > SRAM
.heap (NOLOAD) :
{
. = ALIGN(4);
_sheap = . ;
_sheap_pre_rtos = . ;
*(.heap)
. = ALIGN(4);
_eheap = . ;
_eheap_pre_rtos = . ;
_init_stack_end = . ;
_sheap_post_rtos = . ;
. = . + _init_stack_size ;
. = ALIGN(4);
_eheap_post_rtos = . ;
_init_stack_top = . - 4 ;
} > RAM
/* keep the heap section at the end of the SRAM
* this will allow to claim the remaining bytes not used
* at run time! (done by the reset vector).
*/
_free_ram = . ;
.free_ram (NOLOAD) :
{
. = ORIGIN(RAM) + LENGTH(RAM) - _free_ram ;
/* This is used by the startup in order to initialize the .bss section */
_ebss = . ;
_eram = . ;
} > RAM
PROVIDE ( _end = _ebss ) ;
/* keep the heap section at the end of the SRAM
* this will allow to claim the remaining bytes not used
* at run time! (done by the reset vector).
*/
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );
/* this is the FLASH Bank1 */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */
.b1text :
{
*(.b1text) /* remaining code */
*(.b1rodata) /* read-only data (constants) */
*(.b1rodata*)
} >FLASHB1
/* this is the EXTMEM */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */
/* EXTMEM Bank0 */
.eb0text :
{
*(.eb0text) /* remaining code */
*(.eb0rodata) /* read-only data (constants) */
*(.eb0rodata*)
} >EXTMEMB0
/* EXTMEM Bank1 */
.eb1text :
{
*(.eb1text) /* remaining code */
*(.eb1rodata) /* read-only data (constants) */
*(.eb1rodata*)
} >EXTMEMB1
/* EXTMEM Bank2 */
.eb2text :
{
*(.eb2text) /* remaining code */
*(.eb2rodata) /* read-only data (constants) */
*(.eb2rodata*)
} >EXTMEMB2
/* EXTMEM Bank0 */
.eb3text :
{
*(.eb3text) /* remaining code */
*(.eb3rodata) /* read-only data (constants) */
*(.eb3rodata*)
} >EXTMEMB3
__exidx_start = .;
__exidx_end = .;
/* after that it's only debugging information. */
/* remove the debugging information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

4
flight/PiOS/STM32F2xx/pios_iap.c
View File

@ -83,7 +83,8 @@ void PIOS_IAP_Init( void )
*/
uint32_t PIOS_IAP_CheckRequest( void )
{
#if 0 uint32_t retval = FALSE;
#if 0
uint32_t retval = FALSE;
uint16_t reg1;
uint16_t reg2;
@ -98,6 +99,7 @@ uint32_t PIOS_IAP_CheckRequest( void )
}
return retval;
#endif
return 0;
}

3
flight/PiOS/STM32F2xx/pios_sys.c
View File

@ -257,7 +257,8 @@ int32_t PIOS_SYS_SerialNumberGet(char *str)
static void NVIC_Configuration(void)
{
/* Set the Vector Table base address as specified in .ld file */
NVIC_SetVectorTable(PIOS_NVIC_VECTTAB_FLASH, 0x0);
extern void *pios_isr_vector_table_base;
NVIC_SetVectorTable((uint32_t)&pios_isr_vector_table_base, 0x0);
/* 4 bits for Interrupt priorities so no sub priorities */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);

483
flight/Project/OpenPilotOSX/OpenPilotOSX.xcodeproj/project.pbxproj
View File

@ -85,6 +85,163 @@
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@ -3544,6 +3701,313 @@
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6560A36A13EE26B700105DA5 /* stm32f2xx_hash.c */,
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6560A36D13EE26B700105DA5 /* stm32f2xx_i2c.c */,
6560A36E13EE26B700105DA5 /* stm32f2xx_iwdg.c */,
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6560A37313EE26B700105DA5 /* stm32f2xx_sdio.c */,
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6560A37613EE26B700105DA5 /* stm32f2xx_tim.c */,
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6560A3AD13EE2E8B00105DA5 /* main.c */,
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6560A3A713EE2E8B00105DA5 /* ahrs_spi_program.h */,
6560A3A813EE2E8B00105DA5 /* ahrs_spi_program_master.h */,
6560A3A913EE2E8B00105DA5 /* ahrs_spi_program_slave.h */,
6560A3AA13EE2E8B00105DA5 /* bl_fsm.h */,
6560A3AB13EE2E8B00105DA5 /* ins_bl.h */,
6560A3AC13EE2E8B00105DA5 /* pios_config.h */,
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path = INS/inc;
sourceTree = "<group>";
};
65632DF41251650300469B77 /* Boards */ = {
isa = PBXGroup;
children = (
@ -7648,6 +8112,7 @@
65E8F03811EFF25C00BBF654 /* inc */,
65E8F05711EFF25C00BBF654 /* pios.h */,
65E8F05811EFF25C00BBF654 /* STM32F10x */,
6560A2FD13EE26B700105DA5 /* STM32F2xx */,
);
name = PiOS;
path = ../../PiOS;
@ -7728,6 +8193,23 @@
65E8F05811EFF25C00BBF654 /* STM32F10x */ = {
isa = PBXGroup;
children = (
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6560A39E13EE277E00105DA5 /* pios_sbus.c */,
6560A38E13EE270C00105DA5 /* link_STM3210E_INS_BL_sections.ld */,
6560A38F13EE270C00105DA5 /* link_STM3210E_INS_memory.ld */,
6560A39013EE270C00105DA5 /* link_STM3210E_INS_sections.ld */,
6560A39113EE270C00105DA5 /* link_STM3210E_OP_BL_sections.ld */,
6560A39213EE270C00105DA5 /* link_STM3210E_OP_memory.ld */,
6560A39313EE270C00105DA5 /* link_STM3210E_OP_sections.ld */,
6560A39413EE270C00105DA5 /* link_STM32103CB_AHRS_BL_sections.ld */,
6560A39513EE270C00105DA5 /* link_STM32103CB_AHRS_memory.ld */,
6560A39613EE270C00105DA5 /* link_STM32103CB_AHRS_sections.ld */,
6560A39713EE270C00105DA5 /* link_STM32103CB_CC_Rev1_BL_sections.ld */,
6560A39813EE270C00105DA5 /* link_STM32103CB_PIPXTREME_BL_sections.ld */,
6560A39913EE270C00105DA5 /* link_STM32103CB_PIPXTREME_memory.ld */,
6560A39A13EE270C00105DA5 /* link_STM32103CB_PIPXTREME_sections.ld */,
6560A39B13EE270C00105DA5 /* startup_stm32f10x_HD_OP.S */,
6560A39C13EE270C00105DA5 /* startup_stm32f10x_MD_CC.S */,
65E8F05911EFF25C00BBF654 /* Libraries */,
65E8F0D811EFF25C00BBF654 /* link_stm32f10x_HD.ld */,
65E8F0DB11EFF25C00BBF654 /* link_stm32f10x_MD.ld */,
@ -8304,6 +8786,7 @@
65FF4BB313791C3300146BE4 /* Bootloaders */ = {
isa = PBXGroup;
children = (
6560A39F13EE2E6E00105DA5 /* INS */,
65FF4BB413791C3300146BE4 /* AHRS */,
65FF4BC413791C3300146BE4 /* BootloaderUpdater */,
65FF4BCB13791C3300146BE4 /* CopterControl */,

4
flight/Project/gdb/ins
View File

@ -1,8 +1,8 @@
define connect
target remote localhost:3334
monitor cortex_m3 vector_catch all
file ./build/ins/INS.elf
# file ./build/bl_ins/BL_INS.elf
# file ./build/fw_ins/fw_ins.elf
file ./build/bl_ins/bl_ins.elf
end
#monitor reset halt

4
make/boards/ins/board-info.mk
View File

@ -5,7 +5,7 @@ HW_TYPE := 0x00
MCU := cortex-m3
CHIP := STM32F205RGT
BOARD := STM3210E_INS
BOARD := STM32F2xx_INS
MODEL := HD
MODEL_SUFFIX :=
@ -16,3 +16,5 @@ FW_BANK_BASE := 0x08002000 # Start of firmware flash
FW_BANK_SIZE := 0x0001E000 # Should include FW_DESC_SIZE
FW_DESC_SIZE := 0x00000064
OSCILLATOR_FREQ := 8000000