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AHRS: Switch to sampling at 2khz, plenty of CPU usage. However need to make EKF rate different for outdoor mode with this patch because otherwise will drop samples :-(

git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1592 ebee16cc-31ac-478f-84a7-5cbb03baadba
This commit is contained in:
peabody124 2010-09-12 02:54:47 +00:00 committed by peabody124
parent 5d1ebf76ea
commit 56131476ef
4 changed files with 7 additions and 5 deletions

View File

@ -62,15 +62,15 @@ void DMA1_Channel1_IRQHandler() __attribute__ ((alias ("AHRS_ADC_DMA_Handler")))
// For debugging the raw sensors
//#define DUMP_RAW
//#define DUMP_FRIENDLY
#define DUMP_FRIENDLY
/**
* @addtogroup AHRS_Definitions
* @{
*/
// Currently analog acquistion hard coded at 480 Hz
#define ADC_OVERSAMPLE 12
#define EKF_RATE ((float) 480 / ADC_OVERSAMPLE)
#define ADC_OVERSAMPLE 40
#define EKF_RATE ((float) 4*480 / ADC_OVERSAMPLE)
#define ADC_CONTINUOUS_CHANNELS PIOS_ADC_NUM_PINS
#define CORRECTION_COUNT 4

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@ -193,7 +193,7 @@ TIM8 | | | |
#define PIOS_ADC_NUM_ADC_CHANNELS 2
#define PIOS_ADC_USE_ADC2 1
#define PIOS_ADC_CLOCK_FUNCTION RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2, ENABLE)
#define PIOS_ADC_ADCCLK RCC_PCLK2_Div8
#define PIOS_ADC_ADCCLK RCC_PCLK2_Div2
/* RCC_PCLK2_Div2: ADC clock = PCLK2/2 */
/* RCC_PCLK2_Div4: ADC clock = PCLK2/4 */
/* RCC_PCLK2_Div6: ADC clock = PCLK2/6 */

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@ -157,7 +157,7 @@ void USART3_IRQHandler() __attribute__ ((alias ("PIOS_USART_aux_irq_handler")));
const struct pios_usart_cfg pios_usart_aux_cfg = {
.regs = USART3,
.init = {
.USART_BaudRate = 115200,
.USART_BaudRate = 230400,
.USART_WordLength = USART_WordLength_8b,
.USART_Parity = USART_Parity_No,
.USART_StopBits = USART_StopBits_1,

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@ -43,6 +43,8 @@ if(gaps) % get biggest contiguous chunk
data = data(idx);
end
data(end) = []; % delete in case partial update
q = cat(1,data.q);
accel = cat(1,data.accel);
gyro = cat(1,data.gyro);