mirror of
https://bitbucket.org/librepilot/librepilot.git
synced 2025-03-15 07:29:15 +01:00
Bootloader now jumps to functioning code for INS. Consistent with AHRS code.
This commit is contained in:
parent
e9ca5c15f9
commit
5619e33292
@ -152,7 +152,7 @@ CPPSRCARM =
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# Even though the DOS/Win* filesystem matches both .s and .S the same,
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# it will preserve the spelling of the filenames, and gcc itself does
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# care about how the name is spelled on its command-line.
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ASRC = $(PIOSSTM32F2XX)/startup_stm32f2xx_INS.S
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ASRC = $(PIOSSTM32F2XX)/startup_stm32f2xx.S
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# List Assembler source files here which must be assembled in ARM-Mode..
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ASRCARM =
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@ -1,367 +1,56 @@
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/* This is the size of the stack for early init and for all FreeRTOS IRQs */
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_irq_stack_size = 0x400;
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/* Check valid alignment for VTOR */
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ASSERT(ORIGIN(BL_FLASH) == ALIGN(ORIGIN(BL_FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
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/*
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this sends all unreferenced IRQHandlers to reset
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*/
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PROVIDE ( Undefined_Handler = 0 ) ;
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PROVIDE ( SWI_Handler = 0 ) ;
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PROVIDE ( IRQ_Handler = 0 ) ;
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PROVIDE ( Prefetch_Handler = 0 ) ;
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PROVIDE ( Abort_Handler = 0 ) ;
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PROVIDE ( FIQ_Handler = 0 ) ;
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PROVIDE ( NMI_Handler = 0 ) ;
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PROVIDE ( HardFault_Handler = 0 ) ;
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PROVIDE ( MemManage_Handler = 0 ) ;
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PROVIDE ( BusFault_Handler = 0 ) ;
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PROVIDE ( UsageFault_Handler = 0 ) ;
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PROVIDE ( vPortSVCHandler = 0 ) ;
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PROVIDE ( DebugMon_Handler = 0 ) ;
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PROVIDE ( xPortPendSVHandler = 0 ) ;
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PROVIDE ( xPortSysTickHandler = 0 ) ;
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PROVIDE ( WWDG_IRQHandler = 0 ) ;
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PROVIDE ( PVD_IRQHandler = 0 ) ;
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PROVIDE ( TAMPER_IRQHandler = 0 ) ;
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PROVIDE ( RTC_IRQHandler = 0 ) ;
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PROVIDE ( FLASH_IRQHandler = 0 ) ;
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PROVIDE ( RCC_IRQHandler = 0 ) ;
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PROVIDE ( EXTI0_IRQHandler = 0 ) ;
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PROVIDE ( EXTI1_IRQHandler = 0 ) ;
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PROVIDE ( EXTI2_IRQHandler = 0 ) ;
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PROVIDE ( EXTI3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
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PROVIDE ( ADC_IRQHandler = 0 ) ;
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PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
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PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
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PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
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PROVIDE ( TIM2_IRQHandler = 0 ) ;
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PROVIDE ( TIM3_IRQHandler = 0 ) ;
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PROVIDE ( TIM4_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
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PROVIDE ( SPI1_IRQHandler = 0 ) ;
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PROVIDE ( SPI2_IRQHandler = 0 ) ;
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PROVIDE ( USART1_IRQHandler = 0 ) ;
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PROVIDE ( USART2_IRQHandler = 0 ) ;
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PROVIDE ( USART3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
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PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
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PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
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PROVIDE ( ADC3_IRQHandler = 0 ) ;
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PROVIDE ( FSMC_IRQHandler = 0 ) ;
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PROVIDE ( SDIO_IRQHandler = 0 ) ;
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PROVIDE ( TIM5_IRQHandler = 0 ) ;
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PROVIDE ( SPI3_IRQHandler = 0 ) ;
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PROVIDE ( UART4_IRQHandler = 0 ) ;
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PROVIDE ( UART5_IRQHandler = 0 ) ;
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PROVIDE ( TIM6_IRQHandler = 0 ) ;
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PROVIDE ( TIM7_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/*this allows to compile the ST lib in "non-debug" mode*/
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/* Peripheral and SRAM base address in the alias region */
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PERIPH_BB_BASE = 0x42000000;
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SRAM_BB_BASE = 0x22000000;
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/* Peripheral and SRAM base address in the bit-band region */
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SRAM_BASE = 0x20000000;
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PERIPH_BASE = 0x40000000;
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/* Flash registers base address */
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PROVIDE ( FLASH_BASE = 0x40022000);
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/* Flash Option Bytes base address */
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PROVIDE ( OB_BASE = 0x1FFFF800);
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/* Peripheral memory map */
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APB1PERIPH_BASE = PERIPH_BASE ;
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APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
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AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
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PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
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PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
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PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
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PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
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PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
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PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
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PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
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PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
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PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
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PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
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PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
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PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
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PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
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PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
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PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
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PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
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PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
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PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
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PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
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PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
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PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
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/* System Control Space memory map */
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SCS_BASE = 0xE000E000;
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PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
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PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
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PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
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/* Sections Definitions */
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SECTIONS
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{
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/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
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.isr_vector :
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{
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PROVIDE (pios_isr_vector_table_base = .);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
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.flashtext :
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{
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. = ALIGN(4);
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*(.flashtext) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* init sections */
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.initcalluavobj.init :
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{
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. = ALIGN(4);
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__uavobj_initcall_start = .;
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KEEP(*(.initcalluavobj.init))
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. = ALIGN(4);
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__uavobj_initcall_end = .;
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} > BL_FLASH
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/* the program code is stored in the .text section, which goes to Flash */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* remaining code */
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*(.text.*) /* remaining code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(4);
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_etext = .;
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/* This is used by the startup in order to initialize the .data secion */
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_sidata = _etext;
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} > BL_FLASH
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/*
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* This stack is used both as the initial sp during early init as well as ultimately
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* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
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* is used for _all_ interrupt handlers. The end of this stack should be placed
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* against the lowest address in RAM so that a stack overrun results in a hard fault
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* at the first access beyond the end of the stack.
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*/
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.irq_stack :
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{
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. = ALIGN(4);
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_irq_stack_end = . ;
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. = . + _irq_stack_size ;
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. = ALIGN(4);
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_irq_stack_top = . - 4 ;
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_init_stack_top = _irq_stack_top;
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. = ALIGN(4);
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} >RAM
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/* This is the initialized data section
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The program executes knowing that the data is in the RAM
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but the loader puts the initial values in the FLASH (inidata).
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It is one task of the startup to copy the initial values from FLASH to RAM. */
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.data : AT ( _sidata )
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_sdata = . ;
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*(.data)
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*(.data.*)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM
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/* This is the uninitialized data section */
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.bss :
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .;
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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} >RAM
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PROVIDE ( end = _ebss );
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PROVIDE ( _end = _ebss );
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/* this is the FLASH Bank1 */
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/* the C or assembly source must explicitly place the code or data there
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using the "section" attribute */
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.b1text :
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{
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*(.b1text) /* remaining code */
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*(.b1rodata) /* read-only data (constants) */
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*(.b1rodata*)
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} >FLASHB1
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/* this is the EXTMEM */
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/* the C or assembly source must explicitly place the code or data there
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using the "section" attribute */
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/* EXTMEM Bank0 */
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.eb0text :
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{
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*(.eb0text) /* remaining code */
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*(.eb0rodata) /* read-only data (constants) */
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*(.eb0rodata*)
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} >EXTMEMB0
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/* EXTMEM Bank1 */
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.eb1text :
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{
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*(.eb1text) /* remaining code */
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*(.eb1rodata) /* read-only data (constants) */
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*(.eb1rodata*)
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} >EXTMEMB1
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/* EXTMEM Bank2 */
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.eb2text :
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{
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*(.eb2text) /* remaining code */
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*(.eb2rodata) /* read-only data (constants) */
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*(.eb2rodata*)
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} >EXTMEMB2
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/* EXTMEM Bank0 */
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.eb3text :
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{
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*(.eb3text) /* remaining code */
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*(.eb3rodata) /* read-only data (constants) */
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*(.eb3rodata*)
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} >EXTMEMB3
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__exidx_start = .;
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__exidx_end = .;
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.boardinfo :
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{
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. = ALIGN(4);
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KEEP(*(.boardinfo))
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. = ALIGN(4);
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} > BD_INFO
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/* after that it's only debugging information. */
|
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|
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/* remove the debugging information from the standard libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
|
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}
|
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|
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/* Stabs debugging sections. */
|
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.stab 0 : { *(.stab) }
|
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.stabstr 0 : { *(.stabstr) }
|
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.stab.excl 0 : { *(.stab.excl) }
|
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.stab.exclstr 0 : { *(.stab.exclstr) }
|
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.stab.index 0 : { *(.stab.index) }
|
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.stab.indexstr 0 : { *(.stab.indexstr) }
|
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.comment 0 : { *(.comment) }
|
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/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
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.debug 0 : { *(.debug) }
|
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.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
_estack = 0x20004FF0;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
PROVIDE (pios_isr_vector_table_base = .);
|
||||
KEEP(*(.isr_vector .isr_vector.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
} > BL_FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > BL_FLASH
|
||||
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > BL_FLASH
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
_sidata = .;
|
||||
|
||||
.data : AT (_etext)
|
||||
{
|
||||
_sdata = .;
|
||||
*(.data .data.*)
|
||||
. = ALIGN(4);
|
||||
_edata = . ;
|
||||
} > SRAM
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_sbss = . ;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
} > SRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
|
||||
.boardinfo :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.boardinfo))
|
||||
. = ALIGN(4);
|
||||
} > BD_INFO
|
||||
}
|
||||
|
@ -1,12 +1,7 @@
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x020000
|
||||
BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x05000 - 0x00080
|
||||
BD_INFO (r) : ORIGIN = 0x08005000 - 0x80, LENGTH = 0x00080
|
||||
FLASH (rx) : ORIGIN = 0x08005000, LENGTH = 0x100000 - 0x05000
|
||||
FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
}
|
||||
BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x08000 - 0x00080
|
||||
BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x00080
|
||||
FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 0x100000 - 0x08000
|
||||
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x05000
|
||||
}
|
||||
|
@ -35,8 +35,8 @@ defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
.equ BootRAM, 0xF108F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
@ -1,99 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f100_MD_BL.s
|
||||
* @author MCD Application Team / Angus Peart / Michael Smith
|
||||
* @brief STM32F2xx Devices startup - bootloader, no OS stack.
|
||||
*******************************************************************************
|
||||
* @copy
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
#define INITIAL_STACK_TOP _estack
|
||||
#include "vectors_stm32f2xx.S"
|
@ -207,7 +207,6 @@
|
||||
6560A38913EE26B700105DA5 /* pios_usart.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = pios_usart.c; sourceTree = "<group>"; };
|
||||
6560A38A13EE26B700105DA5 /* pios_wdg.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = pios_wdg.c; sourceTree = "<group>"; };
|
||||
6560A38B13EE26B700105DA5 /* startup_stm32f2xx.S */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.asm; path = startup_stm32f2xx.S; sourceTree = "<group>"; };
|
||||
6560A38C13EE26B700105DA5 /* startup_stm32f2xx_BL.S */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.asm; path = startup_stm32f2xx_BL.S; sourceTree = "<group>"; };
|
||||
6560A38D13EE26B700105DA5 /* vectors_stm32f2xx.S */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.asm; path = vectors_stm32f2xx.S; sourceTree = "<group>"; };
|
||||
6560A38E13EE270C00105DA5 /* link_STM3210E_INS_BL_sections.ld */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = link_STM3210E_INS_BL_sections.ld; sourceTree = "<group>"; };
|
||||
6560A38F13EE270C00105DA5 /* link_STM3210E_INS_memory.ld */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = link_STM3210E_INS_memory.ld; sourceTree = "<group>"; };
|
||||
@ -2864,7 +2863,6 @@
|
||||
65D1FBD913F51AB7006374A6 /* pios_imu3000.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = pios_imu3000.c; sourceTree = "<group>"; };
|
||||
65D1FBDA13F51AE1006374A6 /* pios_imu3000.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = pios_imu3000.h; sourceTree = "<group>"; };
|
||||
65D1FBE713F53477006374A6 /* pios_bl_helper.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = pios_bl_helper.h; sourceTree = "<group>"; };
|
||||
65D1FC9C13F541D4006374A6 /* startup_stm32f2xx_INS.S */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.asm; path = startup_stm32f2xx_INS.S; sourceTree = "<group>"; };
|
||||
65D2CA841248F9A400B1E7D6 /* mixersettings.xml */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.xml; path = mixersettings.xml; sourceTree = "<group>"; };
|
||||
65D2CA851248F9A400B1E7D6 /* mixerstatus.xml */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.xml; path = mixerstatus.xml; sourceTree = "<group>"; };
|
||||
65DEA78513F0FE6000095B06 /* stm32f2xx_conf.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = stm32f2xx_conf.h; sourceTree = "<group>"; };
|
||||
@ -3749,8 +3747,6 @@
|
||||
6560A38913EE26B700105DA5 /* pios_usart.c */,
|
||||
6560A38A13EE26B700105DA5 /* pios_wdg.c */,
|
||||
6560A38B13EE26B700105DA5 /* startup_stm32f2xx.S */,
|
||||
6560A38C13EE26B700105DA5 /* startup_stm32f2xx_BL.S */,
|
||||
65D1FC9C13F541D4006374A6 /* startup_stm32f2xx_INS.S */,
|
||||
6560A38D13EE26B700105DA5 /* vectors_stm32f2xx.S */,
|
||||
);
|
||||
path = STM32F2xx;
|
||||
@ -8265,8 +8261,6 @@
|
||||
6560A39813EE270C00105DA5 /* link_STM32103CB_PIPXTREME_BL_sections.ld */,
|
||||
6560A39913EE270C00105DA5 /* link_STM32103CB_PIPXTREME_memory.ld */,
|
||||
6560A39A13EE270C00105DA5 /* link_STM32103CB_PIPXTREME_sections.ld */,
|
||||
6560A39B13EE270C00105DA5 /* startup_stm32f10x_HD_OP.S */,
|
||||
6560A39C13EE270C00105DA5 /* startup_stm32f10x_MD_CC.S */,
|
||||
65E8F05911EFF25C00BBF654 /* Libraries */,
|
||||
65E8F0D811EFF25C00BBF654 /* link_stm32f10x_HD.ld */,
|
||||
65E8F0DB11EFF25C00BBF654 /* link_stm32f10x_MD.ld */,
|
||||
@ -8293,7 +8287,9 @@
|
||||
651CF9E8120B5D8300EEFD70 /* pios_usb_hid_pwr.c */,
|
||||
65003B31121249CA00C183DD /* pios_wdg.c */,
|
||||
65E8F0EE11EFF25C00BBF654 /* startup_stm32f10x_HD.S */,
|
||||
6560A39B13EE270C00105DA5 /* startup_stm32f10x_HD_OP.S */,
|
||||
65E8F0F111EFF25C00BBF654 /* startup_stm32f10x_MD.S */,
|
||||
6560A39C13EE270C00105DA5 /* startup_stm32f10x_MD_CC.S */,
|
||||
);
|
||||
name = STM32F10x;
|
||||
path = ../../PiOS/STM32F10x;
|
||||
|
Loading…
x
Reference in New Issue
Block a user