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OP-1275 add Stack_Change support
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Alessio Morale
parent
5a60c254ed
commit
5ab9806279
@ -1,287 +0,0 @@
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/**
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******************************************************************************
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* @file startup_stm32f0xx.s
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* @author MCD Application Team
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* @version V1.3.1
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* @date 17-January-2014
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* @brief STM32F031 Devices vector table for RIDE7 toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Configure the system clock
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M0 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m0
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.equ BootRAM, 0xF108F85F
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M0. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word 0
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler
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.word PVD_IRQHandler
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.word RTC_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_IRQHandler
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.word EXTI0_1_IRQHandler
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.word EXTI2_3_IRQHandler
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.word EXTI4_15_IRQHandler
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.word 0
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_3_IRQHandler
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.word DMA1_Channel4_5_IRQHandler
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.word ADC1_IRQHandler
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.word TIM1_BRK_UP_TRG_COM_IRQHandler
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.word TIM1_CC_IRQHandler
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.word TIM2_IRQHandler
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.word TIM3_IRQHandler
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.word 0
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.word 0
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.word TIM14_IRQHandler
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.word 0
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.word TIM16_IRQHandler
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.word TIM17_IRQHandler
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.word I2C1_IRQHandler
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.word 0
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.word SPI1_IRQHandler
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.word 0
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.word USART1_IRQHandler
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.word 0
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.word 0
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.word 0
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.word 0
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.word BootRAM /* @0x108. This is for boot in RAM mode for
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STM32F0xx devices. */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak PVD_IRQHandler
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.thumb_set PVD_IRQHandler,Default_Handler
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.weak RTC_IRQHandler
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.thumb_set RTC_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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.weak EXTI0_1_IRQHandler
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.thumb_set EXTI0_1_IRQHandler,Default_Handler
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.weak EXTI2_3_IRQHandler
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.thumb_set EXTI2_3_IRQHandler,Default_Handler
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.weak EXTI4_15_IRQHandler
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.thumb_set EXTI4_15_IRQHandler,Default_Handler
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.weak DMA1_Channel1_IRQHandler
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.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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.weak DMA1_Channel2_3_IRQHandler
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.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
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.weak DMA1_Channel4_5_IRQHandler
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.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
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.weak ADC1_IRQHandler
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.thumb_set ADC1_IRQHandler,Default_Handler
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.weak TIM1_BRK_UP_TRG_COM_IRQHandler
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.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler,Default_Handler
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.weak TIM3_IRQHandler
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.thumb_set TIM3_IRQHandler,Default_Handler
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.weak TIM14_IRQHandler
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.thumb_set TIM14_IRQHandler,Default_Handler
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.weak TIM16_IRQHandler
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.thumb_set TIM16_IRQHandler,Default_Handler
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.weak TIM17_IRQHandler
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.thumb_set TIM17_IRQHandler,Default_Handler
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.weak I2C1_IRQHandler
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.thumb_set I2C1_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -113,6 +113,33 @@ LoopForever:
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that swaps stack (from end of heap to irq_stack).
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* Also reclaim the heap that was used as a stack.
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* @param None
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* @retval : None
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*/
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.section .text.Stack_Change
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.weak Stack_Change
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.type Stack_Change, %function
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Stack_Change:
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mov r4, lr
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/* Switches stack back momentarily to MSP */
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movs r0, #0
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msr control, r0
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Heap_Reclaim:
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/* add heap_post_rtos to the heap (if the capability/function exist) */
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/* Also claim the unused memory (between end of heap to end of memory */
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/* CAREFULL: the heap section must be the last section in RAM in order this to work */
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ldr r0, = _init_stack_size
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ldr r1, = _eheap_post_rtos
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ldr r2, = _eram
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subs r2, r2, r1
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adds r0, r0, r2
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bl xPortIncreaseHeapSize
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bx r4
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.size Stack_Change, .-Stack_Change
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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