rooty/LibrePilot
1
0
Fork 0
mirror of https://bitbucket.org/librepilot/librepilot.git synced 2025-01-17 02:52:12 +01:00
Code Issues Releases Activity

Made quite a few constants/#defines capitals (previously lower case)

Browse Source 
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2743 ebee16cc-31ac-478f-84a7-5cbb03baadba
This commit is contained in:
pip 2011-02-06 10:55:08 +00:00 committed by pip
parent 14641cd353
commit 6559615ef8
14 changed files with 956 additions and 1385 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
flight/PiOS/Boards/STM32103CB_PIPXTREME_Rev1.h
View File

@ -167,17 +167,18 @@ TIM8 | | | |
// *****************************************************************
// PIOS_USART
#define PIOS_USART_RX_BUFFER_SIZE 512
#define PIOS_USART_TX_BUFFER_SIZE 512
#define PIOS_USART_RX_BUFFER_SIZE 512
#define PIOS_USART_TX_BUFFER_SIZE 512
#define PIOS_COM_SERIAL 0
//#define PIOS_COM_DEBUG PIOS_COM_SERIAL // comment this out if you don't want debug text sent out on the serial port
#define PIOS_COM_SERIAL 0
#define PIOS_USART_BAUDRATE 57600
//#define PIOS_USART_BAUDRATE 115200
//#define PIOS_COM_DEBUG PIOS_COM_SERIAL // comment this out if you don't want debug text sent out on the serial port
#define PIOS_USART_BAUDRATE 57600
//#define PIOS_USART_BAUDRATE 115200
#if defined(PIOS_INCLUDE_USB_HID)
#define PIOS_COM_TELEM_USB 1
#define PIOS_COM_TELEM_USB 1
#endif
#if defined(PIOS_COM_DEBUG)

441
flight/PipXtreme/api_comms.c
View File

@ -1,441 +0,0 @@
/**
******************************************************************************
*
* @file api_comms.h
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
* @brief RF Module hardware layer
* @see The GNU Public License (GPL) Version 3
*
*****************************************************************************/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
// see http://newwiki.openpilot.org/display/Doc/UAVTalk .. for UAVTalk protocol description
//
// This module scans for OP UAVTalk packets in the comm-port or RF data streams.
// It will discard any corrupt/invalid packets and only pass valid ones.
#include <string.h>
#include "stm32f10x.h"
#include "gpio_in.h"
#include "api_comms.h"
#include "packet_handler.h"
#include "main.h"
#if defined(PIOS_COM_DEBUG)
#define API_DEBUG
#endif
// *****************************************************************************
typedef struct
{
uint8_t sync_byte;
uint8_t message_type;
uint16_t packet_size; // not including CRC byte
uint32_t object_id;
} __attribute__((__packed__)) t_uav_header1;
typedef struct
{
uint8_t sync_byte;
uint8_t message_type;
uint16_t packet_size; // not including CRC byte
uint32_t object_id;
uint16_t instance_id;
} __attribute__((__packed__)) t_uav_header2;
#define SYNC_VAL 0x3C
#define TYPE_MASK 0xFC
#define TYPE_VER 0x20
#define TYPE_OBJ (TYPE_VER | 0x00)
#define TYPE_OBJ_REQ (TYPE_VER | 0x01)
#define TYPE_OBJ_ACK (TYPE_VER | 0x02)
#define TYPE_ACK (TYPE_VER | 0x03)
#define MIN_HEADER_LENGTH sizeof(t_uav_header1)
#define MAX_HEADER_LENGTH sizeof(t_uav_header2)
#define MAX_PAYLOAD_LENGTH 256
#define CHECKSUM_LENGTH 1
#define MAX_PACKET_LENGTH (MAX_HEADER_LENGTH + MAX_PAYLOAD_LENGTH + CHECKSUM_LENGTH)
// CRC lookup table
static const uint8_t crc_table[256] = {
0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d,
0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d,
0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd,
0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd,
0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea,
0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a,
0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0d, 0x0a,
0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a,
0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4,
0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4,
0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44,
0x19, 0x1e, 0x17, 0x10, 0x05, 0x02, 0x0b, 0x0c, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34,
0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63,
0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x06, 0x01, 0x08, 0x0f, 0x1a, 0x1d, 0x14, 0x13,
0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83,
0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3
};
// *****************************************************************************
// local variables
int8_t api_previous_com_port = -1;
volatile uint16_t api_rx_timer = 0;
volatile uint16_t api_tx_timer = 0;
uint8_t api_rx_buffer[MAX_PACKET_LENGTH] __attribute__ ((aligned(4)));
uint16_t api_rx_buffer_wr;
uint8_t api_tx_buffer[MAX_PACKET_LENGTH] __attribute__ ((aligned(4)));
uint16_t api_tx_buffer_wr;
// *****************************************************************************
// 8-bit CRC updating
uint8_t api_updateCRC_byte(uint8_t crc, uint8_t b)
{
return crc_table[crc ^ b];
}
uint8_t api_updateCRC_buffer(uint8_t crc, const void *data, int32_t length)
{
// use registers for speed
register uint8_t crc8 = crc;
register const uint8_t *p = (uint8_t *)data;
for (register int32_t i = length; i > 0; i--)
crc8 = crc_table[crc8 ^ *p++];
return crc8;
}
// *****************************************************************************
// returned value < 0 if no valid packet detected.
// otherwise returned value is the total size of the valid UAVTalk packet found in the buffer.
//
// any corrupt/invalid UAVTalk packets/data are deleted from the buffer and we scan for the next valid packet.
int16_t api_scanForUAVTalkPacket(void *buf, uint16_t *len)
{
uint8_t *buffer = (uint8_t *)buf;
t_uav_header1 *header1 = (t_uav_header1 *)buf;
// t_uav_header2 *header2 = (t_uav_header2 *)buf;
register uint16_t num_bytes = *len;
if (num_bytes < MIN_HEADER_LENGTH + CHECKSUM_LENGTH)
return -1; // not yet enough bytes for a complete packet
while (TRUE)
{
// scan the buffer for the start of a UAVTalk packet
for (uint16_t i = 0; i < num_bytes; i++)
{
if (api_rx_buffer[i] != SYNC_VAL)
continue; // not the start of a packet - move on to the next byte in the buffer
// possible start of packet found - we found a SYNC byte
if (i > 0)
{ // remove/delete leading bytes before the SYNC byte
num_bytes -= i;
if (num_bytes > 0)
memmove(buffer, buffer + i, num_bytes);
*len = num_bytes;
}
break;
}
if (num_bytes < MIN_HEADER_LENGTH + CHECKSUM_LENGTH)
return -2; // not yet enough bytes for a complete packet
if (header1->sync_byte != SYNC_VAL)
{ // SYNC byte was not found - start of UAVTalk packet not found in any of the data in the buffer
*len = 0; // empty the entire buffer
return -3;
}
if (header1->packet_size < MIN_HEADER_LENGTH || header1->packet_size > MAX_HEADER_LENGTH + MAX_PAYLOAD_LENGTH)
{ // the packet size value is too small or too big - assume either a corrupt UAVTalk packet or we are at the start of a packet
// if (--num_bytes > 0)
// memmove(buffer, buffer + 1, num_bytes); // remove 1st byte
// *len = num_bytes;
buffer[0] ^= 0xaa; // corrupt the sync byte - we'll move the buffer bytes down further up in the code
continue; // continue scanning for a valid packet in the buffer
}
if (num_bytes < header1->packet_size + CHECKSUM_LENGTH)
{ // not yet enough bytes for a complete packet
return -4;
}
// check the packet CRC
uint8_t crc1 = api_updateCRC_buffer(0, buffer, header1->packet_size);
uint8_t crc2 = buffer[header1->packet_size];
if (crc1 != crc2)
{ // faulty CRC
// if (--num_bytes > 0)
// memmove(buffer, buffer + 1, num_bytes); // remove 1st byte
// *len = num_bytes;
buffer[0] ^= 0xaa; // corrupt the sync byte - we'll move the buffer bytes down further up in the code
#if defined(API_DEBUG)
DEBUG_PRINTF("UAVTalk packet corrupt %d\r\n", header1->packet_size + 1);
#endif
continue; // continue scanning for a valid packet in the buffer
}
#if defined(API_DEBUG)
DEBUG_PRINTF("UAVTalk packet found %d\r\n", header1->packet_size + 1);
#endif
return (header1->packet_size + CHECKSUM_LENGTH); // return the size of the UAVTalk packet
}
return -5;
}
// *****************************************************************************
// can be called from an interrupt if you wish
void api_1ms_tick(void)
{ // call this once every 1ms
if (api_rx_timer < 0xffff) api_rx_timer++;
if (api_tx_timer < 0xffff) api_tx_timer++;
}
// *****************************************************************************
// call this as often as possible - not from an interrupt
void api_process(void)
{ // copy data from comm-port RX buffer to RF packet handler TX buffer, and from RF packet handler RX buffer to comm-port TX buffer
// ********************
// decide which comm-port we are using (usart or usb)
bool usb_comms = false; // TRUE if we are using the usb port for comms.
uint8_t comm_port = PIOS_COM_SERIAL; // default to using the usart comm-port
#if defined(PIOS_INCLUDE_USB_HID)
if (PIOS_USB_HID_CheckAvailable(0))
{ // USB comms is up, use the USB comm-port instead of the USART comm-port
usb_comms = true;
comm_port = PIOS_COM_TELEM_USB;
}
#endif
// ********************
// check to see if the local communication port has changed (usart/usb)
if (api_previous_com_port < 0 && api_previous_com_port != comm_port)
{ // the local communications port has changed .. remove any data in the buffers
api_rx_buffer_wr = 0;
api_tx_buffer_wr = 0;
}
else
if (usb_comms)
{ // we're using the USB for comms - keep the USART rx buffer empty
int32_t bytes = PIOS_COM_ReceiveBufferUsed(PIOS_COM_SERIAL);
while (bytes > 0)
{
PIOS_COM_ReceiveBuffer(PIOS_COM_SERIAL);
bytes--;
}
}
api_previous_com_port = comm_port; // remember the current comm-port we are using
// ********************
uint16_t connection_index = 0; // the RF connection we are using
// ********************
// send the data received down the comm-port to the RF packet handler TX buffer
while (TRUE)
{
// free space size in the RF packet handler tx buffer
uint16_t ph_num = ph_putData_free(connection_index);
// get the number of data bytes received down the comm-port
int32_t com_num = PIOS_COM_ReceiveBufferUsed(comm_port);
// set the USART RTS handshaking line
if (!usb_comms && ph_connected(connection_index))
{
if (ph_num < 32)
SERIAL_RTS_CLEAR; // lower the USART RTS line - we don't have space in the buffer for anymore bytes
else
SERIAL_RTS_SET; // release the USART RTS line - we have space in the buffer for now bytes
}
else
SERIAL_RTS_SET; // release the USART RTS line
// limit number of bytes we will get to how much space we have in our RX buffer
if (com_num > sizeof(api_rx_buffer) - api_rx_buffer_wr)
com_num = sizeof(api_rx_buffer) - api_rx_buffer_wr;
while (com_num > 0)
{ // fetch a byte from the comm-port RX buffer and save it into our RX buffer
api_rx_buffer[api_rx_buffer_wr++] = PIOS_COM_ReceiveBuffer(comm_port);
com_num--;
}
int16_t packet_size = api_scanForUAVTalkPacket(api_rx_buffer, &api_rx_buffer_wr);
if (packet_size < 0)
break; // no UAVTalk packet in our RX buffer
api_rx_timer = 0;
if (!ph_connected(connection_index))
{ // we don't have a link to a remote modem .. remove the UAVTalk packet from our RX buffer
if (api_rx_buffer_wr > packet_size)
{
api_rx_buffer_wr -= packet_size;
memmove(api_rx_buffer, api_rx_buffer + packet_size, api_rx_buffer_wr);
}
else
api_rx_buffer_wr = 0;
continue;
}
if (ph_num < packet_size)
break; // not enough room in the RF packet handler TX buffer for the UAVTalk packet
// copy the rx'ed UAVTalk packet into the RF packet handler TX buffer for sending over the RF link
ph_putData(connection_index, api_rx_buffer, packet_size);
// remove the UAVTalk packet from our RX buffer
if (api_rx_buffer_wr > packet_size)
{
api_rx_buffer_wr -= packet_size;
memmove(api_rx_buffer, api_rx_buffer + packet_size, api_rx_buffer_wr);
}
else
api_rx_buffer_wr = 0;
}
// ********************
// send the data received via the RF link out the comm-port
while (TRUE)
{
// get number of data bytes received via the RF link
uint16_t ph_num = ph_getData_used(connection_index);
// limit to how much space we have in the temp TX buffer
if (ph_num > sizeof(api_tx_buffer) - api_tx_buffer_wr)
ph_num = sizeof(api_tx_buffer) - api_tx_buffer_wr;
if (ph_num > 0)
{ // fetch the data bytes received via the RF link and save into our temp buffer
ph_num = ph_getData(connection_index, api_tx_buffer + api_tx_buffer_wr, ph_num);
api_tx_buffer_wr += ph_num;
}
int16_t packet_size = api_scanForUAVTalkPacket(api_tx_buffer, &api_tx_buffer_wr);
if (packet_size <= 0)
break; // no UAV Talk packet found
// we have a UAVTalk packet to send down the comm-port
/*
#if (defined(PIOS_COM_DEBUG) && (PIOS_COM_DEBUG == PIOS_COM_SERIAL))
if (!usb_comms)
{ // the serial-port is being used for debugging - don't send data down it
api_tx_buffer_wr = 0;
api_tx_timer = 0;
continue;
}
#endif
*/
if (!usb_comms && !GPIO_IN(SERIAL_CTS_PIN))
break; // we can't yet send data down the comm-port
// send the data out the comm-port
int32_t res;
// if (usb_comms)
// res = PIOS_COM_SendBuffer(comm_port, api_tx_buffer, packet_size);
// else
res = PIOS_COM_SendBufferNonBlocking(comm_port, api_tx_buffer, packet_size); // this one doesn't work properly with USB :(
if (res < 0)
{ // failed to send the data out the comm-port
#if defined(API_DEBUG)
DEBUG_PRINTF("PIOS_COM_SendBuffer %d %d\r\n", packet_size, res);
#endif
if (api_tx_timer >= 5000)
{ // seems we can't send our data for at least the last 5 seconds - delete it
if (api_tx_buffer_wr > packet_size)
{
api_tx_buffer_wr -= packet_size;
memmove(api_tx_buffer, api_tx_buffer + packet_size, api_tx_buffer_wr);
}
else
api_tx_buffer_wr = 0;
}
break;
}
// data was sent out the comm-port OK .. remove the sent data from our buffer
if (api_tx_buffer_wr > packet_size)
{
api_tx_buffer_wr -= packet_size;
memmove(api_tx_buffer, api_tx_buffer + packet_size, api_tx_buffer_wr);
}
else
api_tx_buffer_wr = 0;
api_tx_timer = 0;
}
// ********************
}
// *****************************************************************************
void api_init(void)
{
api_previous_com_port = -1;
api_rx_buffer_wr = 0;
api_tx_buffer_wr = 0;
api_rx_timer = 0;
api_tx_timer = 0;
}
// *****************************************************************************

38
flight/PipXtreme/api_config.c
View File

@ -43,12 +43,14 @@
#define PIPX_HEADER_MARKER 0x76b38a52
#define PIPX_PACKET_TYPE_REQ_DETAILS 0
#define PIPX_PACKET_TYPE_DETAILS 1
#define PIPX_PACKET_TYPE_REQ_SETTINGS 2
#define PIPX_PACKET_TYPE_SETTINGS 3
#define PIPX_PACKET_TYPE_REQ_STATE 4
#define PIPX_PACKET_TYPE_STATE 5
enum {
PIPX_PACKET_TYPE_REQ_DETAILS = 0,
PIPX_PACKET_TYPE_DETAILS,
PIPX_PACKET_TYPE_REQ_SETTINGS,
PIPX_PACKET_TYPE_SETTINGS,
PIPX_PACKET_TYPE_REQ_STATE,
PIPX_PACKET_TYPE_STATE
};
typedef struct
{
@ -137,8 +139,8 @@ int apiconfig_sendDetailsPacket(void)
header->spare = 0;
header->data_size = sizeof(t_pipx_config_details);
details->major_version = version_major;
details->minor_version = version_minor;
details->major_version = VERSION_MAJOR;
details->minor_version = VERSION_MINOR;
details->serial_number = serial_number_crc32;
details->min_frequency_Hz = saved_settings.min_frequency_Hz;
details->max_frequency_Hz = saved_settings.max_frequency_Hz;
@ -311,24 +313,24 @@ void apiconfig_processInputPacket(void *buf, uint16_t len)
ph_set_remote_encryption(0, saved_settings.aes_enable, (const void *)saved_settings.aes_key);
switch (saved_settings.mode)
{
case modeNormal: // normal 2-way packet mode
case MODE_NORMAL: // normal 2-way packet mode
break;
case modeStreamTx: // 1-way continuous tx packet mode
case MODE_STREAM_TX: // 1-way continuous tx packet mode
break;
case modeStreamRx: // 1-way continuous rx packet mode
case MODE_STREAM_RX: // 1-way continuous rx packet mode
break;
case modePPMTx: // PPM tx mode
case MODE_PPM_TX: // PPM tx mode
break;
case modePPMRx: // PPM rx mode
case MODE_PPM_RX: // PPM rx mode
break;
case modeScanSpectrum: // scan the receiver over the whole band
case MODE_SCAN_SPECTRUM: // scan the receiver over the whole band
break;
case modeTxBlankCarrierTest: // blank carrier Tx mode (for calibrating the carrier frequency say)
case MODE_TX_BLANK_CARRIER_TEST: // blank carrier Tx mode (for calibrating the carrier frequency say)
break;
case modeTxSpectrumTest: // pseudo random Tx data mode (for checking the Tx carrier spectrum)
case MODE_TX_SPECTRUM_TEST: // pseudo random Tx data mode (for checking the Tx carrier spectrum)
break;
default: // unknown mode
saved_settings.mode = modeNormal;
default: // unknown mode
saved_settings.mode = MODE_NORMAL;
break;
}
}

40
flight/PipXtreme/inc/api_comms.h
View File

@ -1,40 +0,0 @@
/**
******************************************************************************
*
* @file api_comms.h
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
* @brief RF Module hardware layer
* @see The GNU Public License (GPL) Version 3
*
*****************************************************************************/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __API_COMMS_H__
#define __API_COMMS_H__
#include "stdint.h"
// *****************************************************************************
void api_1ms_tick(void);
void api_process(void);
void api_init(void);
// *****************************************************************************
#endif

28
flight/PipXtreme/inc/main.h
View File

@ -32,8 +32,8 @@
// *****************************************************************************
// firmware version
#define version_major 0 // 0 to 255
#define version_minor 2 // 0 to 255
#define VERSION_MAJOR 0 // 0 to 255
#define VERSION_MINOR 3 // 0 to 255
// macro's for reading internal flash memory
#define mem8(addr) (*((volatile uint8_t *)(addr)))
@ -41,21 +41,21 @@
#define mem32(addr) (*((volatile uint32_t *)(addr)))
enum {
freqBand_UNKNOWN = 0,
freqBand_434MHz,
freqBand_868MHz,
freqBand_915MHz
FREQBAND_UNKNOWN = 0,
FREQBAND_434MHz,
FREQBAND_868MHz,
FREQBAND_915MHz
};
enum {
modeNormal = 0, // normal 2-way packet mode
modeStreamTx, // 1-way continuous tx packet mode
modeStreamRx, // 1-way continuous rx packet mode
modePPMTx, // PPM tx mode
modePPMRx, // PPM rx mode
modeScanSpectrum, // scan the receiver over the whole band
modeTxBlankCarrierTest, // blank carrier Tx mode (for calibrating the carrier frequency say)
modeTxSpectrumTest // pseudo random Tx data mode (for checking the Tx carrier spectrum)
MODE_NORMAL = 0, // normal 2-way packet mode
MODE_STREAM_TX, // 1-way continuous tx packet mode
MODE_STREAM_RX, // 1-way continuous rx packet mode
MODE_PPM_TX, // PPM tx mode
MODE_PPM_RX, // PPM rx mode
MODE_SCAN_SPECTRUM, // scan the receiver over the whole band
MODE_TX_BLANK_CARRIER_TEST, // blank carrier Tx mode (for calibrating the carrier frequency say)
MODE_TX_SPECTRUM_TEST // pseudo random Tx data mode (for checking the Tx carrier spectrum)
};
// *****************************************************************************

860
flight/PipXtreme/inc/rfm22b.h
View File

@ -61,514 +61,514 @@ enum { RX_WAIT_PREAMBLE_MODE = 0,
// ************************************
#define rfm22_device_type 0x00 // R
#define rfm22_dt_mask 0x1F
#define RFM22_device_type 0x00 // R
#define RFM22_dt_mask 0x1F
#define rfm22_device_version 0x01 // R
#define rfm22_dv_mask 0x1F
#define RFM22_device_version 0x01 // R
#define RFM22_dv_mask 0x1F
#define rfm22_device_status 0x02 // R
#define rfm22_ds_cps_mask 0x03 // Chip Power State mask
#define rfm22_ds_cps_idle 0x00 // IDLE Chip Power State
#define rfm22_ds_cps_rx 0x01 // RX Chip Power State
#define rfm22_ds_cps_tx 0x02 // TX Chip Power State
//#define rfm22_ds_lockdet 0x04 //
//#define rfm22_ds_freqerr 0x08 //
#define rfm22_ds_headerr 0x10 // Header Error Status. Indicates if the received packet has a header check error
#define rfm22_ds_rxffem 0x20 // RX FIFO Empty Status
#define rfm22_ds_ffunfl 0x40 // RX/TX FIFO Underflow Status
#define rfm22_ds_ffovfl 0x80 // RX/TX FIFO Overflow Status
#define RFM22_device_status 0x02 // R
#define RFM22_ds_cps_mask 0x03 // Chip Power State mask
#define RFM22_ds_cps_idle 0x00 // IDLE Chip Power State
#define RFM22_ds_cps_rx 0x01 // RX Chip Power State
#define RFM22_ds_cps_tx 0x02 // TX Chip Power State
//#define RFM22_ds_lockdet 0x04 //
//#define RFM22_ds_freqerr 0x08 //
#define RFM22_ds_headerr 0x10 // Header Error Status. Indicates if the received packet has a header check error
#define RFM22_ds_rxffem 0x20 // RX FIFO Empty Status
#define RFM22_ds_ffunfl 0x40 // RX/TX FIFO Underflow Status
#define RFM22_ds_ffovfl 0x80 // RX/TX FIFO Overflow Status
#define rfm22_interrupt_status1 0x03 // R
#define rfm22_is1_icrerror BIT0 // CRC Error. When set to 1 the cyclic redundancy check is failed.
#define rfm22_is1_ipkvalid BIT1 // Valid Packet Received.When set to 1 a valid packet has been received.
#define rfm22_is1_ipksent BIT2 // Packet Sent Interrupt. When set to1 a valid packet has been transmitted.
#define rfm22_is1_iext BIT3 // External Interrupt. When set to 1 an interrupt occurred on one of the GPIO’s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details.
#define rfm22_is1_irxffafull BIT4 // RX FIFO Almost Full.When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the microcontroller.
#define rfm22_is1_ixtffaem BIT5 // TX FIFO Almost Empty. When set to 1 the TX FIFO is almost empty and needs to be filled.
#define rfm22_is1_itxffafull BIT6 // TX FIFO Almost Full. When set to 1 the TX FIFO has met its almost full threshold and needs to be transmitted.
#define rfm22_is1_ifferr BIT7 // FIFO Underflow/Overflow Error. When set to 1 the TX or RX FIFO has overflowed or underflowed.
#define RFM22_interrupt_status1 0x03 // R
#define RFM22_is1_icrerror BIT0 // CRC Error. When set to 1 the cyclic redundancy check is failed.
#define RFM22_is1_ipkvalid BIT1 // Valid Packet Received.When set to 1 a valid packet has been received.
#define RFM22_is1_ipksent BIT2 // Packet Sent Interrupt. When set to1 a valid packet has been transmitted.
#define RFM22_is1_iext BIT3 // External Interrupt. When set to 1 an interrupt occurred on one of the GPIO’s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details.
#define RFM22_is1_irxffafull BIT4 // RX FIFO Almost Full.When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the microcontroller.
#define RFM22_is1_ixtffaem BIT5 // TX FIFO Almost Empty. When set to 1 the TX FIFO is almost empty and needs to be filled.
#define RFM22_is1_itxffafull BIT6 // TX FIFO Almost Full. When set to 1 the TX FIFO has met its almost full threshold and needs to be transmitted.
#define RFM22_is1_ifferr BIT7 // FIFO Underflow/Overflow Error. When set to 1 the TX or RX FIFO has overflowed or underflowed.
#define rfm22_interrupt_status2 0x04 // R
#define rfm22_is2_ipor BIT0 // Power-on-Reset (POR). When the chip detects a Power on Reset above the desired setting this bit will be set to 1.
#define rfm22_is2_ichiprdy BIT1 // Chip Ready (XTAL). When a chip ready event has been detected this bit will be set to 1.
#define rfm22_is2_ilbd BIT2 // Low Battery Detect. When a low battery event is been detected this bit will be set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled.
#define rfm22_is2_iwut BIT3 // Wake-Up-Timer. On the expiration of programmed wake-up timer this bit will be set to 1.
#define rfm22_is2_irssi BIT4 // RSSI. When RSSI level exceeds the programmed threshold this bit will be set to 1.
#define rfm22_is2_ipreainval BIT5 // Invalid Preamble Detected. When the preamble is not found within a period of time set by the invalid preamble detection threshold in Register 54h, this bit will be set to 1.
#define rfm22_is2_ipreaval BIT6 // Valid Preamble Detected. When a preamble is detected this bit will be set to 1.
#define rfm22_is2_iswdet BIT7 // Sync Word Detected. When a sync word is detected this bit will be set to 1.
#define RFM22_interrupt_status2 0x04 // R
#define RFM22_is2_ipor BIT0 // Power-on-Reset (POR). When the chip detects a Power on Reset above the desired setting this bit will be set to 1.
#define RFM22_is2_ichiprdy BIT1 // Chip Ready (XTAL). When a chip ready event has been detected this bit will be set to 1.
#define RFM22_is2_ilbd BIT2 // Low Battery Detect. When a low battery event is been detected this bit will be set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled.
#define RFM22_is2_iwut BIT3 // Wake-Up-Timer. On the expiration of programmed wake-up timer this bit will be set to 1.
#define RFM22_is2_irssi BIT4 // RSSI. When RSSI level exceeds the programmed threshold this bit will be set to 1.
#define RFM22_is2_ipreainval BIT5 // Invalid Preamble Detected. When the preamble is not found within a period of time set by the invalid preamble detection threshold in Register 54h, this bit will be set to 1.
#define RFM22_is2_ipreaval BIT6 // Valid Preamble Detected. When a preamble is detected this bit will be set to 1.
#define RFM22_is2_iswdet BIT7 // Sync Word Detected. When a sync word is detected this bit will be set to 1.
#define rfm22_interrupt_enable1 0x05 // R/W
#define rfm22_ie1_encrcerror BIT0 // Enable CRC Error. When set to 1 the CRC Error interrupt will be enabled.
#define rfm22_ie1_enpkvalid BIT1 // Enable Valid Packet Received. When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled.
#define rfm22_ie1_enpksent BIT2 // Enable Packet Sent. When ipksent =1 the Packet Sense Interrupt will be enabled.
#define rfm22_ie1_enext BIT3 // Enable External Interrupt. When set to 1 the External Interrupt will be enabled.
#define rfm22_ie1_enrxffafull BIT4 // Enable RX FIFO Almost Full. When set to 1 the RX FIFO Almost Full interrupt will be enabled.
#define rfm22_ie1_entxffaem BIT5 // Enable TX FIFO Almost Empty. When set to 1 the TX FIFO Almost Empty interrupt will be enabled.
#define rfm22_ie1_entxffafull BIT6 // Enable TX FIFO Almost Full. When set to 1 the TX FIFO Almost Full interrupt will be enabled.
#define rfm22_ie1_enfferr BIT7 // Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled.
#define RFM22_interrupt_enable1 0x05 // R/W
#define RFM22_ie1_encrcerror BIT0 // Enable CRC Error. When set to 1 the CRC Error interrupt will be enabled.
#define RFM22_ie1_enpkvalid BIT1 // Enable Valid Packet Received. When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled.
#define RFM22_ie1_enpksent BIT2 // Enable Packet Sent. When ipksent =1 the Packet Sense Interrupt will be enabled.
#define RFM22_ie1_enext BIT3 // Enable External Interrupt. When set to 1 the External Interrupt will be enabled.
#define RFM22_ie1_enrxffafull BIT4 // Enable RX FIFO Almost Full. When set to 1 the RX FIFO Almost Full interrupt will be enabled.
#define RFM22_ie1_entxffaem BIT5 // Enable TX FIFO Almost Empty. When set to 1 the TX FIFO Almost Empty interrupt will be enabled.
#define RFM22_ie1_entxffafull BIT6 // Enable TX FIFO Almost Full. When set to 1 the TX FIFO Almost Full interrupt will be enabled.
#define RFM22_ie1_enfferr BIT7 // Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled.
#define rfm22_interrupt_enable2 0x06 // R/W
#define rfm22_ie2_enpor BIT0 // Enable POR. When set to 1 the POR interrupt will be enabled.
#define rfm22_ie2_enchiprdy BIT1 // Enable Chip Ready (XTAL). When set to 1 the Chip Ready interrupt will be enabled.
#define rfm22_ie2_enlbd BIT2 // Enable Low Battery Detect. When set to 1 the Low Battery Detect interrupt will be enabled.
#define rfm22_ie2_enwut BIT3 // Enable Wake-Up Timer. When set to 1 the Wake-Up Timer interrupt will be enabled.
#define rfm22_ie2_enrssi BIT4 // Enable RSSI. When set to 1 the RSSI Interrupt will be enabled.
#define rfm22_ie2_enpreainval BIT5 // Enable Invalid Preamble Detected. When mpreadet =1 the Invalid Preamble Detected Interrupt will be enabled.
#define rfm22_ie2_enpreaval BIT6 // Enable Valid Preamble Detected. When mpreadet =1 the Valid Preamble Detected Interrupt will be enabled.
#define rfm22_ie2_enswdet BIT7 // Enable Sync Word Detected. When mpreadet =1 the Preamble Detected Interrupt will be enabled.
#define RFM22_interrupt_enable2 0x06 // R/W
#define RFM22_ie2_enpor BIT0 // Enable POR. When set to 1 the POR interrupt will be enabled.
#define RFM22_ie2_enchiprdy BIT1 // Enable Chip Ready (XTAL). When set to 1 the Chip Ready interrupt will be enabled.
#define RFM22_ie2_enlbd BIT2 // Enable Low Battery Detect. When set to 1 the Low Battery Detect interrupt will be enabled.
#define RFM22_ie2_enwut BIT3 // Enable Wake-Up Timer. When set to 1 the Wake-Up Timer interrupt will be enabled.
#define RFM22_ie2_enrssi BIT4 // Enable RSSI. When set to 1 the RSSI Interrupt will be enabled.
#define RFM22_ie2_enpreainval BIT5 // Enable Invalid Preamble Detected. When mpreadet =1 the Invalid Preamble Detected Interrupt will be enabled.
#define RFM22_ie2_enpreaval BIT6 // Enable Valid Preamble Detected. When mpreadet =1 the Valid Preamble Detected Interrupt will be enabled.
#define RFM22_ie2_enswdet BIT7 // Enable Sync Word Detected. When mpreadet =1 the Preamble Detected Interrupt will be enabled.
#define rfm22_op_and_func_ctrl1 0x07 // R/W
#define rfm22_opfc1_xton 0x01 // READY Mode (Xtal is ON).
#define rfm22_opfc1_pllon 0x02 // TUNE Mode (PLL is ON). When pllon = 1 the PLL will remain enabled in Idle State. This will for faster turn-around time at the cost of increased current consumption in Idle State.
#define rfm22_opfc1_rxon 0x04 // RX on in Manual Receiver Mode. Automatically cleared if Multiple Packets config. is disabled and a valid packet received.
#define rfm22_opfc1_txon 0x08 // TX on in Manual Transmit Mode. Automatically cleared in FIFO mode once the packet is sent. Transmission can be aborted during packet transmission, however, when no data has been sent yet, transmission can only be aborted after the device is programmed to “unmodulated carrier” ("Register 71h. Modulation Mode Control 2").
#define rfm22_opfc1_x32ksel 0x10 // 32,768 kHz Crystal Oscillator Select. 0: RC oscillator 1: 32 kHz crystal
#define rfm22_opfc1_enwt 0x20 // Enable Wake-Up-Timer. Enabled when enwt = 1. If the Wake-up-Timer function is enabled it will operate in any mode and notify the microcontroller through the GPIO interrupt when the timer expires.
#define rfm22_opfc1_enlbd 0x40 // Enable Low Battery Detect. When this bit is set to 1 the Low Battery Detector circuit and threshold comparison will be enabled.
#define rfm22_opfc1_swres 0x80 // Software Register Reset Bit. This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register. The RESET is accomplished by setting swres = 1. This bit will be automatically cleared.
#define RFM22_op_and_func_ctrl1 0x07 // R/W
#define RFM22_opfc1_xton 0x01 // READY Mode (Xtal is ON).
#define RFM22_opfc1_pllon 0x02 // TUNE Mode (PLL is ON). When pllon = 1 the PLL will remain enabled in Idle State. This will for faster turn-around time at the cost of increased current consumption in Idle State.
#define RFM22_opfc1_rxon 0x04 // RX on in Manual Receiver Mode. Automatically cleared if Multiple Packets config. is disabled and a valid packet received.
#define RFM22_opfc1_txon 0x08 // TX on in Manual Transmit Mode. Automatically cleared in FIFO mode once the packet is sent. Transmission can be aborted during packet transmission, however, when no data has been sent yet, transmission can only be aborted after the device is programmed to “unmodulated carrier” ("Register 71h. Modulation Mode Control 2").
#define RFM22_opfc1_x32ksel 0x10 // 32,768 kHz Crystal Oscillator Select. 0: RC oscillator 1: 32 kHz crystal
#define RFM22_opfc1_enwt 0x20 // Enable Wake-Up-Timer. Enabled when enwt = 1. If the Wake-up-Timer function is enabled it will operate in any mode and notify the microcontroller through the GPIO interrupt when the timer expires.
#define RFM22_opfc1_enlbd 0x40 // Enable Low Battery Detect. When this bit is set to 1 the Low Battery Detector circuit and threshold comparison will be enabled.
#define RFM22_opfc1_swres 0x80 // Software Register Reset Bit. This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register. The RESET is accomplished by setting swres = 1. This bit will be automatically cleared.
#define rfm22_op_and_func_ctrl2 0x08 // R/W
#define rfm22_opfc2_ffclrtx 0x01 // TX FIFO Reset/Clear. This has to be a two writes operation: Setting ffclrtx =1 followed by ffclrtx = 0 will clear the contents of the TX FIFO.
#define rfm22_opfc2_ffclrrx 0x02 // RX FIFO Reset/Clear. This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the contents of the RX FIFO.
#define rfm22_opfc2_enldm 0x04 // Enable Low Duty Cycle Mode. If this bit is set to 1 then the chip turns on the RX regularly. The frequency should be set in the Wake-Up Timer Period register, while the minimum ON time should be set in the Low-Duty Cycle Mode Duration register. The FIFO mode should be enabled also.
#define rfm22_opfc2_autotx 0x08 // Automatic Transmission. When autotx = 1 the transceiver will enter automatically TX State when the FIFO is almost full. When the FIFO is empty it will automatically return to the Idle State.
#define rfm22_opfc2_rxmpk 0x10 // RX Multi Packet. When the chip is selected to use FIFO Mode (dtmod[1:0]) and RX Packet Handling (enpacrx) then it will fill up the FIFO with multiple valid packets if this bit is set, otherwise the transceiver will automatically leave the RX State after the first valid packet has been received.
#define rfm22_opfc2_antdiv_mask 0xE0 // Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
#define RFM22_op_and_func_ctrl2 0x08 // R/W
#define RFM22_opfc2_ffclrtx 0x01 // TX FIFO Reset/Clear. This has to be a two writes operation: Setting ffclrtx =1 followed by ffclrtx = 0 will clear the contents of the TX FIFO.
#define RFM22_opfc2_ffclrrx 0x02 // RX FIFO Reset/Clear. This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the contents of the RX FIFO.
#define RFM22_opfc2_enldm 0x04 // Enable Low Duty Cycle Mode. If this bit is set to 1 then the chip turns on the RX regularly. The frequency should be set in the Wake-Up Timer Period register, while the minimum ON time should be set in the Low-Duty Cycle Mode Duration register. The FIFO mode should be enabled also.
#define RFM22_opfc2_autotx 0x08 // Automatic Transmission. When autotx = 1 the transceiver will enter automatically TX State when the FIFO is almost full. When the FIFO is empty it will automatically return to the Idle State.
#define RFM22_opfc2_rxmpk 0x10 // RX Multi Packet. When the chip is selected to use FIFO Mode (dtmod[1:0]) and RX Packet Handling (enpacrx) then it will fill up the FIFO with multiple valid packets if this bit is set, otherwise the transceiver will automatically leave the RX State after the first valid packet has been received.
#define RFM22_opfc2_antdiv_mask 0xE0 // Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
#define rfm22_xtal_osc_load_cap 0x09 // R/W
#define rfm22_xolc_xlc_mask 0x7F // Tuning Capacitance for the 30 MHz XTAL.
#define rfm22_xolc_xtalshft 0x80 // Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. Not binary with xlc[6:0].
#define RFM22_xtal_osc_load_cap 0x09 // R/W
#define RFM22_xolc_xlc_mask 0x7F // Tuning Capacitance for the 30 MHz XTAL.
#define RFM22_xolc_xtalshft 0x80 // Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. Not binary with xlc[6:0].
#define rfm22_cpu_output_clk 0x0A // R/W
#define rfm22_coc_30MHz 0x00
#define rfm22_coc_15MHz 0x01
#define rfm22_coc_10MHz 0x02
#define rfm22_coc_4MHz 0x03
#define rfm22_coc_3MHz 0x04
#define rfm22_coc_2MHz 0x05
#define rfm22_coc_1MHz 0x06
#define rfm22_coc_32768Hz 0x07
#define rfm22_coc_enlfc 0x08
#define rfm22_coc_0cycle 0x00
#define rfm22_coc_128cycles 0x10
#define rfm22_coc_256cycles 0x20
#define rfm22_coc_512cycles 0x30
#define RFM22_cpu_output_clk 0x0A // R/W
#define RFM22_coc_30MHz 0x00
#define RFM22_coc_15MHz 0x01
#define RFM22_coc_10MHz 0x02
#define RFM22_coc_4MHz 0x03
#define RFM22_coc_3MHz 0x04
#define RFM22_coc_2MHz 0x05
#define RFM22_coc_1MHz 0x06
#define RFM22_coc_32768Hz 0x07
#define RFM22_coc_enlfc 0x08
#define RFM22_coc_0cycle 0x00
#define RFM22_coc_128cycles 0x10
#define RFM22_coc_256cycles 0x20
#define RFM22_coc_512cycles 0x30
#define rfm22_gpio0_config 0x0B // R/W
#define rfm22_gpio0_config_por 0x00 // Power-On-Reset (output)
#define rfm22_gpio0_config_wut 0x01 // Wake-Up Timer: 1 when WUT has expired (output)
#define rfm22_gpio0_config_lbd 0x02 // Low Battery Detect: 1 when battery is below threshold setting (output)
#define rfm22_gpio0_config_ddi 0x03 // Direct Digital Input
#define rfm22_gpio0_config_eife 0x04 // External Interrupt, falling edge (input)
#define rfm22_gpio0_config_eire 0x05 // External Interrupt, rising edge (input)
#define rfm22_gpio0_config_eisc 0x06 // External Interrupt, state change (input)
#define rfm22_gpio0_config_ai 0x07 // ADC Analog Input
#define rfm22_gpio0_config_atni 0x08 // Reserved (Analog Test N Input)
#define rfm22_gpio0_config_atpi 0x09 // Reserved (Analog Test P Input)
#define rfm22_gpio0_config_ddo 0x0A // Direct Digital Output
#define rfm22_gpio0_config_dto 0x0B // Reserved (Digital Test Output)
#define rfm22_gpio0_config_atno 0x0C // Reserved (Analog Test N Output)
#define rfm22_gpio0_config_atpo 0x0D // Reserved (Analog Test P Output)
#define rfm22_gpio0_config_rv 0xOE // Reference Voltage (output)
#define rfm22_gpio0_config_dclk 0x0F // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
#define rfm22_gpio0_config_txd 0x10 // TX Data input for direct modulation (input)
#define rfm22_gpio0_config_err 0x11 // External Retransmission Request (input)
#define rfm22_gpio0_config_txstate 0x12 // TX State (output)
#define rfm22_gpio0_config_txfifoaf 0x13 // TX FIFO Almost Full (output)
#define rfm22_gpio0_config_rxd 0x14 // RX Data (output)
#define rfm22_gpio0_config_rxstate 0x15 // RX State (output)
#define rfm22_gpio0_config_rxfifoaf 0x16 // RX FIFO Almost Full (output)
#define rfm22_gpio0_config_antswt1 0x17 // Antenna 1 Switch used for antenna diversity (output)
#define rfm22_gpio0_config_antswt2 0x18 // Antenna 2 Switch used for antenna diversity (output)
#define rfm22_gpio0_config_vpd 0x19 // Valid Preamble Detected (output)
#define rfm22_gpio0_config_ipd 0x1A // Invalid Preamble Detected (output)
#define rfm22_gpio0_config_swd 0x1B // Sync Word Detected (output)
#define rfm22_gpio0_config_cca 0x1C // Clear Channel Assessment (output)
#define rfm22_gpio0_config_vdd 0x1D // VDD
#define rfm22_gpio0_config_pup 0x20
#define rfm22_gpio0_config_drv0 0x00 // output drive level
#define rfm22_gpio0_config_drv1 0x40 // output drive level
#define rfm22_gpio0_config_drv2 0x80 // output drive level
#define rfm22_gpio0_config_drv3 0xC0 // output drive level
#define RFM22_gpio0_config 0x0B // R/W
#define RFM22_gpio0_config_por 0x00 // Power-On-Reset (output)
#define RFM22_gpio0_config_wut 0x01 // Wake-Up Timer: 1 when WUT has expired (output)
#define RFM22_gpio0_config_lbd 0x02 // Low Battery Detect: 1 when battery is below threshold setting (output)
#define RFM22_gpio0_config_ddi 0x03 // Direct Digital Input
#define RFM22_gpio0_config_eife 0x04 // External Interrupt, falling edge (input)
#define RFM22_gpio0_config_eire 0x05 // External Interrupt, rising edge (input)
#define RFM22_gpio0_config_eisc 0x06 // External Interrupt, state change (input)
#define RFM22_gpio0_config_ai 0x07 // ADC Analog Input
#define RFM22_gpio0_config_atni 0x08 // Reserved (Analog Test N Input)
#define RFM22_gpio0_config_atpi 0x09 // Reserved (Analog Test P Input)
#define RFM22_gpio0_config_ddo 0x0A // Direct Digital Output
#define RFM22_gpio0_config_dto 0x0B // Reserved (Digital Test Output)
#define RFM22_gpio0_config_atno 0x0C // Reserved (Analog Test N Output)
#define RFM22_gpio0_config_atpo 0x0D // Reserved (Analog Test P Output)
#define RFM22_gpio0_config_rv 0xOE // Reference Voltage (output)
#define RFM22_gpio0_config_dclk 0x0F // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
#define RFM22_gpio0_config_txd 0x10 // TX Data input for direct modulation (input)
#define RFM22_gpio0_config_err 0x11 // External Retransmission Request (input)
#define RFM22_gpio0_config_txstate 0x12 // TX State (output)
#define RFM22_gpio0_config_txfifoaf 0x13 // TX FIFO Almost Full (output)
#define RFM22_gpio0_config_rxd 0x14 // RX Data (output)
#define RFM22_gpio0_config_rxstate 0x15 // RX State (output)
#define RFM22_gpio0_config_rxfifoaf 0x16 // RX FIFO Almost Full (output)
#define RFM22_gpio0_config_antswt1 0x17 // Antenna 1 Switch used for antenna diversity (output)
#define RFM22_gpio0_config_antswt2 0x18 // Antenna 2 Switch used for antenna diversity (output)
#define RFM22_gpio0_config_vpd 0x19 // Valid Preamble Detected (output)
#define RFM22_gpio0_config_ipd 0x1A // Invalid Preamble Detected (output)
#define RFM22_gpio0_config_swd 0x1B // Sync Word Detected (output)
#define RFM22_gpio0_config_cca 0x1C // Clear Channel Assessment (output)
#define RFM22_gpio0_config_vdd 0x1D // VDD
#define RFM22_gpio0_config_pup 0x20
#define RFM22_gpio0_config_drv0 0x00 // output drive level
#define RFM22_gpio0_config_drv1 0x40 // output drive level
#define RFM22_gpio0_config_drv2 0x80 // output drive level
#define RFM22_gpio0_config_drv3 0xC0 // output drive level
#define rfm22_gpio1_config 0x0C // R/W
#define rfm22_gpio1_config_ipor 0x00 // Inverted Power-On-Reset (output)
#define rfm22_gpio1_config_wut 0x01 // Wake-Up Timer: 1 when WUT has expired (output)
#define rfm22_gpio1_config_lbd 0x02 // Low Battery Detect: 1 when battery is below threshold setting (output)
#define rfm22_gpio1_config_ddi 0x03 // Direct Digital Input
#define rfm22_gpio1_config_eife 0x04 // External Interrupt, falling edge (input)
#define rfm22_gpio1_config_eire 0x05 // External Interrupt, rising edge (input)
#define rfm22_gpio1_config_eisc 0x06 // External Interrupt, state change (input)
#define rfm22_gpio1_config_ai 0x07 // ADC Analog Input
#define rfm22_gpio1_config_atni 0x08 // Reserved (Analog Test N Input)
#define rfm22_gpio1_config_atpi 0x09 // Reserved (Analog Test P Input)
#define rfm22_gpio1_config_ddo 0x0A // Direct Digital Output
#define rfm22_gpio1_config_dto 0x0B // Reserved (Digital Test Output)
#define rfm22_gpio1_config_atno 0x0C // Reserved (Analog Test N Output)
#define rfm22_gpio1_config_atpo 0x0D // Reserved (Analog Test P Output)
#define rfm22_gpio1_config_rv 0xOE // Reference Voltage (output)
#define rfm22_gpio1_config_dclk 0x0F // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
#define rfm22_gpio1_config_txd 0x10 // TX Data input for direct modulation (input)
#define rfm22_gpio1_config_err 0x11 // External Retransmission Request (input)
#define rfm22_gpio1_config_txstate 0x12 // TX State (output)
#define rfm22_gpio1_config_txfifoaf 0x13 // TX FIFO Almost Full (output)
#define rfm22_gpio1_config_rxd 0x14 // RX Data (output)
#define rfm22_gpio1_config_rxstate 0x15 // RX State (output)
#define rfm22_gpio1_config_rxfifoaf 0x16 // RX FIFO Almost Full (output)
#define rfm22_gpio1_config_antswt1 0x17 // Antenna 1 Switch used for antenna diversity (output)
#define rfm22_gpio1_config_antswt2 0x18 // Antenna 2 Switch used for antenna diversity (output)
#define rfm22_gpio1_config_vpd 0x19 // Valid Preamble Detected (output)
#define rfm22_gpio1_config_ipd 0x1A // Invalid Preamble Detected (output)
#define rfm22_gpio1_config_swd 0x1B // Sync Word Detected (output)
#define rfm22_gpio1_config_cca 0x1C // Clear Channel Assessment (output)
#define rfm22_gpio1_config_vdd 0x1D // VDD
#define rfm22_gpio1_config_pup 0x20
#define rfm22_gpio1_config_drv0 0x00 // output drive level
#define rfm22_gpio1_config_drv1 0x40 // output drive level
#define rfm22_gpio1_config_drv2 0x80 // output drive level
#define rfm22_gpio1_config_drv3 0xC0 // output drive level
#define RFM22_gpio1_config 0x0C // R/W
#define RFM22_gpio1_config_ipor 0x00 // Inverted Power-On-Reset (output)
#define RFM22_gpio1_config_wut 0x01 // Wake-Up Timer: 1 when WUT has expired (output)
#define RFM22_gpio1_config_lbd 0x02 // Low Battery Detect: 1 when battery is below threshold setting (output)
#define RFM22_gpio1_config_ddi 0x03 // Direct Digital Input
#define RFM22_gpio1_config_eife 0x04 // External Interrupt, falling edge (input)
#define RFM22_gpio1_config_eire 0x05 // External Interrupt, rising edge (input)
#define RFM22_gpio1_config_eisc 0x06 // External Interrupt, state change (input)
#define RFM22_gpio1_config_ai 0x07 // ADC Analog Input
#define RFM22_gpio1_config_atni 0x08 // Reserved (Analog Test N Input)
#define RFM22_gpio1_config_atpi 0x09 // Reserved (Analog Test P Input)
#define RFM22_gpio1_config_ddo 0x0A // Direct Digital Output
#define RFM22_gpio1_config_dto 0x0B // Reserved (Digital Test Output)
#define RFM22_gpio1_config_atno 0x0C // Reserved (Analog Test N Output)
#define RFM22_gpio1_config_atpo 0x0D // Reserved (Analog Test P Output)
#define RFM22_gpio1_config_rv 0xOE // Reference Voltage (output)
#define RFM22_gpio1_config_dclk 0x0F // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
#define RFM22_gpio1_config_txd 0x10 // TX Data input for direct modulation (input)
#define RFM22_gpio1_config_err 0x11 // External Retransmission Request (input)
#define RFM22_gpio1_config_txstate 0x12 // TX State (output)
#define RFM22_gpio1_config_txfifoaf 0x13 // TX FIFO Almost Full (output)
#define RFM22_gpio1_config_rxd 0x14 // RX Data (output)
#define RFM22_gpio1_config_rxstate 0x15 // RX State (output)
#define RFM22_gpio1_config_rxfifoaf 0x16 // RX FIFO Almost Full (output)
#define RFM22_gpio1_config_antswt1 0x17 // Antenna 1 Switch used for antenna diversity (output)
#define RFM22_gpio1_config_antswt2 0x18 // Antenna 2 Switch used for antenna diversity (output)
#define RFM22_gpio1_config_vpd 0x19 // Valid Preamble Detected (output)
#define RFM22_gpio1_config_ipd 0x1A // Invalid Preamble Detected (output)
#define RFM22_gpio1_config_swd 0x1B // Sync Word Detected (output)
#define RFM22_gpio1_config_cca 0x1C // Clear Channel Assessment (output)
#define RFM22_gpio1_config_vdd 0x1D // VDD
#define RFM22_gpio1_config_pup 0x20
#define RFM22_gpio1_config_drv0 0x00 // output drive level
#define RFM22_gpio1_config_drv1 0x40 // output drive level
#define RFM22_gpio1_config_drv2 0x80 // output drive level
#define RFM22_gpio1_config_drv3 0xC0 // output drive level
#define rfm22_gpio2_config 0x0D // R/W
#define rfm22_gpio2_config_mc 0x00 // Microcontroller Clock (output)
#define rfm22_gpio2_config_wut 0x01 // Wake-Up Timer: 1 when WUT has expired (output)
#define rfm22_gpio2_config_lbd 0x02 // Low Battery Detect: 1 when battery is below threshold setting (output)
#define rfm22_gpio2_config_ddi 0x03 // Direct Digital Input
#define rfm22_gpio2_config_eife 0x04 // External Interrupt, falling edge (input)
#define rfm22_gpio2_config_eire 0x05 // External Interrupt, rising edge (input)
#define rfm22_gpio2_config_eisc 0x06 // External Interrupt, state change (input)
#define rfm22_gpio2_config_ai 0x07 // ADC Analog Input
#define rfm22_gpio2_config_atni 0x08 // Reserved (Analog Test N Input)
#define rfm22_gpio2_config_atpi 0x09 // Reserved (Analog Test P Input)
#define rfm22_gpio2_config_ddo 0x0A // Direct Digital Output
#define rfm22_gpio2_config_dto 0x0B // Reserved (Digital Test Output)
#define rfm22_gpio2_config_atno 0x0C // Reserved (Analog Test N Output)
#define rfm22_gpio2_config_atpo 0x0D // Reserved (Analog Test P Output)
#define rfm22_gpio2_config_rv 0xOE // Reference Voltage (output)
#define rfm22_gpio2_config_dclk 0x0F // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
#define rfm22_gpio2_config_txd 0x10 // TX Data input for direct modulation (input)
#define rfm22_gpio2_config_err 0x11 // External Retransmission Request (input)
#define rfm22_gpio2_config_txstate 0x12 // TX State (output)
#define rfm22_gpio2_config_txfifoaf 0x13 // TX FIFO Almost Full (output)
#define rfm22_gpio2_config_rxd 0x14 // RX Data (output)
#define rfm22_gpio2_config_rxstate 0x15 // RX State (output)
#define rfm22_gpio2_config_rxfifoaf 0x16 // RX FIFO Almost Full (output)
#define rfm22_gpio2_config_antswt1 0x17 // Antenna 1 Switch used for antenna diversity (output)
#define rfm22_gpio2_config_antswt2 0x18 // Antenna 2 Switch used for antenna diversity (output)
#define rfm22_gpio2_config_vpd 0x19 // Valid Preamble Detected (output)
#define rfm22_gpio2_config_ipd 0x1A // Invalid Preamble Detected (output)
#define rfm22_gpio2_config_swd 0x1B // Sync Word Detected (output)
#define rfm22_gpio2_config_cca 0x1C // Clear Channel Assessment (output)
#define rfm22_gpio2_config_vdd 0x1D // VDD
#define rfm22_gpio2_config_pup 0x20
#define rfm22_gpio2_config_drv0 0x00 // output drive level
#define rfm22_gpio2_config_drv1 0x40 // output drive level
#define rfm22_gpio2_config_drv2 0x80 // output drive level
#define rfm22_gpio2_config_drv3 0xC0 // output drive level
#define RFM22_gpio2_config 0x0D // R/W
#define RFM22_gpio2_config_mc 0x00 // Microcontroller Clock (output)
#define RFM22_gpio2_config_wut 0x01 // Wake-Up Timer: 1 when WUT has expired (output)
#define RFM22_gpio2_config_lbd 0x02 // Low Battery Detect: 1 when battery is below threshold setting (output)
#define RFM22_gpio2_config_ddi 0x03 // Direct Digital Input
#define RFM22_gpio2_config_eife 0x04 // External Interrupt, falling edge (input)
#define RFM22_gpio2_config_eire 0x05 // External Interrupt, rising edge (input)
#define RFM22_gpio2_config_eisc 0x06 // External Interrupt, state change (input)
#define RFM22_gpio2_config_ai 0x07 // ADC Analog Input
#define RFM22_gpio2_config_atni 0x08 // Reserved (Analog Test N Input)
#define RFM22_gpio2_config_atpi 0x09 // Reserved (Analog Test P Input)
#define RFM22_gpio2_config_ddo 0x0A // Direct Digital Output
#define RFM22_gpio2_config_dto 0x0B // Reserved (Digital Test Output)
#define RFM22_gpio2_config_atno 0x0C // Reserved (Analog Test N Output)
#define RFM22_gpio2_config_atpo 0x0D // Reserved (Analog Test P Output)
#define RFM22_gpio2_config_rv 0xOE // Reference Voltage (output)
#define RFM22_gpio2_config_dclk 0x0F // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
#define RFM22_gpio2_config_txd 0x10 // TX Data input for direct modulation (input)
#define RFM22_gpio2_config_err 0x11 // External Retransmission Request (input)
#define RFM22_gpio2_config_txstate 0x12 // TX State (output)
#define RFM22_gpio2_config_txfifoaf 0x13 // TX FIFO Almost Full (output)
#define RFM22_gpio2_config_rxd 0x14 // RX Data (output)
#define RFM22_gpio2_config_rxstate 0x15 // RX State (output)
#define RFM22_gpio2_config_rxfifoaf 0x16 // RX FIFO Almost Full (output)
#define RFM22_gpio2_config_antswt1 0x17 // Antenna 1 Switch used for antenna diversity (output)
#define RFM22_gpio2_config_antswt2 0x18 // Antenna 2 Switch used for antenna diversity (output)
#define RFM22_gpio2_config_vpd 0x19 // Valid Preamble Detected (output)
#define RFM22_gpio2_config_ipd 0x1A // Invalid Preamble Detected (output)
#define RFM22_gpio2_config_swd 0x1B // Sync Word Detected (output)
#define RFM22_gpio2_config_cca 0x1C // Clear Channel Assessment (output)
#define RFM22_gpio2_config_vdd 0x1D // VDD
#define RFM22_gpio2_config_pup 0x20
#define RFM22_gpio2_config_drv0 0x00 // output drive level
#define RFM22_gpio2_config_drv1 0x40 // output drive level
#define RFM22_gpio2_config_drv2 0x80 // output drive level
#define RFM22_gpio2_config_drv3 0xC0 // output drive level
#define rfm22_io_port_config 0x0E // R/W
#define rfm22_io_port_extitst2 0x40 // External Interrupt Status. If the GPIO2 is programmed to be external interrupt sources then the status can be read here.
#define rfm22_io_port_extitst1 0x20 // External Interrupt Status. If the GPIO1 is programmed to be external interrupt sources then the status can be read here.
#define rfm22_io_port_extitst0 0x10 // External Interrupt Status. If the GPIO0 is programmed to be external interrupt sources then the status can be read here.
#define rfm22_io_port_itsdo 0x08 // Interrupt Request Output on the SDO Pin. nIRQ output is present on the SDO pin if this bit is set and the nSEL input is inactive (high).
#define rfm22_io_port_dio2 0x04 // Direct I/O for GPIO2. If the GPIO2 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO2 is configured to be a direct input then the value of the pin can be read here.
#define rfm22_io_port_dio1 0x02 // Direct I/O for GPIO1. If the GPIO1 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO1 is configured to be a direct input then the value of the pin can be read here.
#define rfm22_io_port_dio0 0x01 // Direct I/O for GPIO0. If the GPIO0 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO0 is configured to be a direct input then the value of the pin can be read here.
#define rfm22_io_port_default 0x00 // GPIO pins are default
#define RFM22_io_port_config 0x0E // R/W
#define RFM22_io_port_extitst2 0x40 // External Interrupt Status. If the GPIO2 is programmed to be external interrupt sources then the status can be read here.
#define RFM22_io_port_extitst1 0x20 // External Interrupt Status. If the GPIO1 is programmed to be external interrupt sources then the status can be read here.
#define RFM22_io_port_extitst0 0x10 // External Interrupt Status. If the GPIO0 is programmed to be external interrupt sources then the status can be read here.
#define RFM22_io_port_itsdo 0x08 // Interrupt Request Output on the SDO Pin. nIRQ output is present on the SDO pin if this bit is set and the nSEL input is inactive (high).
#define RFM22_io_port_dio2 0x04 // Direct I/O for GPIO2. If the GPIO2 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO2 is configured to be a direct input then the value of the pin can be read here.
#define RFM22_io_port_dio1 0x02 // Direct I/O for GPIO1. If the GPIO1 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO1 is configured to be a direct input then the value of the pin can be read here.
#define RFM22_io_port_dio0 0x01 // Direct I/O for GPIO0. If the GPIO0 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO0 is configured to be a direct input then the value of the pin can be read here.
#define RFM22_io_port_default 0x00 // GPIO pins are default
#define rfm22_adc_config 0x0F // R/W
#define rfm22_ac_adcgain0 0x00
#define rfm22_ac_adcgain1 0x01
#define rfm22_ac_adcgain2 0x02
#define rfm22_ac_adcgain3 0x03
#define rfm22_ac_adcref_bg 0x00
#define rfm22_ac_adcref_vdd3 0x08
#define rfm22_ac_adcref_vdd2 0x0C
#define rfm22_ac_adcsel_temp_sensor 0x00
#define rfm22_ac_adcsel_gpio0 0x10
#define rfm22_ac_adcsel_gpio1 0x20
#define rfm22_ac_adcsel_gpio2 0x30
#define rfm22_ac_adcsel_gpio01 0x40
#define rfm22_ac_adcsel_gpio12 0x50
#define rfm22_ac_adcsel_gpio02 0x60
#define rfm22_ac_adcsel_gpio_gnd 0x70
#define rfm22_ac_adcstartbusy 0x80
#define RFM22_adc_config 0x0F // R/W
#define RFM22_ac_adcgain0 0x00
#define RFM22_ac_adcgain1 0x01
#define RFM22_ac_adcgain2 0x02
#define RFM22_ac_adcgain3 0x03
#define RFM22_ac_adcref_bg 0x00
#define RFM22_ac_adcref_vdd3 0x08
#define RFM22_ac_adcref_vdd2 0x0C
#define RFM22_ac_adcsel_temp_sensor 0x00
#define RFM22_ac_adcsel_gpio0 0x10
#define RFM22_ac_adcsel_gpio1 0x20
#define RFM22_ac_adcsel_gpio2 0x30
#define RFM22_ac_adcsel_gpio01 0x40
#define RFM22_ac_adcsel_gpio12 0x50
#define RFM22_ac_adcsel_gpio02 0x60
#define RFM22_ac_adcsel_gpio_gnd 0x70
#define RFM22_ac_adcstartbusy 0x80
#define rfm22_adc_sensor_amp_offset 0x10 // R/W
#define rfm22_asao_adcoffs_mask 0x0F // ADC Sensor Amplifier Offset. The offset can be calculated as Offset = adcoffs[2:0] x VDD/1000; MSB = adcoffs[3] = Sign bit.
#define RFM22_adc_sensor_amp_offset 0x10 // R/W
#define RFM22_asao_adcoffs_mask 0x0F // ADC Sensor Amplifier Offset. The offset can be calculated as Offset = adcoffs[2:0] x VDD/1000; MSB = adcoffs[3] = Sign bit.
#define rfm22_adc_value 0x11 // R .. Internal 8 bit ADC Output Value.
#define RFM22_adc_value 0x11 // R .. Internal 8 bit ADC Output Value.
#define rfm22_temp_sensor_calib 0x12 // R/W
#define rfm22_tsc_tstrim_mask 0x0F // Temperature Sensor Trim Value.
#define rfm22_tsc_entstrim 0x10 // Temperature Sensor Trim Enable.
#define rfm22_tsc_entsoffs 0x20 // Temperature Sensor Offset to Convert from K to ºC.
#define rfm22_tsc_tsrange0 0x00 // Temperature Sensor Range Selection. –64C to +64C 0.5C resolution
#define rfm22_tsc_tsrange1 0x40 // -40 to +85C with 1.0C resolution
#define rfm22_tsc_tsrange2 0x80 // 0C to 85C with 0.5C resolution
#define rfm22_tsc_tsrange3 0xC0 // -40F to 216F with 1.0F resolution
#define RFM22_temp_sensor_calib 0x12 // R/W
#define RFM22_tsc_tstrim_mask 0x0F // Temperature Sensor Trim Value.
#define RFM22_tsc_entstrim 0x10 // Temperature Sensor Trim Enable.
#define RFM22_tsc_entsoffs 0x20 // Temperature Sensor Offset to Convert from K to ºC.
#define RFM22_tsc_tsrange0 0x00 // Temperature Sensor Range Selection. –64C to +64C 0.5C resolution
#define RFM22_tsc_tsrange1 0x40 // -40 to +85C with 1.0C resolution
#define RFM22_tsc_tsrange2 0x80 // 0C to 85C with 0.5C resolution
#define RFM22_tsc_tsrange3 0xC0 // -40F to 216F with 1.0F resolution
#define rfm22_temp_value_offset 0x13 // R/W
#define RFM22_temp_value_offset 0x13 // R/W
#define rfm22_wakeup_timer_period1 0x14 // R/W
#define rfm22_wakeup_timer_period2 0x15 // R/W
#define rfm22_wakeup_timer_period3 0x16 // R/W
#define RFM22_wakeup_timer_period1 0x14 // R/W
#define RFM22_wakeup_timer_period2 0x15 // R/W
#define RFM22_wakeup_timer_period3 0x16 // R/W
#define rfm22_wakeup_timer_value1 0x17 // R
#define rfm22_wakeup_timer_value2 0x18 // R
#define RFM22_wakeup_timer_value1 0x17 // R
#define RFM22_wakeup_timer_value2 0x18 // R
#define rfm22_low_dutycycle_mode_duration 0x19 // R/W
#define rfm22_low_battery_detector_threshold 0x1A // R/W
#define RFM22_low_dutycycle_mode_duration 0x19 // R/W
#define RFM22_low_battery_detector_threshold 0x1A // R/W
#define rfm22_battery_volateg_level 0x1B // R
#define RFM22_battery_volateg_level 0x1B // R
#define rfm22_if_filter_bandwidth 0x1C // R/W
#define rfm22_iffbw_filset_mask 0x0F
#define rfm22_iffbw_ndec_exp_mask 0x70
#define rfm22_iffbw_dwn3_bypass 0x80
#define RFM22_if_filter_bandwidth 0x1C // R/W
#define RFM22_iffbw_filset_mask 0x0F
#define RFM22_iffbw_ndec_exp_mask 0x70
#define RFM22_iffbw_dwn3_bypass 0x80
#define rfm22_afc_loop_gearshift_override 0x1D // R/W
#define rfm22_afc_lp_gs_ovrd_afcgearl_mask 0x07 // AFC Low Gear Setting.
#define rfm22_afc_lp_gs_ovrd_afcgearh_mask 0x38 // AFC High Gear Setting.
#define rfm22_afc_lp_gs_ovrd_enafc 0x40 // AFC Enable.
#define rfm22_afc_lp_gs_ovrd_afcbd 0x80 // If set, the tolerated AFC frequency error will be halved.
#define RFM22_afc_loop_gearshift_override 0x1D // R/W
#define RFM22_afc_lp_gs_ovrd_afcgearl_mask 0x07 // AFC Low Gear Setting.
#define RFM22_afc_lp_gs_ovrd_afcgearh_mask 0x38 // AFC High Gear Setting.
#define RFM22_afc_lp_gs_ovrd_enafc 0x40 // AFC Enable.
#define RFM22_afc_lp_gs_ovrd_afcbd 0x80 // If set, the tolerated AFC frequency error will be halved.
#define rfm22_afc_timing_control 0x1E // R/W
#define RFM22_afc_timing_control 0x1E // R/W
#define rfm22_clk_recovery_gearshift_override 0x1F // R/W
#define rfm22_clk_recovery_oversampling_ratio 0x20 // R/W
#define rfm22_clk_recovery_offset2 0x21 // R/W
#define rfm22_clk_recovery_offset1 0x22 // R/W
#define rfm22_clk_recovery_offset0 0x23 // R/W
#define rfm22_clk_recovery_timing_loop_gain1 0x24 // R/W
#define rfm22_clk_recovery_timing_loop_gain0 0x25 // R/W
#define RFM22_clk_recovery_gearshift_override 0x1F // R/W
#define RFM22_clk_recovery_oversampling_ratio 0x20 // R/W
#define RFM22_clk_recovery_offset2 0x21 // R/W
#define RFM22_clk_recovery_offset1 0x22 // R/W
#define RFM22_clk_recovery_offset0 0x23 // R/W
#define RFM22_clk_recovery_timing_loop_gain1 0x24 // R/W
#define RFM22_clk_recovery_timing_loop_gain0 0x25 // R/W
#define rfm22_rssi 0x26 // R
#define rfm22_rssi_threshold_clear_chan_indicator 0x27 // R/W
#define RFM22_rssi 0x26 // R
#define RFM22_rssi_threshold_clear_chan_indicator 0x27 // R/W
#define rfm22_antenna_diversity_register1 0x28 // R
#define rfm22_antenna_diversity_register2 0x29 // R
#define RFM22_antenna_diversity_register1 0x28 // R
#define RFM22_antenna_diversity_register2 0x29 // R
#define rfm22_afc_limiter 0x2A // R/W .. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
#define RFM22_afc_limiter 0x2A // R/W .. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
#define rfm22_afc_correction_read 0x2B // R
#define RFM22_afc_correction_read 0x2B // R
#define rfm22_ook_counter_value1 0x2C // R/W
#define rfm22_ook_counter_value2 0x2D // R/W
#define RFM22_ook_counter_value1 0x2C // R/W
#define RFM22_ook_counter_value2 0x2D // R/W
#define rfm22_slicer_peak_hold 0x2E // R/W
#define RFM22_slicer_peak_hold 0x2E // R/W
#define rfm22_data_access_control 0x30 // R/W
#define rfm22_dac_crc_ccitt 0x00 //
#define rfm22_dac_crc_crc16 0x01 //
#define rfm22_dac_crc_iec16 0x02 //
#define rfm22_dac_crc_biacheva 0x03 //
#define rfm22_dac_encrc 0x04 // CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set.
#define rfm22_dac_enpactx 0x08 // Enable Packet TX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30–4D allow for various configurations of the packet structure. Setting enpactx = 0 will not do any packet handling in the TX path. It will only transmit what is loaded to the FIFO.
#define rfm22_dac_skip2ph 0x10 // Skip 2nd Phase of Preamble Detection. If set, we skip the second phase of the preamble detection (under certain conditions) if antenna diversity is enabled.
#define rfm22_dac_crcdonly 0x20 // CRC Data Only Enable. When this bit is set to 1 the CRC is calculated on and checked against the packet data fields only.
#define rfm22_dac_lsbfrst 0x40 // LSB First Enable. The LSB of the data will be transmitted/received first if this bit is set.
#define rfm22_dac_enpacrx 0x80 // Enable Packet RX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register 30–4D allow for various configurations of the packet structure. Setting enpacrx = 0 will not do any packet handling in the RX path. It will only receive everything after the sync word and fill up the RX FIFO.
#define RFM22_data_access_control 0x30 // R/W
#define RFM22_dac_crc_ccitt 0x00 //
#define RFM22_dac_crc_crc16 0x01 //
#define RFM22_dac_crc_iec16 0x02 //
#define RFM22_dac_crc_biacheva 0x03 //
#define RFM22_dac_encrc 0x04 // CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set.
#define RFM22_dac_enpactx 0x08 // Enable Packet TX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30–4D allow for various configurations of the packet structure. Setting enpactx = 0 will not do any packet handling in the TX path. It will only transmit what is loaded to the FIFO.
#define RFM22_dac_skip2ph 0x10 // Skip 2nd Phase of Preamble Detection. If set, we skip the second phase of the preamble detection (under certain conditions) if antenna diversity is enabled.
#define RFM22_dac_crcdonly 0x20 // CRC Data Only Enable. When this bit is set to 1 the CRC is calculated on and checked against the packet data fields only.
#define RFM22_dac_lsbfrst 0x40 // LSB First Enable. The LSB of the data will be transmitted/received first if this bit is set.
#define RFM22_dac_enpacrx 0x80 // Enable Packet RX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register 30–4D allow for various configurations of the packet structure. Setting enpacrx = 0 will not do any packet handling in the RX path. It will only receive everything after the sync word and fill up the RX FIFO.
#define rfm22_ezmac_status 0x31 // R
#define rfm22_ezmac_status_pksent 0x01 // Packet Sent. A 1 a packet has been sent by the radio. (Same bit as in register 03, but reading it does not reset the IRQ)
#define rfm22_ezmac_status_pktx 0x02 // Packet Transmitting. When 1 the radio is currently transmitting a packet.
#define rfm22_ezmac_status_crcerror 0x04 // CRC Error. When 1 a Cyclic Redundancy Check error has been detected. (Same bit as in register 03, but reading it does not reset the IRQ)
#define rfm22_ezmac_status_pkvalid 0x08 // Valid Packet Received. When a 1 a valid packet has been received by the receiver. (Same bit as in register 03, but reading it does not reset the IRQ)
#define rfm22_ezmac_status_pkrx 0x10 // Packet Receiving. When 1 the radio is currently receiving a valid packet.
#define rfm22_ezmac_status_pksrch 0x20 // Packet Searching. When 1 the radio is searching for a valid packet.
#define rfm22_ezmac_status_rxcrc1 0x40 // If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error.
#define RFM22_ezmac_status 0x31 // R
#define RFM22_ezmac_status_pksent 0x01 // Packet Sent. A 1 a packet has been sent by the radio. (Same bit as in register 03, but reading it does not reset the IRQ)
#define RFM22_ezmac_status_pktx 0x02 // Packet Transmitting. When 1 the radio is currently transmitting a packet.
#define RFM22_ezmac_status_crcerror 0x04 // CRC Error. When 1 a Cyclic Redundancy Check error has been detected. (Same bit as in register 03, but reading it does not reset the IRQ)
#define RFM22_ezmac_status_pkvalid 0x08 // Valid Packet Received. When a 1 a valid packet has been received by the receiver. (Same bit as in register 03, but reading it does not reset the IRQ)
#define RFM22_ezmac_status_pkrx 0x10 // Packet Receiving. When 1 the radio is currently receiving a valid packet.
#define RFM22_ezmac_status_pksrch 0x20 // Packet Searching. When 1 the radio is searching for a valid packet.
#define RFM22_ezmac_status_rxcrc1 0x40 // If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error.
#define rfm22_header_control1 0x32 // R/W
#define rfm22_header_cntl1_bcen_none 0x00 // No broadcast address enable.
#define rfm22_header_cntl1_bcen_0 0x10 // Broadcast address enable for header byte 0.
#define rfm22_header_cntl1_bcen_1 0x20 // Broadcast address enable for header byte 1.
#define rfm22_header_cntl1_bcen_01 0x30 // Broadcast address enable for header bytes 0 & 1.
#define rfm22_header_cntl1_hdch_none 0x00 // No Received Header check
#define rfm22_header_cntl1_hdch_0 0x01 // Received Header check for byte 0.
#define rfm22_header_cntl1_hdch_1 0x02 // Received Header check for byte 1.
#define rfm22_header_cntl1_hdch_01 0x03 // Received Header check for bytes 0 & 1.
#define RFM22_header_control1 0x32 // R/W
#define RFM22_header_cntl1_bcen_none 0x00 // No broadcast address enable.
#define RFM22_header_cntl1_bcen_0 0x10 // Broadcast address enable for header byte 0.
#define RFM22_header_cntl1_bcen_1 0x20 // Broadcast address enable for header byte 1.
#define RFM22_header_cntl1_bcen_01 0x30 // Broadcast address enable for header bytes 0 & 1.
#define RFM22_header_cntl1_hdch_none 0x00 // No Received Header check
#define RFM22_header_cntl1_hdch_0 0x01 // Received Header check for byte 0.
#define RFM22_header_cntl1_hdch_1 0x02 // Received Header check for byte 1.
#define RFM22_header_cntl1_hdch_01 0x03 // Received Header check for bytes 0 & 1.
#define rfm22_header_control2 0x33 // R/W
#define rfm22_header_cntl2_hdlen_none 0x00 // no header
#define rfm22_header_cntl2_hdlen_3 0x10 // header 3
#define rfm22_header_cntl2_hdlen_32 0x20 // header 3 and 2
#define rfm22_header_cntl2_hdlen_321 0x30 // header 3 and 2 and 1
#define rfm22_header_cntl2_hdlen_3210 0x40 // header 3 and 2 and 1 and 0
#define rfm22_header_cntl2_fixpklen 0x08 // Fix Packet Length. When fixpklen = 1 the packet length (pklen[7:0]) is not included in the header. When fixpklen = 0 the packet length is included in the header.
#define rfm22_header_cntl2_synclen_3 0x00 // Synchronization Word 3
#define rfm22_header_cntl2_synclen_32 0x02 // Synchronization Word 3 followed by 2
#define rfm22_header_cntl2_synclen_321 0x04 // Synchronization Word 3 followed by 2 followed by 1
#define rfm22_header_cntl2_synclen_3210 0x06 // Synchronization Word 3 followed by 2 followed by 1 followed by 0
#define rfm22_header_cntl2_prealen 0x01 // MSB of Preamble Length. See register Preamble Length.
#define RFM22_header_control2 0x33 // R/W
#define RFM22_header_cntl2_hdlen_none 0x00 // no header
#define RFM22_header_cntl2_hdlen_3 0x10 // header 3
#define RFM22_header_cntl2_hdlen_32 0x20 // header 3 and 2
#define RFM22_header_cntl2_hdlen_321 0x30 // header 3 and 2 and 1
#define RFM22_header_cntl2_hdlen_3210 0x40 // header 3 and 2 and 1 and 0
#define RFM22_header_cntl2_fixpklen 0x08 // Fix Packet Length. When fixpklen = 1 the packet length (pklen[7:0]) is not included in the header. When fixpklen = 0 the packet length is included in the header.
#define RFM22_header_cntl2_synclen_3 0x00 // Synchronization Word 3
#define RFM22_header_cntl2_synclen_32 0x02 // Synchronization Word 3 followed by 2
#define RFM22_header_cntl2_synclen_321 0x04 // Synchronization Word 3 followed by 2 followed by 1
#define RFM22_header_cntl2_synclen_3210 0x06 // Synchronization Word 3 followed by 2 followed by 1 followed by 0
#define RFM22_header_cntl2_prealen 0x01 // MSB of Preamble Length. See register Preamble Length.
#define rfm22_preamble_length 0x34 // R/W
#define RFM22_preamble_length 0x34 // R/W
#define rfm22_preamble_detection_ctrl1 0x35 // R/W
#define rfm22_pre_det_ctrl1_preath_mask 0xF8 // Number of nibbles processed during detection.
#define rfm22_pre_det_ctrl1_rssi_offset_mask 0x07 // Value added as offset to RSSI calculation. Every increment in this register results in an increment of +4 dB in the RSSI.
#define RFM22_preamble_detection_ctrl1 0x35 // R/W
#define RFM22_pre_det_ctrl1_preath_mask 0xF8 // Number of nibbles processed during detection.
#define RFM22_pre_det_ctrl1_rssi_offset_mask 0x07 // Value added as offset to RSSI calculation. Every increment in this register results in an increment of +4 dB in the RSSI.
#define rfm22_sync_word3 0x36 // R/W
#define rfm22_sync_word2 0x37 // R/W
#define rfm22_sync_word1 0x38 // R/W
#define rfm22_sync_word0 0x39 // R/W
#define RFM22_sync_word3 0x36 // R/W
#define RFM22_sync_word2 0x37 // R/W
#define RFM22_sync_word1 0x38 // R/W
#define RFM22_sync_word0 0x39 // R/W
#define rfm22_transmit_header3 0x3A // R/W
#define rfm22_transmit_header2 0x3B // R/W
#define rfm22_transmit_header1 0x3C // R/W
#define rfm22_transmit_header0 0x3D // R/W
#define RFM22_transmit_header3 0x3A // R/W
#define RFM22_transmit_header2 0x3B // R/W
#define RFM22_transmit_header1 0x3C // R/W
#define RFM22_transmit_header0 0x3D // R/W
#define rfm22_transmit_packet_length 0x3E // R/W
#define RFM22_transmit_packet_length 0x3E // R/W
#define rfm22_check_header3 0x3F // R/W
#define rfm22_check_header2 0x40 // R/W
#define rfm22_check_header1 0x41 // R/W
#define rfm22_check_header0 0x42 // R/W
#define RFM22_check_header3 0x3F // R/W
#define RFM22_check_header2 0x40 // R/W
#define RFM22_check_header1 0x41 // R/W
#define RFM22_check_header0 0x42 // R/W
#define rfm22_header_enable3 0x43 // R/W
#define rfm22_header_enable2 0x44 // R/W
#define rfm22_header_enable1 0x45 // R/W
#define rfm22_header_enable0 0x46 // R/W
#define RFM22_header_enable3 0x43 // R/W
#define RFM22_header_enable2 0x44 // R/W
#define RFM22_header_enable1 0x45 // R/W
#define RFM22_header_enable0 0x46 // R/W
#define rfm22_received_header3 0x47 // R
#define rfm22_received_header2 0x48 // R
#define rfm22_received_header1 0x49 // R
#define rfm22_received_header0 0x4A // R
#define RFM22_received_header3 0x47 // R
#define RFM22_received_header2 0x48 // R
#define RFM22_received_header1 0x49 // R
#define RFM22_received_header0 0x4A // R
#define rfm22_received_packet_length 0x4B // R
#define RFM22_received_packet_length 0x4B // R
#define rfm22_adc8_control 0x4F // R/W
#define RFM22_adc8_control 0x4F // R/W
/*
#define rfm22_analog_test_bus 0x50 // R/W
#define rfm22_digital_test_bus 0x51 // R/W
#define rfm22_tx_ramp_control 0x52 // R/W
#define rfm22_pll_tune_time 0x53 // R/W
#define RFM22_analog_test_bus 0x50 // R/W
#define RFM22_digital_test_bus 0x51 // R/W
#define RFM22_tx_ramp_control 0x52 // R/W
#define RFM22_pll_tune_time 0x53 // R/W
#define rfm22_calibration_control 0x55 // R/W
#define RFM22_calibration_control 0x55 // R/W
#define rfm22_modem_test 0x56 // R/W
#define RFM22_modem_test 0x56 // R/W
#define rfm22_chargepump_test 0x57 // R/W
#define rfm22_chargepump_current_trimming_override 0x58 // R/W
#define RFM22_chargepump_test 0x57 // R/W
#define RFM22_chargepump_current_trimming_override 0x58 // R/W
#define rfm22_divider_current_trimming 0x59 // R/W
#define RFM22_divider_current_trimming 0x59 // R/W
#define rfm22_vco_current_trimming 0x5A // R/W
#define rfm22_vco_calibration_override 0x5B // R/W
#define RFM22_vco_current_trimming 0x5A // R/W
#define RFM22_vco_calibration_override 0x5B // R/W
#define rfm22_synthersizer_test 0x5C // R/W
#define RFM22_synthersizer_test 0x5C // R/W
#define rfm22_block_enable_override1 0x5D // R/W
#define rfm22_block_enable_override2 0x5E // R/W
#define rfm22_block_enable_override3 0x5F // R/W
#define RFM22_block_enable_override1 0x5D // R/W
#define RFM22_block_enable_override2 0x5E // R/W
#define RFM22_block_enable_override3 0x5F // R/W
*/
#define rfm22_channel_filter_coeff_addr 0x60 // R/W
#define rfm22_ch_fil_coeff_ad_inv_pre_th_mask 0xF0 //
#define rfm22_ch_fil_coeff_ad_chfiladd_mask 0x0F // Channel Filter Coefficient Look-up Table Address. The address for channel filter coefficients used in the RX path.
#define RFM22_channel_filter_coeff_addr 0x60 // R/W
#define RFM22_ch_fil_coeff_ad_inv_pre_th_mask 0xF0 //
#define RFM22_ch_fil_coeff_ad_chfiladd_mask 0x0F // Channel Filter Coefficient Look-up Table Address. The address for channel filter coefficients used in the RX path.
//#define rfm22_channel_filter_coeff_value 0x61 // R/W
//#define RFM22_channel_filter_coeff_value 0x61 // R/W
#define rfm22_xtal_osc_por_ctrl 0x62 // R/W
#define rfm22_xtal_osc_por_ctrl_pwst_mask 0xE0 // Internal Power States of the Chip.
#define rfm22_xtal_osc_por_ctrl_clkhyst 0x10 // Clock Hysteresis Setting.
#define rfm22_xtal_osc_por_ctrl_enbias2x 0x08 // 2 Times Higher Bias Current Enable.
#define rfm22_xtal_osc_por_ctrl_enamp2x 0x04 // 2 Times Higher Amplification Enable.
#define rfm22_xtal_osc_por_ctrl_bufovr 0x02 // Output Buffer Enable Override.
#define rfm22_xtal_osc_por_ctrl_enbuf 0x01 // Output Buffer Enable.
#define RFM22_xtal_osc_por_ctrl 0x62 // R/W
#define RFM22_xtal_osc_por_ctrl_pwst_mask 0xE0 // Internal Power States of the Chip.
#define RFM22_xtal_osc_por_ctrl_clkhyst 0x10 // Clock Hysteresis Setting.
#define RFM22_xtal_osc_por_ctrl_enbias2x 0x08 // 2 Times Higher Bias Current Enable.
#define RFM22_xtal_osc_por_ctrl_enamp2x 0x04 // 2 Times Higher Amplification Enable.
#define RFM22_xtal_osc_por_ctrl_bufovr 0x02 // Output Buffer Enable Override.
#define RFM22_xtal_osc_por_ctrl_enbuf 0x01 // Output Buffer Enable.
/*
#define rfm22_rc_osc_coarse_calbration_override 0x63 // R/W
#define rfm22_rc_osc_fine_calbration_override 0x64 // R/W
#define RFM22_rc_osc_coarse_calbration_override 0x63 // R/W
#define RFM22_rc_osc_fine_calbration_override 0x64 // R/W
#define rfm22_ldo_control_override 0x65 // R/W
#define rfm22_ldo_level_setting 0x66 // R/W
#define RFM22_ldo_control_override 0x65 // R/W
#define RFM22_ldo_level_setting 0x66 // R/W
#define rfm22_deltasigma_adc_tuning1 0x67 // R/W
#define rfm22_deltasigma_adc_tuning2 0x68 // R/W
#define RFM22_deltasigma_adc_tuning1 0x67 // R/W
#define RFM22_deltasigma_adc_tuning2 0x68 // R/W
*/
#define rfm22_agc_override1 0x69 // R/W
#define rfm22_agc_ovr1_sgi 0x40 // AGC Loop, Set Gain Increase. If set to 0 then gain increasing will not be allowed. If set to 1 then gain increasing is allowed, default is 0.
#define rfm22_agc_ovr1_agcen 0x20 // Automatic Gain Control Enable. When this bit is set then the result of the control can be read out from bits [4:0], otherwise the gain can be controlled manually by writing into bits [4:0].
#define rfm22_agc_ovr1_lnagain 0x10 // LNA Gain Select. 0 = min gain = 5dB, 1 = max gain = 25 dB.
#define rfm22_agc_ovr1_pga_mask 0x0F // PGA Gain Override Value.
#define RFM22_agc_override1 0x69 // R/W
#define RFM22_agc_ovr1_sgi 0x40 // AGC Loop, Set Gain Increase. If set to 0 then gain increasing will not be allowed. If set to 1 then gain increasing is allowed, default is 0.
#define RFM22_agc_ovr1_agcen 0x20 // Automatic Gain Control Enable. When this bit is set then the result of the control can be read out from bits [4:0], otherwise the gain can be controlled manually by writing into bits [4:0].
#define RFM22_agc_ovr1_lnagain 0x10 // LNA Gain Select. 0 = min gain = 5dB, 1 = max gain = 25 dB.
#define RFM22_agc_ovr1_pga_mask 0x0F // PGA Gain Override Value.
//#define rfm22_agc_override2 0x6A // R/W
//#define RFM22_agc_override2 0x6A // R/W
//#define rfm22_gfsk_fir_coeff_addr 0x6B // R/W
//#define rfm22_gfsk_fir_coeff_value 0x6C // R/W
//#define RFM22_gfsk_fir_coeff_addr 0x6B // R/W
//#define RFM22_gfsk_fir_coeff_value 0x6C // R/W
#define rfm22_tx_power 0x6D // R/W
#define rfm22_tx_pwr_txpow_0 0x00 // Lowest TX power
#define rfm22_tx_pwr_txpow_1 0x01 //
#define rfm22_tx_pwr_txpow_2 0x02 //
#define rfm22_tx_pwr_txpow_3 0x03 //
#define rfm22_tx_pwr_txpow_4 0x04 //
#define rfm22_tx_pwr_txpow_5 0x05 //
#define rfm22_tx_pwr_txpow_6 0x06 //
#define rfm22_tx_pwr_txpow_7 0x07 // Highest TX power
#define rfm22_tx_pwr_lna_sw 0x08 // LNA Switch Controller. If set, lna_sw control from the digital will go high during TX modes, and low during other times. If reset, the digital control signal is low at all times.
#define rfm22_tx_pwr_papeaklvl_0 0x10 // " "
#define rfm22_tx_pwr_papeaklvl_1 0x20 // PA Peak Detect Level (direct from register). 00 = 6.5, 01 = 7, 10 = 7.5, 11 = 8, 00 = default
#define rfm22_tx_pwr_papeaken 0x40 // PA Peak Detector Enable.
#define rfm22_tx_pwr_papeakval 0x80 // PA Peak Detector Value Read Register. Reading a 1 in this register when the papeaken=1 then the PA drain voltage is too high and the match network needs adjusting for optimal efficiency.
#define RFM22_tx_power 0x6D // R/W
#define RFM22_tx_pwr_txpow_0 0x00 // Lowest TX power
#define RFM22_tx_pwr_txpow_1 0x01 //
#define RFM22_tx_pwr_txpow_2 0x02 //
#define RFM22_tx_pwr_txpow_3 0x03 //
#define RFM22_tx_pwr_txpow_4 0x04 //
#define RFM22_tx_pwr_txpow_5 0x05 //
#define RFM22_tx_pwr_txpow_6 0x06 //
#define RFM22_tx_pwr_txpow_7 0x07 // Highest TX power
#define RFM22_tx_pwr_lna_sw 0x08 // LNA Switch Controller. If set, lna_sw control from the digital will go high during TX modes, and low during other times. If reset, the digital control signal is low at all times.
#define RFM22_tx_pwr_papeaklvl_0 0x10 // " "
#define RFM22_tx_pwr_papeaklvl_1 0x20 // PA Peak Detect Level (direct from register). 00 = 6.5, 01 = 7, 10 = 7.5, 11 = 8, 00 = default
#define RFM22_tx_pwr_papeaken 0x40 // PA Peak Detector Enable.
#define RFM22_tx_pwr_papeakval 0x80 // PA Peak Detector Value Read Register. Reading a 1 in this register when the papeaken=1 then the PA drain voltage is too high and the match network needs adjusting for optimal efficiency.
#define rfm22_tx_data_rate1 0x6E // R/W
#define rfm22_tx_data_rate0 0x6F // R/W
#define RFM22_tx_data_rate1 0x6E // R/W
#define RFM22_tx_data_rate0 0x6F // R/W
#define rfm22_modulation_mode_control1 0x70 // R/W
#define rfm22_mmc1_enwhite 0x01 // Data Whitening is Enabled if this bit is set.
#define rfm22_mmc1_enmanch 0x02 // Manchester Coding is Enabled if this bit is set.
#define rfm22_mmc1_enmaninv 0x04 // Manchester Data Inversion is Enabled if this bit is set.
#define rfm22_mmc1_manppol 0x08 // Manchester Preamble Polarity (will transmit a series of 1 if set, or series of 0 if reset).
#define rfm22_mmc1_enphpwdn 0x10 // If set, the Packet Handler will be powered down when chip is in low power mode.
#define rfm22_mmc1_txdtrtscale 0x20 // This bit should be set for Data Rates below 30 kbps.
#define RFM22_modulation_mode_control1 0x70 // R/W
#define RFM22_mmc1_enwhite 0x01 // Data Whitening is Enabled if this bit is set.
#define RFM22_mmc1_enmanch 0x02 // Manchester Coding is Enabled if this bit is set.
#define RFM22_mmc1_enmaninv 0x04 // Manchester Data Inversion is Enabled if this bit is set.
#define RFM22_mmc1_manppol 0x08 // Manchester Preamble Polarity (will transmit a series of 1 if set, or series of 0 if reset).
#define RFM22_mmc1_enphpwdn 0x10 // If set, the Packet Handler will be powered down when chip is in low power mode.
#define RFM22_mmc1_txdtrtscale 0x20 // This bit should be set for Data Rates below 30 kbps.
#define rfm22_modulation_mode_control2 0x71 // R/W
#define rfm22_mmc2_modtyp_mask 0x03 // Modulation type.
#define rfm22_mmc2_modtyp_none 0x00 //
#define rfm22_mmc2_modtyp_ook 0x01 //
#define rfm22_mmc2_modtyp_fsk 0x02 //
#define rfm22_mmc2_modtyp_gfsk 0x03 //
#define rfm22_mmc2_fd 0x04 // MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation".
#define rfm22_mmc2_eninv 0x08 // Invert TX and RX Data.
#define rfm22_mmc2_dtmod_mask 0x30 // Modulation source.
#define rfm22_mmc2_dtmod_dm_gpio 0x00 //
#define rfm22_mmc2_dtmod_dm_sdi 0x10 //
#define rfm22_mmc2_dtmod_fifo 0x20 //
#define rfm22_mmc2_dtmod_pn9 0x30 //
#define rfm22_mmc2_trclk_mask 0xC0 // TX Data Clock Configuration.
#define rfm22_mmc2_trclk_clk_none 0x00 //
#define rfm22_mmc2_trclk_clk_gpio 0x40 //
#define rfm22_mmc2_trclk_clk_sdo 0x80 //
#define rfm22_mmc2_trclk_clk_nirq 0xC0 //
#define RFM22_modulation_mode_control2 0x71 // R/W
#define RFM22_mmc2_modtyp_mask 0x03 // Modulation type.
#define RFM22_mmc2_modtyp_none 0x00 //
#define RFM22_mmc2_modtyp_ook 0x01 //
#define RFM22_mmc2_modtyp_fsk 0x02 //
#define RFM22_mmc2_modtyp_gfsk 0x03 //
#define RFM22_mmc2_fd 0x04 // MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation".
#define RFM22_mmc2_eninv 0x08 // Invert TX and RX Data.
#define RFM22_mmc2_dtmod_mask 0x30 // Modulation source.
#define RFM22_mmc2_dtmod_dm_gpio 0x00 //
#define RFM22_mmc2_dtmod_dm_sdi 0x10 //
#define RFM22_mmc2_dtmod_fifo 0x20 //
#define RFM22_mmc2_dtmod_pn9 0x30 //
#define RFM22_mmc2_trclk_mask 0xC0 // TX Data Clock Configuration.
#define RFM22_mmc2_trclk_clk_none 0x00 //
#define RFM22_mmc2_trclk_clk_gpio 0x40 //
#define RFM22_mmc2_trclk_clk_sdo 0x80 //
#define RFM22_mmc2_trclk_clk_nirq 0xC0 //
#define rfm22_frequency_deviation 0x72 // R/W
#define RFM22_frequency_deviation 0x72 // R/W
#define rfm22_frequency_offset1 0x73 // R/W
#define rfm22_frequency_offset2 0x74 // R/W
#define RFM22_frequency_offset1 0x73 // R/W
#define RFM22_frequency_offset2 0x74 // R/W
#define rfm22_frequency_band_select 0x75 // R/W
#define rfm22_fb_mask 0x1F
#define rfm22_fbs_hbsel 0x20
#define rfm22_fbs_sbse 0x40
#define RFM22_frequency_band_select 0x75 // R/W
#define RFM22_fb_mask 0x1F
#define RFM22_fbs_hbsel 0x20
#define RFM22_fbs_sbse 0x40
#define rfm22_nominal_carrier_frequency1 0x76 // R/W
#define rfm22_nominal_carrier_frequency0 0x77 // R/W
#define RFM22_nominal_carrier_frequency1 0x76 // R/W
#define RFM22_nominal_carrier_frequency0 0x77 // R/W
#define rfm22_frequency_hopping_channel_select 0x79 // R/W
#define rfm22_frequency_hopping_step_size 0x7A // R/W
#define RFM22_frequency_hopping_channel_select 0x79 // R/W
#define RFM22_frequency_hopping_step_size 0x7A // R/W
#define rfm22_tx_fifo_control1 0x7C // R/W .. TX FIFO Almost Full Threshold (0 - 63)
#define rfm22_tx_fifo_control1_mask 0x3F
#define RFM22_tx_fifo_control1 0x7C // R/W .. TX FIFO Almost Full Threshold (0 - 63)
#define RFM22_tx_fifo_control1_mask 0x3F
#define rfm22_tx_fifo_control2 0x7D // R/W .. TX FIFO Almost Empty Threshold (0 - 63)
#define rfm22_tx_fifo_control2_mask 0x3F
#define RFM22_tx_fifo_control2 0x7D // R/W .. TX FIFO Almost Empty Threshold (0 - 63)
#define RFM22_tx_fifo_control2_mask 0x3F
#define rfm22_rx_fifo_control 0x7E // R/W .. RX FIFO Almost Full Threshold (0 - 63)
#define rfm22_rx_fifo_control_mask 0x3F
#define RFM22_rx_fifo_control 0x7E // R/W .. RX FIFO Almost Full Threshold (0 - 63)
#define RFM22_rx_fifo_control_mask 0x3F
#define rfm22_fifo_access 0x7F // R/W
#define RFM22_fifo_access 0x7F // R/W
// ************************************

46
flight/PipXtreme/main.c
View File

@ -276,16 +276,16 @@ void TIMER_INT_FUNC(void)
rfm22_1ms_tick(); // rf module tick
if (mode == modeNormal)
if (mode == MODE_NORMAL)
ph_1ms_tick(); // packet handler tick
if (mode == modeStreamTx || mode == modeStreamRx)
if (mode == MODE_STREAM_TX || mode == MODE_STREAM_RX)
stream_1ms_tick(); // continuous data stream tick
if (mode == modeScanSpectrum)
if (mode == MODE_SCAN_SPECTRUM)
ss_1ms_tick(); // spectrum scan tick
if (mode == modePPMTx || mode == modePPMRx)
if (mode == MODE_PPM_TX || mode == MODE_PPM_RX)
ppm_1ms_tick(); // ppm tick
if (!API_Mode)
@ -395,9 +395,9 @@ void init_RF_module(void)
switch (saved_settings.frequency_band)
{
case freqBand_434MHz:
case freqBand_868MHz:
case freqBand_915MHz:
case FREQBAND_434MHz:
case FREQBAND_868MHz:
case FREQBAND_915MHz:
i = rfm22_init(saved_settings.min_frequency_Hz, saved_settings.max_frequency_Hz, 50000);
break;
@ -586,7 +586,7 @@ int main()
second_tick_timer = 0;
second_tick = FALSE;
saved_settings.frequency_band = freqBand_UNKNOWN;
saved_settings.frequency_band = FREQBAND_UNKNOWN;
// *************
@ -700,19 +700,19 @@ int main()
// *************
// read the 434/868/915 jumper options
if (!GPIO_IN(_868MHz_PIN) && !GPIO_IN(_915MHz_PIN)) saved_settings.frequency_band = freqBand_434MHz; // 434MHz band
if (!GPIO_IN(_868MHz_PIN) && !GPIO_IN(_915MHz_PIN)) saved_settings.frequency_band = FREQBAND_434MHz; // 434MHz band
else
if (!GPIO_IN(_868MHz_PIN) && GPIO_IN(_915MHz_PIN)) saved_settings.frequency_band = freqBand_868MHz; // 868MHz band
if (!GPIO_IN(_868MHz_PIN) && GPIO_IN(_915MHz_PIN)) saved_settings.frequency_band = FREQBAND_868MHz; // 868MHz band
else
if ( GPIO_IN(_868MHz_PIN) && !GPIO_IN(_915MHz_PIN)) saved_settings.frequency_band = freqBand_915MHz; // 915MHz band
if ( GPIO_IN(_868MHz_PIN) && !GPIO_IN(_915MHz_PIN)) saved_settings.frequency_band = FREQBAND_915MHz; // 915MHz band
if (saved_settings.mode == 0xff)
saved_settings.mode = modeNormal;
saved_settings.mode = MODE_NORMAL;
// set some defaults if they are not set
switch (saved_settings.frequency_band)
{
case freqBand_434MHz:
case FREQBAND_434MHz:
if (saved_settings.min_frequency_Hz == 0xffffffff)
{
@ -749,7 +749,7 @@ int main()
}
break;
case freqBand_868MHz:
case FREQBAND_868MHz:
if (saved_settings.min_frequency_Hz == 0xffffffff)
{
saved_settings.frequency_Hz = 868000000;
@ -785,7 +785,7 @@ int main()
}
break;
case freqBand_915MHz:
case FREQBAND_915MHz:
if (saved_settings.min_frequency_Hz == 0xffffffff)
{
saved_settings.frequency_Hz = 915000000;
@ -849,10 +849,10 @@ int main()
switch (saved_settings.frequency_band)
{
case freqBand_UNKNOWN: DEBUG_PRINTF("UNKNOWN band\r\n"); break;
case freqBand_434MHz: DEBUG_PRINTF("434MHz band\r\n"); break;
case freqBand_868MHz: DEBUG_PRINTF("868MHz band\r\n"); break;
case freqBand_915MHz: DEBUG_PRINTF("915MHz band\r\n"); break;
case FREQBAND_UNKNOWN: DEBUG_PRINTF("UNKNOWN band\r\n"); break;
case FREQBAND_434MHz: DEBUG_PRINTF("434MHz band\r\n"); break;
case FREQBAND_868MHz: DEBUG_PRINTF("868MHz band\r\n"); break;
case FREQBAND_915MHz: DEBUG_PRINTF("915MHz band\r\n"); break;
}
#endif
@ -940,16 +940,16 @@ int main()
// modeTxBlankCarrierTest, // blank carrier Tx mode (for calibrating the carrier frequency say)
// modeTxSpectrumTest // pseudo random Tx data mode (for checking the Tx carrier spectrum)
if (mode == modeNormal)
if (mode == MODE_NORMAL)
ph_process(); // packet handler processing
if (mode == modeStreamTx || mode == modeStreamRx)
if (mode == MODE_STREAM_TX || mode == MODE_STREAM_RX)
stream_process(); // continuous data stream processing
if (mode == modeScanSpectrum)
if (mode == MODE_SCAN_SPECTRUM)
ss_process(); // spectrum scan processing
if (mode == modePPMTx || mode == modePPMRx)
if (mode == MODE_PPM_TX || mode == MODE_PPM_RX)
ppm_process(); // ppm processing
if (!API_Mode)

364
flight/PipXtreme/packet_handler.c
View File

@ -85,30 +85,30 @@ const uint8_t default_aes_key[AES_BLOCK_SIZE] = {0x65, 0x3b, 0x71, 0x89, 0x4a, 0
#define PACKET_TYPE_MASK 0x7f // packet type mask
enum {
packet_type_none = 0,
PACKET_TYPE_NONE = 0,
packet_type_connect = 1, // for requesting a connection
packet_type_connect_ack = 2, // ack
PACKET_TYPE_CONNECT, // for requesting a connection
PACKET_TYPE_CONNECT_ACK, // ack
packet_type_disconnect = 3, // to tell the other modem they cannot connect to us
PACKET_TYPE_DISCONNECT, // to tell the other modem they cannot connect to us
packet_type_data = 4, // data packet (packet contains user data)
packet_type_data_ack = 5, // ack
PACKET_TYPE_DATA, // data packet (packet contains user data)
PACKET_TYPE_DATA_ACK, // ack
packet_type_ready = 6, // tells the other modem we are ready to accept more data
packet_type_ready_ack = 7, // ack
PACKET_TYPE_READY, // tells the other modem we are ready to accept more data
PACKET_TYPE_READY_ACK, // ack
packet_type_notready = 8, // tells the other modem we're not ready to accept more data - we can also send user data in this packet type
packet_type_notready_ack = 9, // ack
PACKET_TYPE_NOTREADY, // tells the other modem we're not ready to accept more data - we can also send user data in this packet type
PACKET_TYPE_NOTREADY_ACK, // ack
packet_type_datarate = 10, // for changing the RF data rate
packet_type_datarate_ack = 11, // ack
PACKET_TYPE_DATARATE, // for changing the RF data rate
PACKET_TYPE_DATARATE_ACK, // ack
packet_type_ping = 12, // used to check link is still up
packet_type_pong = 13, // ack
PACKET_TYPE_PING, // used to check link is still up
PACKET_TYPE_PONG, // ack
packet_type_adjust_tx_pwr = 14, // used to ask the other modem to adjust it's tx power
packet_type_adjust_tx_pwr_ack = 15 // ack
PACKET_TYPE_ADJUST_TX_PWR, // used to ask the other modem to adjust it's tx power
PACKET_TYPE_ADJUST_TX_PWR_ACK // ack
};
#define BROADCAST_ADDR 0xffffffff
@ -148,9 +148,10 @@ typedef struct
// *****************************************************************************
// link state for each remote connection
enum { link_disconnected = 0,
link_connecting,
link_connected
enum {
LINK_DISCONNECTED = 0,
LINK_CONNECTING,
LINK_CONNECTED
};
typedef struct
@ -230,7 +231,7 @@ bool ph_connected(const int connection_index)
t_connection *conn = &connection[connection_index];
return (conn->link_state == link_connected);
return (conn->link_state == LINK_CONNECTED);
}
// *****************************************************************************
@ -283,7 +284,7 @@ int ph_startConnect(int connection_index, uint32_t sn)
t_connection *conn = &connection[connection_index];
conn->link_state = link_disconnected;
conn->link_state = LINK_DISCONNECTED;
LINK_LED_OFF;
@ -342,7 +343,7 @@ int ph_startConnect(int connection_index, uint32_t sn)
}
if (conn->serial_number != 0)
conn->link_state = link_connecting;
conn->link_state = LINK_CONNECTING;
return connection_index;
}
@ -383,7 +384,7 @@ bool ph_sendPacket(int connection_index, bool encrypt, uint8_t packet_type, bool
if (!rfm22_txReady())
return false;
if ((packet_type & PACKET_TYPE_MASK) == packet_type_none)
if ((packet_type & PACKET_TYPE_MASK) == PACKET_TYPE_NONE)
return false;
if (connection_index >= PH_MAX_CONNECTIONS)
@ -399,7 +400,7 @@ bool ph_sendPacket(int connection_index, bool encrypt, uint8_t packet_type, bool
uint8_t pack_type = packet_type & PACKET_TYPE_MASK;
bool data_packet = (pack_type == packet_type_data || pack_type == packet_type_notready);
bool data_packet = (pack_type == PACKET_TYPE_DATA || pack_type == PACKET_TYPE_NOTREADY);
// ******************
// calculate how many user data bytes we are going to add to the packet
@ -529,22 +530,22 @@ bool ph_sendPacket(int connection_index, bool encrypt, uint8_t packet_type, bool
DEBUG_PRINTF("T-PACK ");
switch (pack_type)
{
case packet_type_none: DEBUG_PRINTF("none"); break;
case packet_type_connect: DEBUG_PRINTF("connect"); break;
case packet_type_connect_ack: DEBUG_PRINTF("connect_ack"); break;
case packet_type_disconnect: DEBUG_PRINTF("disconnect"); break;
case packet_type_data: DEBUG_PRINTF("data"); break;
case packet_type_data_ack: DEBUG_PRINTF("data_ack"); break;
case packet_type_ready: DEBUG_PRINTF("ready"); break;
case packet_type_ready_ack: DEBUG_PRINTF("ready_ack"); break;
case packet_type_notready: DEBUG_PRINTF("notready"); break;
case packet_type_notready_ack: DEBUG_PRINTF("notready_ack"); break;
case packet_type_datarate: DEBUG_PRINTF("datarate"); break;
case packet_type_datarate_ack: DEBUG_PRINTF("datarate_ack"); break;
case packet_type_ping: DEBUG_PRINTF("ping"); break;
case packet_type_pong: DEBUG_PRINTF("pong"); break;
case packet_type_adjust_tx_pwr: DEBUG_PRINTF("packet_type_adjust_tx_pwr"); break;
case packet_type_adjust_tx_pwr_ack: DEBUG_PRINTF("packet_type_adjust_tx_pwr_ack"); break;
case PACKET_TYPE_NONE: DEBUG_PRINTF("none"); break;
case PACKET_TYPE_CONNECT: DEBUG_PRINTF("connect"); break;
case PACKET_TYPE_CONNECT_ACK: DEBUG_PRINTF("connect_ack"); break;
case PACKET_TYPE_DISCONNECT: DEBUG_PRINTF("disconnect"); break;
case PACKET_TYPE_DATA: DEBUG_PRINTF("data"); break;
case PACKET_TYPE_DATA_ACK: DEBUG_PRINTF("data_ack"); break;
case PACKET_TYPE_READY: DEBUG_PRINTF("ready"); break;
case PACKET_TYPE_READY_ACK: DEBUG_PRINTF("ready_ack"); break;
case PACKET_TYPE_NOTREADY: DEBUG_PRINTF("notready"); break;
case PACKET_TYPE_NOTREADY_ACK: DEBUG_PRINTF("notready_ack"); break;
case PACKET_TYPE_DATARATE: DEBUG_PRINTF("datarate"); break;
case PACKET_TYPE_DATARATE_ACK: DEBUG_PRINTF("datarate_ack"); break;
case PACKET_TYPE_PING: DEBUG_PRINTF("ping"); break;
case PACKET_TYPE_PONG: DEBUG_PRINTF("pong"); break;
case PACKET_TYPE_ADJUST_TX_PWR: DEBUG_PRINTF("PACKET_TYPE_ADJUST_TX_PWR"); break;
case PACKET_TYPE_ADJUST_TX_PWR_ACK: DEBUG_PRINTF("PACKET_TYPE_ADJUST_TX_PWR_ACK"); break;
default: DEBUG_PRINTF("UNKNOWN [%d]", pack_type); break;
}
DEBUG_PRINTF(" tseq:%d rseq:%d", conn->tx_sequence, conn->rx_sequence);
@ -558,28 +559,28 @@ bool ph_sendPacket(int connection_index, bool encrypt, uint8_t packet_type, bool
switch (pack_type)
{
case packet_type_connect:
case packet_type_disconnect:
case packet_type_data:
case packet_type_ready:
case packet_type_notready:
case packet_type_datarate:
case packet_type_ping:
case packet_type_adjust_tx_pwr:
case PACKET_TYPE_CONNECT:
case PACKET_TYPE_DISCONNECT:
case PACKET_TYPE_DATA:
case PACKET_TYPE_READY:
case PACKET_TYPE_NOTREADY:
case PACKET_TYPE_DATARATE:
case PACKET_TYPE_PING:
case PACKET_TYPE_ADJUST_TX_PWR:
if (conn->tx_retry_counter < 0xffff)
conn->tx_retry_counter++;
break;
case packet_type_connect_ack:
case packet_type_data_ack:
case packet_type_ready_ack:
case packet_type_notready_ack:
case packet_type_datarate_ack:
case packet_type_pong:
case packet_type_adjust_tx_pwr_ack:
case PACKET_TYPE_CONNECT_ACK:
case PACKET_TYPE_DATA_ACK:
case PACKET_TYPE_READY_ACK:
case PACKET_TYPE_NOTREADY_ACK:
case PACKET_TYPE_DATARATE_ACK:
case PACKET_TYPE_PONG:
case PACKET_TYPE_ADJUST_TX_PWR_ACK:
break;
case packet_type_none:
case PACKET_TYPE_NONE:
break;
}
@ -627,22 +628,22 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
DEBUG_PRINTF("R-PACK ");
switch (packet_type)
{
case packet_type_none: DEBUG_PRINTF("none"); break;
case packet_type_connect: DEBUG_PRINTF("connect"); break;
case packet_type_connect_ack: DEBUG_PRINTF("connect_ack"); break;
case packet_type_disconnect: DEBUG_PRINTF("disconnect"); break;
case packet_type_data: DEBUG_PRINTF("data"); break;
case packet_type_data_ack: DEBUG_PRINTF("data_ack"); break;
case packet_type_ready: DEBUG_PRINTF("ready"); break;
case packet_type_ready_ack: DEBUG_PRINTF("ready_ack"); break;
case packet_type_notready: DEBUG_PRINTF("notready"); break;
case packet_type_notready_ack: DEBUG_PRINTF("notready_ack"); break;
case packet_type_datarate: DEBUG_PRINTF("datarate"); break;
case packet_type_datarate_ack: DEBUG_PRINTF("datarate_ack"); break;
case packet_type_ping: DEBUG_PRINTF("ping"); break;
case packet_type_pong: DEBUG_PRINTF("pong"); break;
case packet_type_adjust_tx_pwr: DEBUG_PRINTF("packet_type_adjust_tx_pwr"); break;
case packet_type_adjust_tx_pwr_ack: DEBUG_PRINTF("packet_type_adjust_tx_pwr_ack"); break;
case PACKET_TYPE_NONE: DEBUG_PRINTF("none"); break;
case PACKET_TYPE_CONNECT: DEBUG_PRINTF("connect"); break;
case PACKET_TYPE_CONNECT_ACK: DEBUG_PRINTF("connect_ack"); break;
case PACKET_TYPE_DISCONNECT: DEBUG_PRINTF("disconnect"); break;
case PACKET_TYPE_DATA: DEBUG_PRINTF("data"); break;
case PACKET_TYPE_DATA_ACK: DEBUG_PRINTF("data_ack"); break;
case PACKET_TYPE_READY: DEBUG_PRINTF("ready"); break;
case PACKET_TYPE_READY_ACK: DEBUG_PRINTF("ready_ack"); break;
case PACKET_TYPE_NOTREADY: DEBUG_PRINTF("notready"); break;
case PACKET_TYPE_NOTREADY_ACK: DEBUG_PRINTF("notready_ack"); break;
case PACKET_TYPE_DATARATE: DEBUG_PRINTF("datarate"); break;
case PACKET_TYPE_DATARATE_ACK: DEBUG_PRINTF("datarate_ack"); break;
case PACKET_TYPE_PING: DEBUG_PRINTF("ping"); break;
case PACKET_TYPE_PONG: DEBUG_PRINTF("pong"); break;
case PACKET_TYPE_ADJUST_TX_PWR: DEBUG_PRINTF("PACKET_TYPE_ADJUST_TX_PWR"); break;
case PACKET_TYPE_ADJUST_TX_PWR_ACK: DEBUG_PRINTF("PACKET_TYPE_ADJUST_TX_PWR_ACK"); break;
default: DEBUG_PRINTF("UNKNOWN [%d]", packet_type); break;
}
DEBUG_PRINTF(" tseq-%d rseq-%d", header->tx_seq, header->rx_seq);
@ -692,9 +693,9 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
if (connection_index >= PH_MAX_CONNECTIONS)
{ // the packet is from an unknown source ID (unknown modem)
if (packet_type != packet_type_none)
if (packet_type != PACKET_TYPE_NONE)
{ // send a disconnect packet back to them
// ph_sendPacket(-1, was_encrypted, packet_type_disconnect, true);
// ph_sendPacket(-1, was_encrypted, PACKET_TYPE_DISCONNECT, true);
}
return;
@ -721,17 +722,17 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
// ***********
if (packet_type == packet_type_none)
if (packet_type == PACKET_TYPE_NONE)
return;
if (packet_type == packet_type_disconnect)
if (packet_type == PACKET_TYPE_DISCONNECT)
{
conn->link_state = link_disconnected;
conn->link_state = LINK_DISCONNECTED;
LINK_LED_OFF;
return;
}
if (packet_type == packet_type_connect)
if (packet_type == PACKET_TYPE_CONNECT)
{
LINK_LED_ON;
@ -763,10 +764,10 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
conn->not_ready_timer = -1;
conn->link_state = link_connected;
conn->link_state = LINK_CONNECTED;
// send an ack back
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_connect_ack, true))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_CONNECT_ACK, true))
{
conn->tx_packet_timer = 0;
}
@ -774,11 +775,11 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_connect_ack)
if (packet_type == PACKET_TYPE_CONNECT_ACK)
{
LINK_LED_ON;
if (conn->link_state != link_connecting)
if (conn->link_state != LINK_CONNECTING)
{ // reset the link
ph_set_remote_serial_number(connection_index, conn->serial_number);
return;
@ -809,7 +810,7 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
conn->not_ready_timer = -1;
conn->link_state = link_connected;
conn->link_state = LINK_CONNECTED;
return;
}
@ -817,9 +818,9 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
if (conn->link_state == link_connecting)
if (conn->link_state == LINK_CONNECTING)
{ // we are trying to connect to them .. reply with a connect request packet
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_connect, true))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_CONNECT, true))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len * 4 + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len * 4;
@ -827,7 +828,7 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (conn->link_state != link_connected)
if (conn->link_state != LINK_CONNECTED)
{ // they have sent us a packet when we are not in a connected state - start a connection
ph_startConnect(connection_index, conn->serial_number);
return;
@ -839,18 +840,18 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
// check to make sure it's a wanted packet type
switch (packet_type)
{
case packet_type_data:
case packet_type_data_ack:
case packet_type_ready:
case packet_type_ready_ack:
case packet_type_notready:
case packet_type_notready_ack:
case packet_type_datarate:
case packet_type_datarate_ack:
case packet_type_ping:
case packet_type_pong:
case packet_type_adjust_tx_pwr:
case packet_type_adjust_tx_pwr_ack:
case PACKET_TYPE_DATA:
case PACKET_TYPE_DATA_ACK:
case PACKET_TYPE_READY:
case PACKET_TYPE_READY_ACK:
case PACKET_TYPE_NOTREADY:
case PACKET_TYPE_NOTREADY_ACK:
case PACKET_TYPE_DATARATE:
case PACKET_TYPE_DATARATE_ACK:
case PACKET_TYPE_PING:
case PACKET_TYPE_PONG:
case PACKET_TYPE_ADJUST_TX_PWR:
case PACKET_TYPE_ADJUST_TX_PWR_ACK:
break;
default:
return;
@ -877,9 +878,9 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
if (packet_type == packet_type_data || packet_type == packet_type_data_ack)
if (packet_type == PACKET_TYPE_DATA || packet_type == PACKET_TYPE_DATA_ACK)
{
if (packet_type == packet_type_data && header->tx_seq == conn->rx_sequence)
if (packet_type == PACKET_TYPE_DATA && header->tx_seq == conn->rx_sequence)
{ // the packet number is what we expected
if (data_size > 0)
@ -903,9 +904,9 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
if (size >= 200 || (conn->ready_to_send_timer >= 10 && size > 0) || (conn->tx_sequence_data_size > 0 && size > 0))
{ // send data
uint8_t pack_type = packet_type_data;
uint8_t pack_type = PACKET_TYPE_DATA;
if (conn->rx_not_ready_mode)
pack_type = packet_type_notready;
pack_type = PACKET_TYPE_NOTREADY;
if (ph_sendPacket(connection_index, conn->send_encrypted, pack_type, true))
{
@ -915,11 +916,11 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
}
}
if (packet_type == packet_type_data)
if (packet_type == PACKET_TYPE_DATA)
{ // send an ack back
uint8_t pack_type = packet_type_data_ack;
uint8_t pack_type = PACKET_TYPE_DATA_ACK;
if (conn->rx_not_ready_mode)
pack_type = packet_type_notready_ack;
pack_type = PACKET_TYPE_NOTREADY_ACK;
if (ph_sendPacket(connection_index, conn->send_encrypted, pack_type, true))
{
@ -932,12 +933,12 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_ready)
if (packet_type == PACKET_TYPE_READY)
{
conn->not_ready_timer = -1; // stop timer
// send an ack back
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_ready_ack, true))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_READY_ACK, true))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len * 4 + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len * 4;
@ -947,13 +948,13 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_ready_ack)
if (packet_type == PACKET_TYPE_READY_ACK)
{
conn->rx_not_ready_mode = false;
return;
}
if (packet_type == packet_type_notready)
if (packet_type == PACKET_TYPE_NOTREADY)
{
// conn->not_ready_timer = 0; // start timer
@ -980,7 +981,7 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
}
// send an ack back
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_notready_ack, true))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_NOTREADY_ACK, true))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len * 4 + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len * 4;
@ -990,14 +991,14 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_notready_ack)
if (packet_type == PACKET_TYPE_NOTREADY_ACK)
{
return;
}
if (packet_type == packet_type_ping)
if (packet_type == PACKET_TYPE_PING)
{ // send a pong back
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_pong, true))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_PONG, true))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len;
@ -1005,7 +1006,7 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_pong)
if (packet_type == PACKET_TYPE_PONG)
{
if (conn->pinging)
{
@ -1015,10 +1016,10 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_datarate)
if (packet_type == PACKET_TYPE_DATARATE)
{
// send an ack back
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_datarate_ack, true))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_DATARATE_ACK, true))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len;
@ -1026,15 +1027,15 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_datarate_ack)
if (packet_type == PACKET_TYPE_DATARATE_ACK)
{
return;
}
if (packet_type == packet_type_adjust_tx_pwr)
if (packet_type == PACKET_TYPE_ADJUST_TX_PWR)
{
// send an ack back
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_adjust_tx_pwr_ack, true))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_ADJUST_TX_PWR_ACK, true))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len;
@ -1042,7 +1043,7 @@ void ph_processPacket2(bool was_encrypted, t_packet_header *header, uint8_t *dat
return;
}
if (packet_type == packet_type_adjust_tx_pwr_ack)
if (packet_type == PACKET_TYPE_ADJUST_TX_PWR_ACK)
{
return;
}
@ -1244,7 +1245,7 @@ void ph_processLinks(int connection_index)
switch (conn->link_state)
{
case link_disconnected:
case LINK_DISCONNECTED:
if (!canTx)
{
conn->tx_packet_timer = 0;
@ -1262,7 +1263,7 @@ void ph_processLinks(int connection_index)
break;
case link_connecting:
case LINK_CONNECTING:
if (!canTx)
{
conn->tx_packet_timer = 0;
@ -1272,7 +1273,7 @@ void ph_processLinks(int connection_index)
if (!timeToRetry)
break;
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_connect, false))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_CONNECT, false))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len * 4 + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len * 4;
@ -1281,7 +1282,7 @@ void ph_processLinks(int connection_index)
break;
case link_connected:
case LINK_CONNECTED:
if (!canTx)
{
conn->tx_packet_timer = 0;
@ -1299,7 +1300,7 @@ void ph_processLinks(int connection_index)
if (conn->pinging)
{ // we are trying to ping them
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_ping, false))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_PING, false))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len * 4 + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len * 4;
@ -1311,7 +1312,7 @@ void ph_processLinks(int connection_index)
if (fast_ping) ping_time = conn->fast_ping_time;
if (conn->tx_packet_timer >= ping_time)
{ // start pinging
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_ping, false))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_PING, false))
{
conn->ping_time = 8000 + (random32 % 100) * 10;
conn->fast_ping_time = 600 + (random32 % 50) * 10;
@ -1330,7 +1331,7 @@ void ph_processLinks(int connection_index)
uint16_t size = fifoBuf_getFree(&conn->rx_fifo_buffer);
if (size >= conn->rx_fifo_buffer.buf_size / 6)
{ // leave 'rx not ready' mode
if (ph_sendPacket(connection_index, conn->send_encrypted, packet_type_ready, false))
if (ph_sendPacket(connection_index, conn->send_encrypted, PACKET_TYPE_READY, false))
{
conn->tx_packet_timer = 0;
conn->tx_retry_time = conn->tx_retry_time_slot_len + (random32 % conn->tx_retry_time_slots) * conn->tx_retry_time_slot_len;
@ -1355,9 +1356,9 @@ void ph_processLinks(int connection_index)
if (size >= 200 || (conn->ready_to_send_timer >= 10 && size > 0) || (conn->tx_sequence_data_size > 0 && size > 0))
{ // send data
uint8_t pack_type = packet_type_data;
uint8_t pack_type = PACKET_TYPE_DATA;
if (conn->rx_not_ready_mode)
pack_type = packet_type_notready;
pack_type = PACKET_TYPE_NOTREADY;
if (ph_sendPacket(connection_index, conn->send_encrypted, pack_type, false))
{
@ -1373,7 +1374,7 @@ void ph_processLinks(int connection_index)
break;
default: // we should never end up here - maybe we should do a reboot?
conn->link_state = link_disconnected;
conn->link_state = LINK_DISCONNECTED;
/*
// disable all interrupts
PIOS_IRQ_Disable();
@ -1528,57 +1529,59 @@ void ph_set_remote_encryption(int connection_index, bool enabled, const void *ke
}
// *****************************************************************************
// can be called from an interrupt if you wish
// can be called from an interrupt if you wish.
// call this once every ms
void ph_1ms_tick(void)
{ // call this once every ms
{
if (saved_settings.mode == MODE_NORMAL)
{
// help randomize the encryptor cbc bytes
register uint32_t *cbc = (uint32_t *)&enc_cbc;
for (int i = 0; i < sizeof(enc_cbc) / 4; i++)
{
random32 = updateCRC32(random32, 0xff);
*cbc++ ^= random32;
}
// help randomize the encryptor cbc bytes
register uint32_t *cbc = (uint32_t *)&enc_cbc;
for (int i = 0; i < sizeof(enc_cbc) / 4; i++)
{
random32 = updateCRC32(random32, 0xff);
*cbc++ ^= random32;
}
for (int i = 0; i < PH_MAX_CONNECTIONS; i++)
{
t_connection *conn = &connection[i];
for (int i = 0; i < PH_MAX_CONNECTIONS; i++)
{
t_connection *conn = &connection[i];
if (conn->tx_packet_timer < 0xffff)
conn->tx_packet_timer++;
if (conn->tx_packet_timer < 0xffff)
conn->tx_packet_timer++;
if (conn->link_state == LINK_CONNECTED)
{ // we are connected
if (conn->link_state == link_connected)
{ // we are connected
if (conn->ready_to_send_timer >= 0 && conn->ready_to_send_timer < 0x7fff)
conn->ready_to_send_timer++;
if (conn->ready_to_send_timer >= 0 && conn->ready_to_send_timer < 0x7fff)
conn->ready_to_send_timer++;
if (conn->not_ready_timer >= 0 && conn->not_ready_timer < 0x7fffffff)
conn->not_ready_timer++;
if (conn->not_ready_timer >= 0 && conn->not_ready_timer < 0x7fffffff)
conn->not_ready_timer++;
if (conn->data_speed_timer < 0xffff)
{
if (++conn->data_speed_timer >= 1000)
{ // 1 second gone by
conn->data_speed_timer = 0;
conn->tx_data_speed = (conn->tx_data_speed + conn->tx_data_speed_count) >> 1;
conn->tx_data_speed_count = 0;
conn->rx_data_speed = (conn->rx_data_speed + conn->rx_data_speed_count) >> 1;
conn->rx_data_speed_count = 0;
}
}
}
else
{ // we are not connected
if (conn->data_speed_timer) conn->data_speed_timer = 0;
if (conn->tx_data_speed_count) conn->tx_data_speed_count = 0;
if (conn->tx_data_speed) conn->tx_data_speed = 0;
if (conn->rx_data_speed_count) conn->rx_data_speed_count = 0;
if (conn->rx_data_speed) conn->rx_data_speed = 0;
}
}
if (conn->data_speed_timer < 0xffff)
{
if (++conn->data_speed_timer >= 1000)
{ // 1 second gone by
conn->data_speed_timer = 0;
conn->tx_data_speed = (conn->tx_data_speed + conn->tx_data_speed_count) >> 1;
conn->tx_data_speed_count = 0;
conn->rx_data_speed = (conn->rx_data_speed + conn->rx_data_speed_count) >> 1;
conn->rx_data_speed_count = 0;
}
}
}
else
{ // we are not connected
if (conn->data_speed_timer) conn->data_speed_timer = 0;
if (conn->tx_data_speed_count) conn->tx_data_speed_count = 0;
if (conn->tx_data_speed) conn->tx_data_speed = 0;
if (conn->rx_data_speed_count) conn->rx_data_speed_count = 0;
if (conn->rx_data_speed) conn->rx_data_speed = 0;
}
}
}
}
// *****************************************************************************
@ -1586,10 +1589,17 @@ void ph_1ms_tick(void)
void ph_process(void)
{
ph_processRxPacket();
if (saved_settings.mode == MODE_NORMAL)
{
ph_processRxPacket();
for (int i = 0; i < PH_MAX_CONNECTIONS; i++)
ph_processLinks(i);
for (int i = 0; i < PH_MAX_CONNECTIONS; i++)
ph_processLinks(i);
}
else
{
}
}
// *****************************************************************************
@ -1616,7 +1626,7 @@ void ph_init(uint32_t our_sn, uint32_t datarate_bps, uint8_t tx_power)
fifoBuf_init(&conn->tx_fifo_buffer, conn->tx_buffer, PH_FIFO_BUFFER_SIZE);
fifoBuf_init(&conn->rx_fifo_buffer, conn->rx_buffer, PH_FIFO_BUFFER_SIZE);
conn->link_state = link_disconnected;
conn->link_state = LINK_DISCONNECTED;
conn->tx_packet_timer = 0;

17
flight/PipXtreme/ppm.c
View File

@ -36,9 +36,17 @@
// *************************************************************
// can be called from an interrupt if you wish
// call this once every ms
void ppm_1ms_tick(void)
{ // call this once every ms
{
if (saved_settings.mode == MODE_PPM_TX)
{
}
else
if (saved_settings.mode == MODE_PPM_RX)
{
}
}
// *************************************************************
@ -46,6 +54,13 @@ void ppm_1ms_tick(void)
void ppm_process(void)
{
if (saved_settings.mode == MODE_PPM_TX)
{
}
else
if (saved_settings.mode == MODE_PPM_RX)
{
}
}
// *************************************************************

382
flight/PipXtreme/rfm22b.c
View File

@ -91,14 +91,14 @@
// ************************************
// the default TX power level
#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_0 // +1dBm ... 1.25mW
//#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_1 // +2dBm ... 1.6mW
//#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_2 // +5dBm ... 3.16mW
//#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_3 // +8dBm ... 6.3mW
//#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_4 // +11dBm .. 12.6mW
//#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_5 // +14dBm .. 25mW
//#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_6 // +17dBm .. 50mW
//#define RFM22_DEFAULT_RF_POWER rfm22_tx_pwr_txpow_7 // +20dBm .. 100mW
#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_0 // +1dBm ... 1.25mW
//#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_1 // +2dBm ... 1.6mW
//#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_2 // +5dBm ... 3.16mW
//#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_3 // +8dBm ... 6.3mW
//#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_4 // +11dBm .. 12.6mW
//#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_5 // +14dBm .. 25mW
//#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_6 // +17dBm .. 50mW
//#define RFM22_DEFAULT_RF_POWER RFM22_tx_pwr_txpow_7 // +20dBm .. 100mW
// ************************************
// the default RF datarate
@ -407,7 +407,7 @@ void rfm22_setFreqCalibration(uint8_t value)
exec_using_spi = TRUE;
#endif
rfm22_write(rfm22_xtal_osc_load_cap, osc_load_cap);
rfm22_write(RFM22_xtal_osc_load_cap, osc_load_cap);
#if defined(RFM22_EXT_INT_USE)
exec_using_spi = FALSE;
@ -426,14 +426,14 @@ void rfm22_setTxPower(uint8_t tx_pwr)
{
switch (tx_pwr)
{
case 0: tx_power = rfm22_tx_pwr_txpow_0; break; // +1dBm ... 1.25mW
case 1: tx_power = rfm22_tx_pwr_txpow_1; break; // +2dBm ... 1.6mW
case 2: tx_power = rfm22_tx_pwr_txpow_2; break; // +5dBm ... 3.16mW
case 3: tx_power = rfm22_tx_pwr_txpow_3; break; // +8dBm ... 6.3mW
case 4: tx_power = rfm22_tx_pwr_txpow_4; break; // +11dBm .. 12.6mW
case 5: tx_power = rfm22_tx_pwr_txpow_5; break; // +14dBm .. 25mW
case 6: tx_power = rfm22_tx_pwr_txpow_6; break; // +17dBm .. 50mW
case 7: tx_power = rfm22_tx_pwr_txpow_7; break; // +20dBm .. 100mW
case 0: tx_power = RFM22_tx_pwr_txpow_0; break; // +1dBm ... 1.25mW
case 1: tx_power = RFM22_tx_pwr_txpow_1; break; // +2dBm ... 1.6mW
case 2: tx_power = RFM22_tx_pwr_txpow_2; break; // +5dBm ... 3.16mW
case 3: tx_power = RFM22_tx_pwr_txpow_3; break; // +8dBm ... 6.3mW
case 4: tx_power = RFM22_tx_pwr_txpow_4; break; // +11dBm .. 12.6mW
case 5: tx_power = RFM22_tx_pwr_txpow_5; break; // +14dBm .. 25mW
case 6: tx_power = RFM22_tx_pwr_txpow_6; break; // +17dBm .. 50mW
case 7: tx_power = RFM22_tx_pwr_txpow_7; break; // +20dBm .. 100mW
default: break;
}
}
@ -472,20 +472,20 @@ void rfm22_setNominalCarrierFrequency(uint32_t frequency_hz)
fb -= 24;
if (hbsel > 1)
fb |= rfm22_fbs_hbsel;
fb |= RFM22_fbs_hbsel;
fb |= rfm22_fbs_sbse; // is this the RX LO polarity?
fb |= RFM22_fbs_sbse; // is this the RX LO polarity?
frequency_step_size = 156.25f * hbsel;
rfm22_write(rfm22_frequency_hopping_channel_select, frequency_hop_channel); // frequency hoppping channel (0-255)
rfm22_write(RFM22_frequency_hopping_channel_select, frequency_hop_channel); // frequency hoppping channel (0-255)
rfm22_write(rfm22_frequency_offset1, 0); // no frequency offset
rfm22_write(rfm22_frequency_offset2, 0); // no frequency offset
rfm22_write(RFM22_frequency_offset1, 0); // no frequency offset
rfm22_write(RFM22_frequency_offset2, 0); // no frequency offset
rfm22_write(rfm22_frequency_band_select, fb); // set the carrier frequency
rfm22_write(rfm22_nominal_carrier_frequency1, fc >> 8); // " "
rfm22_write(rfm22_nominal_carrier_frequency0, fc & 0xff); // " "
rfm22_write(RFM22_frequency_band_select, fb); // set the carrier frequency
rfm22_write(RFM22_nominal_carrier_frequency1, fc >> 8); // " "
rfm22_write(RFM22_nominal_carrier_frequency0, fc & 0xff); // " "
// *******
@ -512,7 +512,7 @@ float rfm22_getFrequencyStepSize(void)
void rfm22_setFreqHopChannel(uint8_t channel)
{ // set the frequency hopping channel
frequency_hop_channel = channel;
rfm22_write(rfm22_frequency_hopping_channel_select, frequency_hop_channel);
rfm22_write(RFM22_frequency_hopping_channel_select, frequency_hop_channel);
}
uint8_t rfm22_freqHopChannel(void)
@ -586,35 +586,35 @@ void rfm22_setDatarate(uint32_t datarate_bps)
rfm22_write(0x72, reg_72[lookup_index]); // rfm22_frequency_deviation
rfm22_write(rfm22_ook_counter_value1, 0x00);
rfm22_write(rfm22_ook_counter_value2, 0x00);
rfm22_write(RFM22_ook_counter_value1, 0x00);
rfm22_write(RFM22_ook_counter_value2, 0x00);
// ********************************
// calculate the TX register values
/*
uint16_t fd = frequency_deviation / 625;
uint8_t mmc1 = rfm22_mmc1_enphpwdn | rfm22_mmc1_manppol;
uint8_t mmc1 = RFM22_mmc1_enphpwdn | RFM22_mmc1_manppol;
uint16_t txdr;
if (datarate_bps < 30000)
{
txdr = (datarate_bps * 20972) / 10000;
mmc1 |= rfm22_mmc1_txdtrtscale;
mmc1 |= RFM22_mmc1_txdtrtscale;
}
else
txdr = (datarate_bps * 6553) / 100000;
uint8_t mmc2 = rfm22_mmc2_dtmod_fifo | rfm22_mmc2_modtyp_gfsk; // FIFO mode, GFSK
// uint8_t mmc2 = rfm22_mmc2_dtmod_pn9 | rfm22_mmc2_modtyp_gfsk; // PN9 mode, GFSK .. TX TEST MODE
if (fd & 0x100) mmc2 |= rfm22_mmc2_fd;
uint8_t mmc2 = RFM22_mmc2_dtmod_fifo | RFM22_mmc2_modtyp_gfsk; // FIFO mode, GFSK
// uint8_t mmc2 = RFM22_mmc2_dtmod_pn9 | RFM22_mmc2_modtyp_gfsk; // PN9 mode, GFSK .. TX TEST MODE
if (fd & 0x100) mmc2 |= RFM22_mmc2_fd;
rfm22_write(rfm22_frequency_deviation, fd); // set the TX peak frequency deviation
rfm22_write(RFM22_frequency_deviation, fd); // set the TX peak frequency deviation
rfm22_write(rfm22_modulation_mode_control1, mmc1);
rfm22_write(rfm22_modulation_mode_control2, mmc2);
rfm22_write(RFM22_modulation_mode_control1, mmc1);
rfm22_write(RFM22_modulation_mode_control2, mmc2);
rfm22_write(rfm22_tx_data_rate1, txdr >> 8); // set the TX data rate
rfm22_write(rfm22_tx_data_rate0, txdr); // " "
rfm22_write(RFM22_tx_data_rate1, txdr >> 8); // set the TX data rate
rfm22_write(RFM22_tx_data_rate0, txdr); // " "
*/
// ********************************
// determine a clear channel time
@ -667,12 +667,12 @@ void rfm22_reenableRx(void)
RX_LED_OFF;
// disable the receiver
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton); // READY mode
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon); // TUNE mode
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton); // READY mode
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon); // TUNE mode
// clear FIFOs
rfm22_write(rfm22_op_and_func_ctrl2, rfm22_opfc2_ffclrrx | rfm22_opfc2_ffclrtx);
rfm22_write(rfm22_op_and_func_ctrl2, 0x00);
rfm22_write(RFM22_op_and_func_ctrl2, RFM22_opfc2_ffclrrx | RFM22_opfc2_ffclrtx);
rfm22_write(RFM22_op_and_func_ctrl2, 0x00);
rx_buffer_wr = 0; // empty the rx buffer
@ -683,8 +683,8 @@ void rfm22_reenableRx(void)
rf_mode = RX_WAIT_PREAMBLE_MODE;
// enable the receiver
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton | rfm22_opfc1_rxon);
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon | rfm22_opfc1_rxon);
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton | RFM22_opfc1_rxon);
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon | RFM22_opfc1_rxon);
#if defined(RFM22_EXT_INT_USE)
exec_using_spi = FALSE;
@ -698,22 +698,22 @@ void rfm22_setRxMode(void)
#endif
// disable interrupts
rfm22_write(rfm22_interrupt_enable1, 0x00);
rfm22_write(rfm22_interrupt_enable2, 0x00);
rfm22_write(RFM22_interrupt_enable1, 0x00);
rfm22_write(RFM22_interrupt_enable2, 0x00);
// disable the receiver and transmitter
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton); // READY mode
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon); // TUNE mode
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton); // READY mode
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon); // TUNE mode
RX_LED_OFF;
TX_LED_OFF;
// rfm22_write(rfm22_rx_fifo_control, RX_FIFO_HI_WATERMARK); // RX FIFO Almost Full Threshold (0 - 63)
// rfm22_write(RFM22_rx_fifo_control, RX_FIFO_HI_WATERMARK); // RX FIFO Almost Full Threshold (0 - 63)
if (rf_mode == TX_CARRIER_MODE || rf_mode == TX_PN_MODE)
{ // FIFO mode, GFSK modulation
uint8_t fd_bit = rfm22_read(rfm22_modulation_mode_control2) & rfm22_mmc2_fd;
rfm22_write(rfm22_modulation_mode_control2, fd_bit | rfm22_mmc2_dtmod_fifo | rfm22_mmc2_modtyp_gfsk);
uint8_t fd_bit = rfm22_read(RFM22_modulation_mode_control2) & RFM22_mmc2_fd;
rfm22_write(RFM22_modulation_mode_control2, fd_bit | RFM22_mmc2_dtmod_fifo | RFM22_mmc2_modtyp_gfsk);
}
rx_buffer_wr = 0; // empty the rx buffer
@ -725,20 +725,20 @@ void rfm22_setRxMode(void)
rf_mode = RX_WAIT_PREAMBLE_MODE;
// enable RX interrupts
rfm22_write(rfm22_interrupt_enable1, rfm22_ie1_encrcerror | rfm22_ie1_enpkvalid | rfm22_ie1_enrxffafull | rfm22_ie1_enfferr);
rfm22_write(rfm22_interrupt_enable2, rfm22_ie2_enpreainval | rfm22_ie2_enpreaval | rfm22_ie2_enswdet);
rfm22_write(RFM22_interrupt_enable1, RFM22_ie1_encrcerror | RFM22_ie1_enpkvalid | RFM22_ie1_enrxffafull | RFM22_ie1_enfferr);
rfm22_write(RFM22_interrupt_enable2, RFM22_ie2_enpreainval | RFM22_ie2_enpreaval | RFM22_ie2_enswdet);
// read interrupt status - clear interrupts
rfm22_read(rfm22_interrupt_status1);
rfm22_read(rfm22_interrupt_status2);
rfm22_read(RFM22_interrupt_status1);
rfm22_read(RFM22_interrupt_status2);
// clear FIFOs
rfm22_write(rfm22_op_and_func_ctrl2, rfm22_opfc2_ffclrrx | rfm22_opfc2_ffclrtx);
rfm22_write(rfm22_op_and_func_ctrl2, 0x00);
rfm22_write(RFM22_op_and_func_ctrl2, RFM22_opfc2_ffclrrx | RFM22_opfc2_ffclrtx);
rfm22_write(RFM22_op_and_func_ctrl2, 0x00);
// enable the receiver
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton | rfm22_opfc1_rxon);
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon | rfm22_opfc1_rxon);
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton | RFM22_opfc1_rxon);
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon | RFM22_opfc1_rxon);
#if defined(RFM22_EXT_INT_USE)
exec_using_spi = FALSE;
@ -763,38 +763,38 @@ void rfm22_setTxMode(uint8_t mode)
// *******************
// disable interrupts
rfm22_write(rfm22_interrupt_enable1, 0x00);
rfm22_write(rfm22_interrupt_enable2, 0x00);
rfm22_write(RFM22_interrupt_enable1, 0x00);
rfm22_write(RFM22_interrupt_enable2, 0x00);
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton); // READY mode
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon); // TUNE mode
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton); // READY mode
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon); // TUNE mode
RX_LED_OFF;
uint8_t fd_bit = rfm22_read(rfm22_modulation_mode_control2) & rfm22_mmc2_fd;
uint8_t fd_bit = rfm22_read(RFM22_modulation_mode_control2) & RFM22_mmc2_fd;
if (mode == TX_CARRIER_MODE)
{ // blank carrier mode - for testing
rfm22_write(rfm22_tx_power, rfm22_tx_pwr_papeaken | rfm22_tx_pwr_papeaklvl_0 | rfm22_tx_pwr_lna_sw | rfm22_tx_pwr_txpow_0); // tx power +1dBm ... 1.25mW
rfm22_write(rfm22_modulation_mode_control2, fd_bit | rfm22_mmc2_dtmod_pn9 | rfm22_mmc2_modtyp_none); // FIFO mode, Blank carrier
rfm22_write(RFM22_tx_power, RFM22_tx_pwr_papeaken | RFM22_tx_pwr_papeaklvl_0 | RFM22_tx_pwr_lna_sw | RFM22_tx_pwr_txpow_0); // tx power +1dBm ... 1.25mW
rfm22_write(RFM22_modulation_mode_control2, fd_bit | RFM22_mmc2_dtmod_pn9 | RFM22_mmc2_modtyp_none); // FIFO mode, Blank carrier
}
else
if (mode == TX_PN_MODE)
{ // psuedo random data carrier mode - for testing
rfm22_write(rfm22_tx_power, rfm22_tx_pwr_papeaken | rfm22_tx_pwr_papeaklvl_0 | rfm22_tx_pwr_lna_sw | rfm22_tx_pwr_txpow_0); // tx power +1dBm ... 1.25mW
rfm22_write(rfm22_modulation_mode_control2, fd_bit | rfm22_mmc2_dtmod_pn9 | rfm22_mmc2_modtyp_gfsk); // FIFO mode, PN9 carrier
rfm22_write(RFM22_tx_power, RFM22_tx_pwr_papeaken | RFM22_tx_pwr_papeaklvl_0 | RFM22_tx_pwr_lna_sw | RFM22_tx_pwr_txpow_0); // tx power +1dBm ... 1.25mW
rfm22_write(RFM22_modulation_mode_control2, fd_bit | RFM22_mmc2_dtmod_pn9 | RFM22_mmc2_modtyp_gfsk); // FIFO mode, PN9 carrier
}
else
{ // data transmission
// rfm22_write(rfm22_tx_power, rfm22_tx_pwr_lna_sw | tx_power); // set the tx power
rfm22_write(rfm22_tx_power, rfm22_tx_pwr_papeaken | rfm22_tx_pwr_papeaklvl_0 | rfm22_tx_pwr_lna_sw | tx_power); // set the tx power
rfm22_write(rfm22_modulation_mode_control2, fd_bit | rfm22_mmc2_dtmod_fifo | rfm22_mmc2_modtyp_gfsk); // FIFO mode, GFSK modulation
// rfm22_write(RFM22_tx_power, RFM22_tx_pwr_lna_sw | tx_power); // set the tx power
rfm22_write(RFM22_tx_power, RFM22_tx_pwr_papeaken | RFM22_tx_pwr_papeaklvl_0 | RFM22_tx_pwr_lna_sw | tx_power); // set the tx power
rfm22_write(RFM22_modulation_mode_control2, fd_bit | RFM22_mmc2_dtmod_fifo | RFM22_mmc2_modtyp_gfsk); // FIFO mode, GFSK modulation
}
// rfm22_write(0x72, reg_72[lookup_index]); // rfm22_frequency_deviation
// clear FIFOs
rfm22_write(rfm22_op_and_func_ctrl2, rfm22_opfc2_ffclrrx | rfm22_opfc2_ffclrtx);
rfm22_write(rfm22_op_and_func_ctrl2, 0x00);
rfm22_write(RFM22_op_and_func_ctrl2, RFM22_opfc2_ffclrrx | RFM22_opfc2_ffclrtx);
rfm22_write(RFM22_op_and_func_ctrl2, 0x00);
// *******************
// add some data to the chips TX FIFO before enabling the transmitter
@ -806,13 +806,13 @@ void rfm22_setTxMode(uint8_t mode)
register uint16_t rd = tx_data_rd;
// set the total number of data bytes we are going to transmit
rfm22_write(rfm22_transmit_packet_length, tx_data_wr);
rfm22_write(RFM22_transmit_packet_length, tx_data_wr);
register uint16_t num = tx_data_wr - rd;
if (num > (FIFO_SIZE - 1)) num = FIFO_SIZE - 1;
// add some data
rfm22_startBurstWrite(rfm22_fifo_access);
rfm22_startBurstWrite(RFM22_fifo_access);
for (register uint16_t i = num; i > 0; i--)
rfm22_burstWrite(tx_data_addr[rd++]);
rfm22_endBurstWrite();
@ -832,16 +832,16 @@ void rfm22_setTxMode(uint8_t mode)
rf_mode = mode;
// enable TX interrupts
// rfm22_write(rfm22_interrupt_enable1, rfm22_ie1_enpksent | rfm22_ie1_entxffaem | rfm22_ie1_enfferr);
rfm22_write(rfm22_interrupt_enable1, rfm22_ie1_enpksent | rfm22_ie1_entxffaem);
// rfm22_write(RFM22_interrupt_enable1, RFM22_ie1_enpksent | RFM22_ie1_entxffaem | RFM22_ie1_enfferr);
rfm22_write(RFM22_interrupt_enable1, RFM22_ie1_enpksent | RFM22_ie1_entxffaem);
// read interrupt status - clear interrupts
rfm22_read(rfm22_interrupt_status1);
rfm22_read(rfm22_interrupt_status2);
rfm22_read(RFM22_interrupt_status1);
rfm22_read(RFM22_interrupt_status2);
// enable the transmitter
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton | rfm22_opfc1_txon);
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon | rfm22_opfc1_txon);
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton | RFM22_opfc1_txon);
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon | RFM22_opfc1_txon);
TX_LED_ON;
@ -874,7 +874,7 @@ void rfm22_processRxInt(void)
register uint8_t int_stat1 = int_status1;
register uint8_t int_stat2 = int_status2;
if (int_stat2 & rfm22_is2_ipreaval)
if (int_stat2 & RFM22_is2_ipreaval)
{ // Valid preamble detected
if (rf_mode == RX_WAIT_PREAMBLE_MODE)
@ -890,7 +890,7 @@ void rfm22_processRxInt(void)
}
}
/* else
if (int_stat2 & rfm22_is2_ipreainval)
if (int_stat2 & RFM22_is2_ipreainval)
{ // Invalid preamble detected
if (rf_mode == RX_WAIT_SYNC_MODE)
@ -909,7 +909,7 @@ void rfm22_processRxInt(void)
}
}
*/
if (int_stat2 & rfm22_is2_iswdet)
if (int_stat2 & RFM22_is2_iswdet)
{ // Sync word detected
STOPWATCH_reset(); // reset timer
@ -921,8 +921,8 @@ void rfm22_processRxInt(void)
RX_LED_ON;
// read the 10-bit signed afc correction value
afc_correction = (uint16_t)rfm22_read(rfm22_afc_correction_read) << 8; // bits 9 to 2
afc_correction |= (uint16_t)rfm22_read(rfm22_ook_counter_value1) & 0x00c0; // bits 1 & 0
afc_correction = (uint16_t)rfm22_read(RFM22_afc_correction_read) << 8; // bits 9 to 2
afc_correction |= (uint16_t)rfm22_read(RFM22_ook_counter_value1) & 0x00c0; // bits 1 & 0
afc_correction >>= 6;
afc_correction_Hz = (int32_t)(frequency_step_size * afc_correction + 0.5f); // convert the afc value to Hz
@ -937,14 +937,14 @@ void rfm22_processRxInt(void)
}
}
if (int_stat1 & rfm22_is1_irxffafull)
if (int_stat1 & RFM22_is1_irxffafull)
{ // RX FIFO almost full, it needs emptying
if (rf_mode == RX_DATA_MODE)
{ // read data from the rf chips FIFO buffer
rfm22_int_timer = 0; // reset the timer
register uint16_t len = rfm22_read(rfm22_received_packet_length); // read the total length of the packet data
register uint16_t len = rfm22_read(RFM22_received_packet_length); // read the total length of the packet data
register uint16_t wr = rx_buffer_wr;
@ -960,7 +960,7 @@ void rfm22_processRxInt(void)
return;
}
if (((wr + RX_FIFO_HI_WATERMARK) >= len) && !(int_stat1 & rfm22_is1_ipkvalid))
if (((wr + RX_FIFO_HI_WATERMARK) >= len) && !(int_stat1 & RFM22_is1_ipkvalid))
{ // some kind of error in the RF module
#if defined(RFM22_DEBUG) && !defined(RFM22_EXT_INT_USE)
DEBUG_PRINTF(" r_size_error2");
@ -973,7 +973,7 @@ void rfm22_processRxInt(void)
}
// fetch the rx'ed data from the rf chips RX FIFO
rfm22_startBurstRead(rfm22_fifo_access);
rfm22_startBurstRead(RFM22_fifo_access);
for (register uint16_t i = RX_FIFO_HI_WATERMARK; i > 0; i--)
{
register uint8_t b = rfm22_burstRead(); // read a byte from the rf modules RX FIFO buffer
@ -991,14 +991,14 @@ void rfm22_processRxInt(void)
}
else
{ // just clear the RX FIFO
rfm22_startBurstRead(rfm22_fifo_access);
rfm22_startBurstRead(RFM22_fifo_access);
for (register uint16_t i = RX_FIFO_HI_WATERMARK; i > 0; i--)
rfm22_burstRead(); // read a byte from the rf modules RX FIFO buffer
rfm22_endBurstRead();
}
}
if (int_stat1 & rfm22_is1_icrerror)
if (int_stat1 & RFM22_is1_icrerror)
{ // CRC error .. discard the received data
if (rf_mode == RX_DATA_MODE)
@ -1016,19 +1016,19 @@ void rfm22_processRxInt(void)
}
}
// if (int_stat2 & rfm22_is2_irssi)
// if (int_stat2 & RFM22_is2_irssi)
// { // RSSI level is >= the set threshold
// }
// if (device_status & rfm22_ds_rxffem)
// if (device_status & RFM22_ds_rxffem)
// { // RX FIFO empty
// }
// if (device_status & rfm22_ds_headerr)
// if (device_status & RFM22_ds_headerr)
// { // Header check error
// }
if (int_stat1 & rfm22_is1_ipkvalid)
if (int_stat1 & RFM22_is1_ipkvalid)
{ // Valid packet received
if (rf_mode == RX_DATA_MODE)
@ -1036,17 +1036,17 @@ void rfm22_processRxInt(void)
rfm22_int_timer = 0; // reset the timer
// disable the receiver
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton); // READY mode
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon); // TUNE mode
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton); // READY mode
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon); // TUNE mode
register uint16_t len = rfm22_read(rfm22_received_packet_length); // read the total length of the packet data
register uint16_t len = rfm22_read(RFM22_received_packet_length); // read the total length of the packet data
register uint16_t wr = rx_buffer_wr;
if (wr < len)
{ // their must still be data in the RX FIFO we need to get
rfm22_startBurstRead(rfm22_fifo_access);
rfm22_startBurstRead(RFM22_fifo_access);
while (wr < len)
{
if (wr >= sizeof(rx_buffer)) break;
@ -1104,7 +1104,7 @@ void rfm22_processTxInt(void)
// register uint8_t int_stat2 = int_status2;
/*
if (int_stat1 & rfm22_is1_ifferr)
if (int_stat1 & RFM22_is1_ifferr)
{ // FIFO underflow/overflow error
rfm22_setRxMode();
tx_data_addr = NULL;
@ -1113,7 +1113,7 @@ void rfm22_processTxInt(void)
}
*/
if (int_stat1 & rfm22_is1_ixtffaem)
if (int_stat1 & RFM22_is1_ixtffaem)
{ // TX FIFO almost empty, it needs filling up
#if defined(RFM22_DEBUG) && !defined(RFM22_EXT_INT_USE)
@ -1134,7 +1134,7 @@ void rfm22_processTxInt(void)
num = FIFO_SIZE - TX_FIFO_LO_WATERMARK - 1;
// top-up the rf chips TX FIFO buffer
rfm22_startBurstWrite(rfm22_fifo_access);
rfm22_startBurstWrite(RFM22_fifo_access);
for (register uint16_t i = num; i > 0; i--)
rfm22_burstWrite(tx_data_addr[rd++]);
rfm22_endBurstWrite();
@ -1152,7 +1152,7 @@ void rfm22_processTxInt(void)
}
}
if (int_stat1 & rfm22_is1_ipksent)
if (int_stat1 & RFM22_is1_ipksent)
{ // Packet has been sent
#if defined(RFM22_DEBUG) && !defined(RFM22_EXT_INT_USE)
DEBUG_PRINTF(" T_Sent");
@ -1169,7 +1169,7 @@ void rfm22_processTxInt(void)
}
}
// if (int_stat1 & rfm22_is1_itxffafull)
// if (int_stat1 & RFM22_is1_itxffafull)
// { // TX FIFO almost full, it needs to be transmitted
// }
}
@ -1193,18 +1193,18 @@ void rfm22_processInt(void)
// read the RF modules current status registers
// read device status register
device_status = rfm22_read(rfm22_device_status);
device_status = rfm22_read(RFM22_device_status);
// read ezmac status register
ezmac_status = rfm22_read(rfm22_ezmac_status);
ezmac_status = rfm22_read(RFM22_ezmac_status);
// read interrupt status registers - clears the interrupt line
int_status1 = rfm22_read(rfm22_interrupt_status1);
int_status2 = rfm22_read(rfm22_interrupt_status2);
int_status1 = rfm22_read(RFM22_interrupt_status1);
int_status2 = rfm22_read(RFM22_interrupt_status2);
if (rf_mode != TX_DATA_MODE && rf_mode != TX_CARRIER_MODE && rf_mode != TX_PN_MODE)
{
rssi = rfm22_read(rfm22_rssi); // read rx signal strength .. 45 = -100dBm, 205 = -20dBm
rssi = rfm22_read(RFM22_rssi); // read rx signal strength .. 45 = -100dBm, 205 = -20dBm
rssi_dBm = ((int16_t)rssi / 2) - 122; // convert to dBm
// calibrate the RSSI value (rf bandwidth appears to affect it)
@ -1213,10 +1213,10 @@ void rfm22_processInt(void)
}
else
{
tx_pwr = rfm22_read(rfm22_tx_power); // read the tx power register
tx_pwr = rfm22_read(RFM22_tx_power); // read the tx power register
}
if (int_status2 & rfm22_is2_ipor)
if (int_status2 & RFM22_is2_ipor)
{ // the RF module has gone and done a reset - we need to re-initialize the rf module
initialized = FALSE;
power_on_reset = TRUE;
@ -1231,11 +1231,11 @@ void rfm22_processInt(void)
{
DEBUG_PRINTF("%02x %02x %02x %02x %dC", device_status, int_status1, int_status2, ezmac_status, temperature_reg);
if ((device_status & rfm22_ds_cps_mask) == rfm22_ds_cps_rx)
if ((device_status & RFM22_ds_cps_mask) == RFM22_ds_cps_rx)
DEBUG_PRINTF(" %ddBm", rssi_dBm); // rx mode
else
if ((device_status & rfm22_ds_cps_mask) == rfm22_ds_cps_tx)
DEBUG_PRINTF(" %s", (tx_pwr & rfm22_tx_pwr_papeakval) ? "ANT_MISMATCH" : "ant_ok"); // tx mode
if ((device_status & RFM22_ds_cps_mask) == RFM22_ds_cps_tx)
DEBUG_PRINTF(" %s", (tx_pwr & RFM22_tx_pwr_papeakval) ? "ANT_MISMATCH" : "ant_ok"); // tx mode
debug_outputted = true;
@ -1249,14 +1249,14 @@ void rfm22_processInt(void)
// ********************************
// read the ADC - temperature sensor .. this can only be used in IDLE mode
/*
if (!(rfm22_read(rfm22_adc_config) & rfm22_ac_adcstartbusy))
if (!(rfm22_read(RFM22_adc_config) & RFM22_ac_adcstartbusy))
{ // the ADC has completed it's conversion
// read the ADC sample
temperature_reg = (int16_t)rfm22_read(rfm22_adc_value) * 0.5f - 64;
temperature_reg = (int16_t)rfm22_read(RFM22_adc_value) * 0.5f - 64;
// start a new ADC conversion
rfm22_write(rfm22_adc_config, adc_config | rfm22_ac_adcstartbusy);
rfm22_write(RFM22_adc_config, adc_config | RFM22_ac_adcstartbusy);
#if defined(RFM22_DEBUG) && !defined(RFM22_EXT_INT_USE)
DEBUG_PRINTF(", %dC", temperature_reg);
@ -1274,7 +1274,7 @@ void rfm22_processInt(void)
case RX_WAIT_SYNC_MODE:
case RX_DATA_MODE:
if (device_status & (rfm22_ds_ffunfl | rfm22_ds_ffovfl))
if (device_status & (RFM22_ds_ffunfl | RFM22_ds_ffovfl))
{ // FIFO under/over flow error
#if defined(RFM22_DEBUG) && !defined(RFM22_EXT_INT_USE)
@ -1309,7 +1309,7 @@ void rfm22_processInt(void)
break;
}
if ((device_status & rfm22_ds_cps_mask) != rfm22_ds_cps_rx)
if ((device_status & RFM22_ds_cps_mask) != RFM22_ds_cps_rx)
{ // the rf module is not in rx mode
if (timer_ms >= 100)
{
@ -1331,7 +1331,7 @@ void rfm22_processInt(void)
case TX_DATA_MODE:
if (device_status & (rfm22_ds_ffunfl | rfm22_ds_ffovfl))
if (device_status & (RFM22_ds_ffunfl | RFM22_ds_ffovfl))
{ // FIFO under/over flow error
#if defined(RFM22_DEBUG) && !defined(RFM22_EXT_INT_USE)
@ -1352,7 +1352,7 @@ void rfm22_processInt(void)
break;
}
if ((device_status & rfm22_ds_cps_mask) != rfm22_ds_cps_tx)
if ((device_status & RFM22_ds_cps_mask) != RFM22_ds_cps_tx)
{ // the rf module is not in tx mode
if (timer_ms >= 100)
{
@ -1702,7 +1702,7 @@ int rfm22_init(uint32_t min_frequency_hz, uint32_t max_frequency_hz, uint32_t fr
// ****************
// software reset the RF chip .. following procedure according to Si4x3x Errata (rev. B)
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_swres); // software reset the radio
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_swres); // software reset the radio
PIOS_DELAY_WaitmS(26); // wait 26ms
@ -1711,22 +1711,22 @@ int rfm22_init(uint32_t min_frequency_hz, uint32_t max_frequency_hz, uint32_t fr
PIOS_DELAY_WaitmS(1); // wait 1ms
// read the status registers
int_status1 = rfm22_read(rfm22_interrupt_status1);
int_status2 = rfm22_read(rfm22_interrupt_status2);
if (int_status2 & rfm22_is2_ichiprdy) break;
int_status1 = rfm22_read(RFM22_interrupt_status1);
int_status2 = rfm22_read(RFM22_interrupt_status2);
if (int_status2 & RFM22_is2_ichiprdy) break;
}
// ****************
// read status - clears interrupt
device_status = rfm22_read(rfm22_device_status);
int_status1 = rfm22_read(rfm22_interrupt_status1);
int_status2 = rfm22_read(rfm22_interrupt_status2);
ezmac_status = rfm22_read(rfm22_ezmac_status);
device_status = rfm22_read(RFM22_device_status);
int_status1 = rfm22_read(RFM22_interrupt_status1);
int_status2 = rfm22_read(RFM22_interrupt_status2);
ezmac_status = rfm22_read(RFM22_ezmac_status);
// disable all interrupts
rfm22_write(rfm22_interrupt_enable1, 0x00);
rfm22_write(rfm22_interrupt_enable2, 0x00);
rfm22_write(RFM22_interrupt_enable1, 0x00);
rfm22_write(RFM22_interrupt_enable2, 0x00);
// ****************
@ -1810,14 +1810,14 @@ int rfm22_init(uint32_t min_frequency_hz, uint32_t max_frequency_hz, uint32_t fr
// ****************
// read the RF chip ID bytes
device_type = rfm22_read(rfm22_device_type) & rfm22_dt_mask; // read the device type
device_type = rfm22_read(RFM22_device_type) & RFM22_dt_mask; // read the device type
#if defined(RFM22_DEBUG)
DEBUG_PRINTF("rf device type: %d\r\n", device_type);
#endif
if (device_type != 0x08)
return -1; // incorrect RF module type
device_version = rfm22_read(rfm22_device_version) & rfm22_dv_mask; // read the device version
device_version = rfm22_read(RFM22_device_version) & RFM22_dv_mask; // read the device version
#if defined(RFM22_DEBUG)
DEBUG_PRINTF("rf device version: %d\r\n", device_version);
#endif
@ -1831,7 +1831,7 @@ int rfm22_init(uint32_t min_frequency_hz, uint32_t max_frequency_hz, uint32_t fr
// ****************
// disable Low Duty Cycle Mode
rfm22_write(rfm22_op_and_func_ctrl2, 0x00);
rfm22_write(RFM22_op_and_func_ctrl2, 0x00);
// calibrate our RF module to be exactly on frequency .. different for every module
osc_load_cap = OSC_LOAD_CAP; // default
@ -1842,96 +1842,96 @@ int rfm22_init(uint32_t min_frequency_hz, uint32_t max_frequency_hz, uint32_t fr
if (serial_number_crc32 == 0x9F6393C1) osc_load_cap = OSC_LOAD_CAP_3;
else
if (serial_number_crc32 == 0x994ECD31) osc_load_cap = OSC_LOAD_CAP_4;
*/ rfm22_write(rfm22_xtal_osc_load_cap, osc_load_cap);
*/ rfm22_write(RFM22_xtal_osc_load_cap, osc_load_cap);
rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_xton); // READY mode
// rfm22_write(rfm22_op_and_func_ctrl1, rfm22_opfc1_pllon); // TUNE mode
rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_xton); // READY mode
// rfm22_write(RFM22_op_and_func_ctrl1, RFM22_opfc1_pllon); // TUNE mode
// choose the 3 GPIO pin functions
rfm22_write(rfm22_io_port_config, rfm22_io_port_default); // GPIO port use default value
rfm22_write(rfm22_gpio0_config, rfm22_gpio0_config_drv3 | rfm22_gpio0_config_txstate); // GPIO0 = TX State (to control RF Switch)
rfm22_write(rfm22_gpio1_config, rfm22_gpio1_config_drv3 | rfm22_gpio1_config_rxstate); // GPIO1 = RX State (to control RF Switch)
rfm22_write(rfm22_gpio2_config, rfm22_gpio2_config_drv3 | rfm22_gpio2_config_cca); // GPIO2 = Clear Channel Assessment
rfm22_write(RFM22_io_port_config, RFM22_io_port_default); // GPIO port use default value
rfm22_write(RFM22_gpio0_config, RFM22_gpio0_config_drv3 | RFM22_gpio0_config_txstate); // GPIO0 = TX State (to control RF Switch)
rfm22_write(RFM22_gpio1_config, RFM22_gpio1_config_drv3 | RFM22_gpio1_config_rxstate); // GPIO1 = RX State (to control RF Switch)
rfm22_write(RFM22_gpio2_config, RFM22_gpio2_config_drv3 | RFM22_gpio2_config_cca); // GPIO2 = Clear Channel Assessment
// set the RF datarate
rfm22_setDatarate(RFM22_DEFAULT_RF_DATARATE);
// Enable data whitening
// uint8_t txdtrtscale_bit = rfm22_read(rfm22_modulation_mode_control1) & rfm22_mmc1_txdtrtscale;
// rfm22_write(rfm22_modulation_mode_control1, txdtrtscale_bit | rfm22_mmc1_enwhite);
// uint8_t txdtrtscale_bit = rfm22_read(RFM22_modulation_mode_control1) & RFM22_mmc1_txdtrtscale;
// rfm22_write(RFM22_modulation_mode_control1, txdtrtscale_bit | RFM22_mmc1_enwhite);
// FIFO mode, GFSK modulation
uint8_t fd_bit = rfm22_read(rfm22_modulation_mode_control2) & rfm22_mmc2_fd;
rfm22_write(rfm22_modulation_mode_control2, rfm22_mmc2_trclk_clk_none | rfm22_mmc2_dtmod_fifo | fd_bit | rfm22_mmc2_modtyp_gfsk);
uint8_t fd_bit = rfm22_read(RFM22_modulation_mode_control2) & RFM22_mmc2_fd;
rfm22_write(RFM22_modulation_mode_control2, RFM22_mmc2_trclk_clk_none | RFM22_mmc2_dtmod_fifo | fd_bit | RFM22_mmc2_modtyp_gfsk);
rfm22_write(rfm22_cpu_output_clk, rfm22_coc_1MHz); // 1MHz clock output
rfm22_write(RFM22_cpu_output_clk, RFM22_coc_1MHz); // 1MHz clock output
// setup to read the internal temperature sensor
adc_config = rfm22_ac_adcsel_temp_sensor | rfm22_ac_adcref_bg; // ADC used to sample the temperature sensor
rfm22_write(rfm22_adc_config, adc_config); //
rfm22_write(rfm22_adc_sensor_amp_offset, 0); // adc offset
rfm22_write(rfm22_temp_sensor_calib, rfm22_tsc_tsrange0 | rfm22_tsc_entsoffs); // temp sensor calibration .. –40C to +64C 0.5C resolution
rfm22_write(rfm22_temp_value_offset, 0); // temp sensor offset
rfm22_write(rfm22_adc_config, adc_config | rfm22_ac_adcstartbusy); // start an ADC conversion
adc_config = RFM22_ac_adcsel_temp_sensor | RFM22_ac_adcref_bg; // ADC used to sample the temperature sensor
rfm22_write(RFM22_adc_config, adc_config); //
rfm22_write(RFM22_adc_sensor_amp_offset, 0); // adc offset
rfm22_write(RFM22_temp_sensor_calib, RFM22_tsc_tsrange0 | RFM22_tsc_entsoffs); // temp sensor calibration .. –40C to +64C 0.5C resolution
rfm22_write(RFM22_temp_value_offset, 0); // temp sensor offset
rfm22_write(RFM22_adc_config, adc_config | RFM22_ac_adcstartbusy); // start an ADC conversion
rfm22_write(rfm22_rssi_threshold_clear_chan_indicator, (-80 + 122) * 2); // set the RSSI threshold interrupt to about -80dBm
rfm22_write(RFM22_rssi_threshold_clear_chan_indicator, (-80 + 122) * 2); // set the RSSI threshold interrupt to about -80dBm
// enable the internal Tx & Rx packet handlers (with CRC)
// rfm22_write(rfm22_data_access_control, rfm22_dac_enpacrx | rfm22_dac_enpactx | rfm22_dac_encrc | rfm22_dac_crc_crc16);
// rfm22_write(RFM22_data_access_control, RFM22_dac_enpacrx | RFM22_dac_enpactx | RFM22_dac_encrc | RFM22_dac_crc_crc16);
// enable the internal Tx & Rx packet handlers (without CRC)
rfm22_write(rfm22_data_access_control, rfm22_dac_enpacrx | rfm22_dac_enpactx);
rfm22_write(RFM22_data_access_control, RFM22_dac_enpacrx | RFM22_dac_enpactx);
rfm22_write(rfm22_preamble_length, TX_PREAMBLE_NIBBLES); // x-nibbles tx preamble
rfm22_write(rfm22_preamble_detection_ctrl1, RX_PREAMBLE_NIBBLES << 3); // x-nibbles rx preamble detection
rfm22_write(RFM22_preamble_length, TX_PREAMBLE_NIBBLES); // x-nibbles tx preamble
rfm22_write(RFM22_preamble_detection_ctrl1, RX_PREAMBLE_NIBBLES << 3); // x-nibbles rx preamble detection
rfm22_write(rfm22_header_control1, rfm22_header_cntl1_bcen_none | rfm22_header_cntl1_hdch_none); // header control - we are not using the header
rfm22_write(rfm22_header_control2, rfm22_header_cntl2_hdlen_none | rfm22_header_cntl2_synclen_3210 | ((TX_PREAMBLE_NIBBLES >> 8) & 0x01)); // no header bytes, synchronization word length 3, 2, 1 & 0 used, packet length included in header.
rfm22_write(RFM22_header_control1, RFM22_header_cntl1_bcen_none | RFM22_header_cntl1_hdch_none); // header control - we are not using the header
rfm22_write(RFM22_header_control2, RFM22_header_cntl2_hdlen_none | RFM22_header_cntl2_synclen_3210 | ((TX_PREAMBLE_NIBBLES >> 8) & 0x01)); // no header bytes, synchronization word length 3, 2, 1 & 0 used, packet length included in header.
rfm22_write(rfm22_sync_word3, SYNC_BYTE_1); // sync word
rfm22_write(rfm22_sync_word2, SYNC_BYTE_2); //
rfm22_write(rfm22_sync_word1, SYNC_BYTE_3); //
rfm22_write(rfm22_sync_word0, SYNC_BYTE_4); //
rfm22_write(RFM22_sync_word3, SYNC_BYTE_1); // sync word
rfm22_write(RFM22_sync_word2, SYNC_BYTE_2); //
rfm22_write(RFM22_sync_word1, SYNC_BYTE_3); //
rfm22_write(RFM22_sync_word0, SYNC_BYTE_4); //
/*
rfm22_write(rfm22_transmit_header3, 'p'); // set tx header
rfm22_write(rfm22_transmit_header2, 'i'); //
rfm22_write(rfm22_transmit_header1, 'p'); //
rfm22_write(rfm22_transmit_header0, ' '); //
rfm22_write(RFM22_transmit_header3, 'p'); // set tx header
rfm22_write(RFM22_transmit_header2, 'i'); //
rfm22_write(RFM22_transmit_header1, 'p'); //
rfm22_write(RFM22_transmit_header0, ' '); //
rfm22_write(rfm22_check_header3, 'p'); // set expected rx header
rfm22_write(rfm22_check_header2, 'i'); //
rfm22_write(rfm22_check_header1, 'p'); //
rfm22_write(rfm22_check_header0, ' '); //
rfm22_write(RFM22_check_header3, 'p'); // set expected rx header
rfm22_write(RFM22_check_header2, 'i'); //
rfm22_write(RFM22_check_header1, 'p'); //
rfm22_write(RFM22_check_header0, ' '); //
// all the bits to be checked
rfm22_write(rfm22_header_enable3, 0xff);
rfm22_write(rfm22_header_enable2, 0xff);
rfm22_write(rfm22_header_enable1, 0xff);
rfm22_write(rfm22_header_enable0, 0xff);
rfm22_write(RFM22_header_enable3, 0xff);
rfm22_write(RFM22_header_enable2, 0xff);
rfm22_write(RFM22_header_enable1, 0xff);
rfm22_write(RFM22_header_enable0, 0xff);
*/ // no bits to be checked
rfm22_write(rfm22_header_enable3, 0x00);
rfm22_write(rfm22_header_enable2, 0x00);
rfm22_write(rfm22_header_enable1, 0x00);
rfm22_write(rfm22_header_enable0, 0x00);
rfm22_write(RFM22_header_enable3, 0x00);
rfm22_write(RFM22_header_enable2, 0x00);
rfm22_write(RFM22_header_enable1, 0x00);
rfm22_write(RFM22_header_enable0, 0x00);
// rfm22_write(rfm22_modem_test, 0x01);
// rfm22_write(RFM22_modem_test, 0x01);
rfm22_write(rfm22_agc_override1, rfm22_agc_ovr1_agcen);
// rfm22_write(rfm22_agc_override1, rfm22_agc_ovr1_sgi | rfm22_agc_ovr1_agcen);
rfm22_write(RFM22_agc_override1, RFM22_agc_ovr1_agcen);
// rfm22_write(RFM22_agc_override1, RFM22_agc_ovr1_sgi | RFM22_agc_ovr1_agcen);
rfm22_write(rfm22_frequency_hopping_step_size, frequency_hop_step_size_reg); // set frequency hopping channel step size (multiples of 10kHz)
rfm22_write(RFM22_frequency_hopping_step_size, frequency_hop_step_size_reg); // set frequency hopping channel step size (multiples of 10kHz)
rfm22_setNominalCarrierFrequency((min_frequency_hz + max_frequency_hz) / 2); // set our nominal carrier frequency
rfm22_write(rfm22_tx_power, rfm22_tx_pwr_papeaken | rfm22_tx_pwr_papeaklvl_0 | rfm22_tx_pwr_lna_sw | tx_power); // set the tx power
rfm22_write(RFM22_tx_power, RFM22_tx_pwr_papeaken | RFM22_tx_pwr_papeaklvl_0 | RFM22_tx_pwr_lna_sw | tx_power); // set the tx power
// rfm22_write(rfm22_vco_current_trimming, 0x7f);
// rfm22_write(rfm22_vco_calibration_override, 0x40);
// rfm22_write(rfm22_chargepump_current_trimming_override, 0x80);
// rfm22_write(RFM22_vco_current_trimming, 0x7f);
// rfm22_write(RFM22_vco_calibration_override, 0x40);
// rfm22_write(RFM22_chargepump_current_trimming_override, 0x80);
rfm22_write(rfm22_tx_fifo_control1, TX_FIFO_HI_WATERMARK); // TX FIFO Almost Full Threshold (0 - 63)
rfm22_write(rfm22_tx_fifo_control2, TX_FIFO_LO_WATERMARK); // TX FIFO Almost Empty Threshold (0 - 63)
rfm22_write(RFM22_tx_fifo_control1, TX_FIFO_HI_WATERMARK); // TX FIFO Almost Full Threshold (0 - 63)
rfm22_write(RFM22_tx_fifo_control2, TX_FIFO_LO_WATERMARK); // TX FIFO Almost Empty Threshold (0 - 63)
rfm22_write(rfm22_rx_fifo_control, RX_FIFO_HI_WATERMARK); // RX FIFO Almost Full Threshold (0 - 63)
rfm22_write(RFM22_rx_fifo_control, RX_FIFO_HI_WATERMARK); // RX FIFO Almost Full Threshold (0 - 63)
#if defined(RFM22_EXT_INT_USE)
// Enable RF module external interrupt

4
flight/PipXtreme/saved_settings.c
View File

@ -295,11 +295,11 @@ void saved_settings_init(void)
memset((void *)&saved_settings, 0xff, sizeof(t_saved_settings));
saved_settings.mode = modeNormal;
saved_settings.mode = MODE_NORMAL;
saved_settings.destination_id = 0;
saved_settings.frequency_band = freqBand_UNKNOWN;
saved_settings.frequency_band = FREQBAND_UNKNOWN;
saved_settings.rf_xtal_cap = 0x7f;

11
flight/PipXtreme/scan_spectrum.c
View File

@ -35,10 +35,14 @@
#endif
// *************************************************************
// can be called from an interrupt if you wish
// can be called from an interrupt if you wish.
// call this once every ms
void ss_1ms_tick(void)
{ // call this once every ms
{
if (saved_settings.mode == MODE_SCAN_SPECTRUM)
{
}
}
// *************************************************************
@ -46,6 +50,9 @@ void ss_1ms_tick(void)
void ss_process(void)
{
if (saved_settings.mode == MODE_SCAN_SPECTRUM)
{
}
}
// *************************************************************

17
flight/PipXtreme/stream.c
View File

@ -39,9 +39,17 @@
// *************************************************************
// can be called from an interrupt if you wish
// call this once every ms
void stream_1ms_tick(void)
{ // call this once every ms
{
if (saved_settings.mode == MODE_STREAM_TX)
{
}
else
if (saved_settings.mode == MODE_STREAM_RX)
{
}
}
// *************************************************************
@ -49,6 +57,13 @@ void stream_1ms_tick(void)
void stream_process(void)
{
if (saved_settings.mode == MODE_STREAM_TX)
{
}
else
if (saved_settings.mode == MODE_STREAM_RX)
{
}
}
// *************************************************************

78
ground/openpilotgcs/src/plugins/pipxtreme/pipxtremegadgetwidget.cpp
View File

@ -45,37 +45,39 @@
#define PIPX_HEADER_MARKER 0x76b38a52
#define PIPX_PACKET_TYPE_REQ_DETAILS 0
#define PIPX_PACKET_TYPE_DETAILS 1
#define PIPX_PACKET_TYPE_REQ_SETTINGS 2
#define PIPX_PACKET_TYPE_SETTINGS 3
#define PIPX_PACKET_TYPE_REQ_STATE 4
#define PIPX_PACKET_TYPE_STATE 5
enum {
freqBand_UNKNOWN = 0,
freqBand_434MHz,
freqBand_868MHz,
freqBand_915MHz
PIPX_PACKET_TYPE_REQ_DETAILS = 0,
PIPX_PACKET_TYPE_DETAILS,
PIPX_PACKET_TYPE_REQ_SETTINGS,
PIPX_PACKET_TYPE_SETTINGS,
PIPX_PACKET_TYPE_REQ_STATE,
PIPX_PACKET_TYPE_STATE
};
enum {
link_disconnected = 0,
link_connecting,
link_connected
FREQBAND_UNKNOWN = 0,
FREQBAND_434MHz,
FREQBAND_868MHz,
FREQBAND_915MHz
};
enum {
LINK_DISCONNECTED = 0,
LINK_CONNECTING,
LINK_CONNECTED
};
// ***************************************************************************************
enum {
modeNormal = 0, // normal 2-way packet mode
modeStreamTx, // 1-way continuous tx packet mode
modeStreamRx, // 1-way continuous rx packet mode
modePPMTx, // PPM tx mode
modePPMRx, // PPM rx mode
modeScanSpectrum, // scan the receiver over the whole band
modeTxBlankCarrierTest, // blank carrier Tx mode (for calibrating the carrier frequency say)
modeTxSpectrumTest // pseudo random Tx data mode (for checking the Tx carrier spectrum)
MODE_NORMAL = 0, // normal 2-way packet mode
MODE_STREAM_TX, // 1-way continuous tx packet mode
MODE_STREAM_RX, // 1-way continuous rx packet mode
MODE_PPM_TX, // PPM tx mode
MODE_PPM_RX, // PPM rx mode
MODE_SCAN_SPECTRUM, // scan the receiver over the whole band
MODE_TX_BLANK_CARRIER_TEST, // blank carrier Tx mode (for calibrating the carrier frequency say)
MODE_TX_SPECTRUM_TEST // pseudo random Tx data mode (for checking the Tx carrier spectrum)
};
// ***************************************************************************************
@ -156,14 +158,14 @@ PipXtremeGadgetWidget::PipXtremeGadgetWidget(QWidget *parent) :
m_widget->comboBox_SerialBaudrate->setCurrentIndex(m_widget->comboBox_SerialBaudrate->findText("57600"));
m_widget->comboBox_Mode->clear();
m_widget->comboBox_Mode->addItem("Normal", modeNormal);
m_widget->comboBox_Mode->addItem("Stream Tx", modeStreamTx);
m_widget->comboBox_Mode->addItem("Stream Rx", modeStreamRx);
m_widget->comboBox_Mode->addItem("PPM Tx", modePPMTx);
m_widget->comboBox_Mode->addItem("PPM Rx", modePPMRx);
m_widget->comboBox_Mode->addItem("Scan Spectrum", modeScanSpectrum);
m_widget->comboBox_Mode->addItem("Test Tx Blank Carrier Frequency", modeTxBlankCarrierTest);
m_widget->comboBox_Mode->addItem("Test Tx Spectrum", modeTxSpectrumTest);
m_widget->comboBox_Mode->addItem("Normal", MODE_NORMAL);
m_widget->comboBox_Mode->addItem("Continuous Stream Tx", MODE_STREAM_TX);
m_widget->comboBox_Mode->addItem("Continuous Stream Rx", MODE_STREAM_RX);
m_widget->comboBox_Mode->addItem("PPM Tx", MODE_PPM_TX);
m_widget->comboBox_Mode->addItem("PPM Rx", MODE_PPM_RX);
m_widget->comboBox_Mode->addItem("Scan Spectrum", MODE_SCAN_SPECTRUM);
m_widget->comboBox_Mode->addItem("Test Tx Blank Carrier Frequency", MODE_TX_BLANK_CARRIER_TEST);
m_widget->comboBox_Mode->addItem("Test Tx Spectrum", MODE_TX_SPECTRUM_TEST);
m_widget->comboBox_SerialPortSpeed->clear();
for (int i = 0; i < m_widget->comboBox_SerialBaudrate->count(); i++)
@ -870,11 +872,11 @@ void PipXtremeGadgetWidget::processRxPacket(quint8 *packet, int packet_size)
memcpy(&pipx_config_details, data, sizeof(t_pipx_config_details));
if (pipx_config_details.major_version < 0 || (pipx_config_details.major_version == 0 && pipx_config_details.minor_version < 2))
if (pipx_config_details.major_version < 0 || (pipx_config_details.major_version <= 0 && pipx_config_details.minor_version < 3))
{
QMessageBox msgBox;
msgBox.setIcon(QMessageBox::Critical);
msgBox.setText("You need to update your modem firmware to V0.2 or later");
msgBox.setText("You need to update your modem firmware to V0.3 or later");
msgBox.exec();
disconnectPort(true);
return;
@ -884,13 +886,13 @@ void PipXtremeGadgetWidget::processRxPacket(quint8 *packet, int packet_size)
m_widget->lineEdit_SerialNumber->setText(QString::number(pipx_config_details.serial_number, 16).toUpper());
if (pipx_config_details.frequency_band == freqBand_434MHz)
if (pipx_config_details.frequency_band == FREQBAND_434MHz)
m_widget->lineEdit_FrequencyBand->setText("434MHz");
else
if (pipx_config_details.frequency_band == freqBand_868MHz)
if (pipx_config_details.frequency_band == FREQBAND_868MHz)
m_widget->lineEdit_FrequencyBand->setText("868MHz");
else
if (pipx_config_details.frequency_band == freqBand_915MHz)
if (pipx_config_details.frequency_band == FREQBAND_915MHz)
m_widget->lineEdit_FrequencyBand->setText("915MHz");
else
m_widget->lineEdit_FrequencyBand->setText("UNKNOWN [" + QString::number(pipx_config_details.frequency_band) + "]");
@ -962,13 +964,13 @@ void PipXtremeGadgetWidget::processRxPacket(quint8 *packet, int packet_size)
switch (pipx_config_state.link_state)
{
case link_disconnected:
case LINK_DISCONNECTED:
m_widget->lineEdit_LinkState->setText("Disconnected");
break;
case link_connecting:
case LINK_CONNECTING:
m_widget->lineEdit_LinkState->setText("Connecting");
break;
case link_connected:
case LINK_CONNECTED:
m_widget->lineEdit_LinkState->setText("Connected");
break;
default: