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Add F2 support for the new OpenOCD for newer targets. Requires compiling
OpenOCD from repo.
This commit is contained in:
James Cotton
parent
0bba13a0e9
commit
7720f9ff09
75
flight/Project/OpenOCD/stm32f1x.cfg
Normal file
75
flight/Project/OpenOCD/stm32f1x.cfg
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@ -0,0 +1,75 @@
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# script for stm32
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
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adapter_khz 1000
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adapter_nsrst_delay 100
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jtag_ntrst_delay 100
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#jtag scan chain
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0008
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# Section 26.6.3
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set _CPUTAPID 0x3ba00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID ] } {
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# FIXME this never gets used to override defaults...
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0008
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# Section 29.6.2
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# Low density devices, Rev A
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set _BSTAPID1 0x06412041
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# Medium density devices, Rev A
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set _BSTAPID2 0x06410041
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# Medium density devices, Rev B and Rev Z
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set _BSTAPID3 0x16410041
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set _BSTAPID4 0x06420041
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# High density devices, Rev A
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set _BSTAPID5 0x06414041
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# Connectivity line devices, Rev A and Rev Z
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set _BSTAPID6 0x06418041
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# XL line devices, Rev A
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set _BSTAPID7 0x06430041
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}
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jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
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-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
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-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
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-expected-id $_BSTAPID6 -expected-id $_BSTAPID7
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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61
flight/Project/OpenOCD/stm32f2x.cfg
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61
flight/Project/OpenOCD/stm32f2x.cfg
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@ -0,0 +1,61 @@
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# script for stm32f2xxx
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f2xxx
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
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#
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# Since we may be running of an RC oscilator, we crank down the speed a
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# bit more to be on the safe side. Perhaps superstition, but if are
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# running off a crystal, we can run closer to the limit. Note
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# that there can be a pretty wide band where things are more or less stable.
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jtag_khz 1000
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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#jtag scan chain
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0033
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# Section 32.6.3 - corresponds to Cortex-M3 r2p0
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set _CPUTAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID ] } {
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0033
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# Section 32.6.2
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#
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set _BSTAPID 0x06411041
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}
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jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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@ -242,4 +242,50 @@ wipe:
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-c "flash erase_address pad $(2) $(3)" \
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-c "reset run" \
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-c "shutdown"
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endef
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endef
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# $(1) = Name of binary image to write
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# $(2) = Base of flash region to write/wipe
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# $(3) = Size of flash region to write/wipe
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define JTAG_TEMPLATE_F2X
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# ---------------------------------------------------------------------------
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# Options for OpenOCD flash-programming
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# see openocd.pdf/openocd.texi for further information
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# if OpenOCD is in the $PATH just set OPENOCDEXE=openocd
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OOCD_EXE ?= openocd
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# debug level
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OOCD_JTAG_SETUP = -d0
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# interface and board/target settings (using the OOCD target-library here)
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OOCD_JTAG_SETUP += -s $(TOP)/flight/Project/OpenOCD
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OOCD_JTAG_SETUP += -f foss-jtag.revb.cfg -f stm32f2x.cfg
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# initialize
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OOCD_BOARD_RESET = -c init
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# show the targets
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#OOCD_BOARD_RESET += -c targets
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# commands to prepare flash-write
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OOCD_BOARD_RESET += -c "reset halt"
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.PHONY: program
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program: $(1)
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@echo $(MSG_JTAG_PROGRAM) $$(call toprel, $$<)
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$(V1) $(OOCD_EXE) \
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$$(OOCD_JTAG_SETUP) \
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$$(OOCD_BOARD_RESET) \
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-c "flash write_image erase $$< $(2) bin" \
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-c "verify_image $$< $(2) bin" \
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-c "reset run" \
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-c "shutdown"
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.PHONY: wipe
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wipe:
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@echo $(MSG_JTAG_WIPE) wiping $(3) bytes starting from $(2)
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$(V1) $(OOCD_EXE) \
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$$(OOCD_JTAG_SETUP) \
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$$(OOCD_BOARD_RESET) \
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-c "flash erase_address pad $(2) $(3)" \
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-c "reset run" \
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-c "shutdown"
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endef
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