Add F2 support for the new OpenOCD for newer targets. Requires compiling

OpenOCD from repo.

flight/Project/OpenOCD/stm32f1x.cfg

@@ -0,0 +1,75 @@
+# script for stm32
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.3
+   set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0008
+  # Section 29.6.2
+  # Low density devices, Rev A
+  set _BSTAPID1 0x06412041
+  # Medium density devices, Rev A
+  set _BSTAPID2 0x06410041
+  # Medium density devices, Rev B and Rev Z
+  set _BSTAPID3 0x16410041
+  set _BSTAPID4 0x06420041
+  # High density devices, Rev A
+  set _BSTAPID5 0x06414041
+  # Connectivity line devices, Rev A and Rev Z
+  set _BSTAPID6 0x06418041
+  # XL line devices, Rev A
+  set _BSTAPID7 0x06430041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+	-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
+	-expected-id $_BSTAPID6 -expected-id $_BSTAPID7
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq

flight/Project/OpenOCD/stm32f2x.cfg

@@ -0,0 +1,61 @@
+# script for stm32f2xxx
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32f2xxx
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x10000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0033
+  # Section 32.6.3 - corresponds to Cortex-M3 r2p0
+   set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0033
+  # Section 32.6.2
+  # 
+  set _BSTAPID 0x06411041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+

make/firmware-defs.mk

@@ -242,4 +242,50 @@ wipe:
 		-c "flash erase_address pad $(2) $(3)" \
 		-c "reset run" \
 		-c "shutdown"
-endef
+endef
+
+# $(1) = Name of binary image to write
+# $(2) = Base of flash region to write/wipe
+# $(3) = Size of flash region to write/wipe
+define JTAG_TEMPLATE_F2X
+# ---------------------------------------------------------------------------
+# Options for OpenOCD flash-programming
+# see openocd.pdf/openocd.texi for further information
+
+# if OpenOCD is in the $PATH just set OPENOCDEXE=openocd
+OOCD_EXE ?= openocd
+
+# debug level
+OOCD_JTAG_SETUP  = -d0
+# interface and board/target settings (using the OOCD target-library here)
+OOCD_JTAG_SETUP += -s $(TOP)/flight/Project/OpenOCD
+OOCD_JTAG_SETUP += -f foss-jtag.revb.cfg -f stm32f2x.cfg
+
+# initialize
+OOCD_BOARD_RESET = -c init
+# show the targets
+#OOCD_BOARD_RESET += -c targets
+# commands to prepare flash-write
+OOCD_BOARD_RESET += -c "reset halt"
+
+.PHONY: program
+program: $(1)
+	@echo $(MSG_JTAG_PROGRAM) $$(call toprel, $$<)
+	$(V1) $(OOCD_EXE) \
+		$$(OOCD_JTAG_SETUP) \
+		$$(OOCD_BOARD_RESET) \
+		-c "flash write_image erase $$< $(2) bin" \
+		-c "verify_image $$< $(2) bin" \
+		-c "reset run" \
+		-c "shutdown"
+
+.PHONY: wipe
+wipe:
+	@echo $(MSG_JTAG_WIPE) wiping $(3) bytes starting from $(2)
+	$(V1) $(OOCD_EXE) \
+		$$(OOCD_JTAG_SETUP) \
+		$$(OOCD_BOARD_RESET) \
+		-c "flash erase_address pad $(2) $(3)" \
+		-c "reset run" \
+		-c "shutdown"
+endef