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MagBaro Extension board module
OSD update OSD output module for FC Sonar update Flight mode fixes + poi
This commit is contained in:
parent
587b12dd3e
commit
77cae9ffc3
@ -39,7 +39,9 @@
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#include "openpilot.h"
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#include "hwsettings.h"
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#include "altitude.h"
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#if defined(PIOS_INCLUDE_BMP085)
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#include "baroaltitude.h" // object that will be updated by the module
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#endif
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#if defined(PIOS_INCLUDE_HCSR04)
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#include "sonaraltitude.h" // object that will be updated by the module
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#endif
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@ -55,12 +57,15 @@
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static xTaskHandle taskHandle;
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// down sampling variables
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#if defined(PIOS_INCLUDE_BMP085)
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#define alt_ds_size 4
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static int32_t alt_ds_temp = 0;
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static int32_t alt_ds_pres = 0;
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static int alt_ds_count = 0;
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#endif
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static bool altitudeEnabled;
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static uint8_t hwsettings_rcvrport;;
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// Private functions
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static void altitudeTask(void *parameters);
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@ -73,9 +78,11 @@ int32_t AltitudeStart()
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{
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if (altitudeEnabled) {
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#if defined(PIOS_INCLUDE_BMP085)
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BaroAltitudeInitialize();
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#endif
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#if defined(PIOS_INCLUDE_HCSR04)
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SonarAltitudeInitialze();
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SonarAltitudeInitialize();
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#endif
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// Start main task
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@ -105,11 +112,13 @@ int32_t AltitudeInitialize()
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}
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#endif
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#if defined(PIOS_INCLUDE_BMP085)
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// init down-sampling data
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alt_ds_temp = 0;
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alt_ds_pres = 0;
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alt_ds_count = 0;
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#endif
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HwSettingsCC_RcvrPortGet(&hwsettings_rcvrport);
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return 0;
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}
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MODULE_INITCALL(AltitudeInitialize, AltitudeStart)
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@ -118,46 +127,52 @@ MODULE_INITCALL(AltitudeInitialize, AltitudeStart)
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*/
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static void altitudeTask(void *parameters)
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{
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BaroAltitudeData data;
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portTickType lastSysTime;
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#if defined(PIOS_INCLUDE_HCSR04)
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SonarAltitudeData sonardata;
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int32_t value=0,timeout=5;
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float coeff=0.25,height_out=0,height_in=0;
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PIOS_HCSR04_Init();
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PIOS_HCSR04_Trigger();
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if(hwsettings_rcvrport==HWSETTINGS_CC_RCVRPORT_DISABLED) {
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PIOS_HCSR04_Trigger();
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}
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#endif
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#if defined(PIOS_INCLUDE_BMP085)
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BaroAltitudeData data;
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PIOS_BMP085_Init();
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#endif
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// Main task loop
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lastSysTime = xTaskGetTickCount();
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while (1)
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{
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#if defined(PIOS_INCLUDE_HCSR04)
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// Compute the current altitude (all pressures in kPa)
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if(PIOS_HCSR04_Completed())
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{
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value = PIOS_HCSR04_Get();
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if((value>100) && (value < 15000)) //from 3.4cm to 5.1m
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// Compute the current altitude
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if(hwsettings_rcvrport==HWSETTINGS_CC_RCVRPORT_DISABLED) {
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if(PIOS_HCSR04_Completed())
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{
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height_in = value*0.00034;
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height_out = (height_out * (1 - coeff)) + (height_in * coeff);
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sonardata.Altitude = height_out; // m/us
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value = PIOS_HCSR04_Get();
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if((value>100) && (value < 15000)) //from 3.4cm to 5.1m
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{
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height_in = value*0.00034f/2.0f;
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height_out = (height_out * (1 - coeff)) + (height_in * coeff);
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sonardata.Altitude = height_out; // m/us
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}
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// Update the AltitudeActual UAVObject
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SonarAltitudeSet(&sonardata);
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timeout=5;
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PIOS_HCSR04_Trigger();
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}
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if(!(timeout--))
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{
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//retrigger
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timeout=5;
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PIOS_HCSR04_Trigger();
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}
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// Update the AltitudeActual UAVObject
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SonarAltitudeSet(&sonardata);
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timeout=5;
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PIOS_HCSR04_Trigger();
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}
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if(timeout--)
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{
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//retrigger
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timeout=5;
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PIOS_HCSR04_Trigger();
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}
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#endif
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#if defined(PIOS_INCLUDE_BMP085)
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// Update the temperature data
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PIOS_BMP085_StartADC(TemperatureConv);
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#ifdef PIOS_BMP085_HAS_GPIOS
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@ -196,6 +211,7 @@ static void altitudeTask(void *parameters)
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// Update the AltitudeActual UAVObject
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BaroAltitudeSet(&data);
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}
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#endif
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// Delay until it is time to read the next sample
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vTaskDelayUntil(&lastSysTime, UPDATE_PERIOD / portTICK_RATE_MS);
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@ -61,10 +61,6 @@ static void altitudeTask(void *parameters);
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*/
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int32_t AltitudeStart()
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{
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#if defined(PIOS_INCLUDE_HCSR04)
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SonarAltitudeInitialze();
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#endif
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// Start main task
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xTaskCreate(altitudeTask, (signed char *)"Altitude", STACK_SIZE_BYTES/4, NULL, TASK_PRIORITY, &taskHandle);
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TaskMonitorAdd(TASKINFO_RUNNING_ALTITUDE, taskHandle);
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@ -79,7 +75,9 @@ int32_t AltitudeStart()
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int32_t AltitudeInitialize()
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{
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BaroAltitudeInitialize();
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#if defined(PIOS_INCLUDE_HCSR04)
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SonarAltitudeInitialize();
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#endif
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return 0;
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}
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MODULE_INITCALL(AltitudeInitialize, AltitudeStart)
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@ -92,9 +90,8 @@ static void altitudeTask(void *parameters)
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#if defined(PIOS_INCLUDE_HCSR04)
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SonarAltitudeData sonardata;
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int32_t value=0,timeout=5;
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int32_t value=0,timeout=10,sample_rate=0;
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float coeff=0.25,height_out=0,height_in=0;
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PIOS_HCSR04_Init();
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PIOS_HCSR04_Trigger();
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#endif
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@ -111,27 +108,32 @@ static void altitudeTask(void *parameters)
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while (1)
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{
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#if defined(PIOS_INCLUDE_HCSR04)
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// Compute the current altitude (all pressures in kPa)
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if(PIOS_HCSR04_Completed())
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// Compute the current altitude
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// depends on baro samplerate
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if(!(sample_rate--))
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{
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value = PIOS_HCSR04_Get();
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if((value>100) && (value < 15000)) //from 3.4cm to 5.1m
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if(PIOS_HCSR04_Completed())
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{
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height_in = value*0.00034;
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height_out = (height_out * (1 - coeff)) + (height_in * coeff);
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sonardata.Altitude = height_out; // m/us
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value = PIOS_HCSR04_Get();
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if((value>100) && (value < 15000)) //from 3.4cm to 5.1m
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{
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height_in = value*0.00034f/2.0f;
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height_out = (height_out * (1 - coeff)) + (height_in * coeff);
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sonardata.Altitude = height_out; // m/us
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}
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// Update the SonarAltitude UAVObject
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SonarAltitudeSet(&sonardata);
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timeout=10;
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PIOS_HCSR04_Trigger();
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}
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// Update the AltitudeActual UAVObject
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SonarAltitudeSet(&sonardata);
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timeout=5;
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PIOS_HCSR04_Trigger();
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}
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if(timeout--)
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{
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//retrigger
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timeout=5;
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PIOS_HCSR04_Trigger();
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if(!(timeout--))
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{
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//retrigger
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timeout=10;
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PIOS_HCSR04_Trigger();
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}
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sample_rate=25;
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}
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#endif
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float temp, press;
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@ -43,9 +43,9 @@
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#include "magnetometer.h"
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// Private constants
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#define STACK_SIZE_BYTES 620
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#define STACK_SIZE_BYTES 600
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#define TASK_PRIORITY (tskIDLE_PRIORITY+1)
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#define UPDATE_PERIOD 50
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#define UPDATE_PERIOD 100
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// Private types
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@ -53,14 +53,20 @@
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static xTaskHandle taskHandle;
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// down sampling variables
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static bool magbaroEnabled;
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#if defined(PIOS_INCLUDE_BMP085)
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#define alt_ds_size 4
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static int32_t alt_ds_temp = 0;
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static int32_t alt_ds_pres = 0;
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static int alt_ds_count = 0;
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#endif
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#if defined(PIOS_INCLUDE_HMC5883)
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int32_t mag_test;
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static bool magbaroEnabled;
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static float mag_bias[3] = {0,0,0};
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static float mag_scale[3] = {1,1,1};
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#endif
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// Private functions
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static void magbaroTask(void *parameters);
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@ -75,7 +81,7 @@ int32_t MagBaroStart()
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if (magbaroEnabled) {
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// Start main task
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xTaskCreate(magbaroTask, (signed char *)"MagBaro", STACK_SIZE_BYTES/4, NULL, TASK_PRIORITY, &taskHandle);
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//TaskMonitorAdd(TASKINFO_RUNNING_MAGBARO, taskHandle);
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TaskMonitorAdd(TASKINFO_RUNNING_MAGBARO, taskHandle);
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return 0;
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}
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return -1;
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@ -102,13 +108,18 @@ int32_t MagBaroInitialize()
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if(magbaroEnabled)
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{
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#if defined(PIOS_INCLUDE_HMC5883)
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MagnetometerInitialize();
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#endif
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#if defined(PIOS_INCLUDE_BMP085)
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BaroAltitudeInitialize();
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// init down-sampling data
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alt_ds_temp = 0;
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alt_ds_pres = 0;
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alt_ds_count = 0;
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#endif
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}
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return 0;
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}
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@ -116,7 +127,7 @@ MODULE_INITCALL(MagBaroInitialize, MagBaroStart)
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/**
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* Module thread, should not return.
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*/
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#if defined(PIOS_INCLUDE_HMC5883)
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static const struct pios_hmc5883_cfg pios_hmc5883_cfg = {
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#ifdef PIOS_HMC5883_HAS_GPIOS
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.exti_cfg = 0,
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@ -127,27 +138,25 @@ static const struct pios_hmc5883_cfg pios_hmc5883_cfg = {
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.Mode = PIOS_HMC5883_MODE_CONTINUOUS,
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};
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#endif
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static void magbaroTask(void *parameters)
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{
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BaroAltitudeData data;
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portTickType lastSysTime;
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#if defined(PIOS_INCLUDE_BMP085)
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BaroAltitudeData data;
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PIOS_BMP085_Init();
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#endif
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#if defined(PIOS_INCLUDE_HMC5883)
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PIOS_HMC5883_Init(&pios_hmc5883_cfg);
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#endif
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#if defined(PIOS_INCLUDE_HMC5883)
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//mag_test = PIOS_HMC5883_Test();
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#else
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mag_test = 0;
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MagnetometerData mag;
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PIOS_HMC5883_Init(&pios_hmc5883_cfg);
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uint32_t mag_update_time = PIOS_DELAY_GetRaw();
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#endif
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// Main task loop
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lastSysTime = xTaskGetTickCount();
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uint32_t mag_update_time = PIOS_DELAY_GetRaw();
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while (1)
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{
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#if defined(PIOS_INCLUDE_BMP085)
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@ -160,7 +169,7 @@ static void magbaroTask(void *parameters)
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#endif
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PIOS_BMP085_ReadADC();
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alt_ds_temp += PIOS_BMP085_GetTemperature();
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// Update the pressure data
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PIOS_BMP085_StartADC(PressureConv);
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#ifdef PIOS_BMP085_HAS_GPIOS
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@ -170,7 +179,7 @@ static void magbaroTask(void *parameters)
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#endif
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PIOS_BMP085_ReadADC();
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alt_ds_pres += PIOS_BMP085_GetPressure();
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if (++alt_ds_count >= alt_ds_size)
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{
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alt_ds_count = 0;
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@ -192,7 +201,6 @@ static void magbaroTask(void *parameters)
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#endif
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#if defined(PIOS_INCLUDE_HMC5883)
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MagnetometerData mag;
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if (PIOS_HMC5883_NewDataAvailable() || PIOS_DELAY_DiffuS(mag_update_time) > 100000) {
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int16_t values[3];
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PIOS_HMC5883_ReadMag(values);
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@ -42,9 +42,12 @@ typedef enum {FLIGHTMODE_UNDEFINED = 0, FLIGHTMODE_MANUAL = 1, FLIGHTMODE_STABIL
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(x == FLIGHTSTATUS_FLIGHTMODE_ALTITUDEHOLD) ? FLIGHTMODE_GUIDANCE : \
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(x == FLIGHTSTATUS_FLIGHTMODE_VELOCITYCONTROL) ? FLIGHTMODE_GUIDANCE : \
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(x == FLIGHTSTATUS_FLIGHTMODE_POSITIONHOLD) ? FLIGHTMODE_GUIDANCE : \
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(x == FLIGHTSTATUS_FLIGHTMODE_RETURNTOBASE) ? FLIGHTMODE_GUIDANCE : \
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(x == FLIGHTSTATUS_FLIGHTMODE_PATHPLANNER) ? FLIGHTMODE_GUIDANCE : \
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(x == FLIGHTSTATUS_FLIGHTMODE_AUTOTUNE) ? FLIGHTMODE_TUNING : FLIGHTMODE_UNDEFINED \
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(x == FLIGHTSTATUS_FLIGHTMODE_RETURNTOBASE) ? FLIGHTMODE_GUIDANCE : \
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(x == FLIGHTSTATUS_FLIGHTMODE_LAND) ? FLIGHTMODE_GUIDANCE : \
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(x == FLIGHTSTATUS_FLIGHTMODE_AUTOTUNE) ? FLIGHTMODE_TUNING : \
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(x == FLIGHTSTATUS_FLIGHTMODE_POI) ? FLIGHTMODE_GUIDANCE : \
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FLIGHTMODE_UNDEFINED \
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)
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int32_t ManualControlInitialize();
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@ -105,8 +108,14 @@ int32_t ManualControlInitialize();
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_STABILIZED1 == (int) FLIGHTSTATUS_FLIGHTMODE_STABILIZED1) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_STABILIZED2 == (int) FLIGHTSTATUS_FLIGHTMODE_STABILIZED2) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_STABILIZED3 == (int) FLIGHTSTATUS_FLIGHTMODE_STABILIZED3) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_ALTITUDEHOLD == (int) FLIGHTSTATUS_FLIGHTMODE_ALTITUDEHOLD) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_VELOCITYCONTROL == (int) FLIGHTSTATUS_FLIGHTMODE_VELOCITYCONTROL) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_POSITIONHOLD == (int) FLIGHTSTATUS_FLIGHTMODE_POSITIONHOLD) \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_POSITIONHOLD == (int) FLIGHTSTATUS_FLIGHTMODE_POSITIONHOLD) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_PATHPLANNER == (int) FLIGHTSTATUS_FLIGHTMODE_PATHPLANNER) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_RETURNTOBASE == (int) FLIGHTSTATUS_FLIGHTMODE_RETURNTOBASE) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_LAND == (int) FLIGHTSTATUS_FLIGHTMODE_LAND) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_AUTOTUNE == (int) FLIGHTSTATUS_FLIGHTMODE_AUTOTUNE) && \
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( (int)MANUALCONTROLSETTINGS_FLIGHTMODEPOSITION_POI == (int) FLIGHTSTATUS_FLIGHTMODE_POI) \
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)
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#define assumptions_channelcount ( \
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315
flight/Modules/Osd/OsdHk/OsdHk.c
Normal file
315
flight/Modules/Osd/OsdHk/OsdHk.c
Normal file
@ -0,0 +1,315 @@
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/**
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******************************************************************************
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* @addtogroup OpenPilotModules OpenPilot Modules
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* @{
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* @addtogroup HKOSDModule HK OSD Module
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* @brief On screen display support
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* @{
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*
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* @file OsdHk.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* @brief Interfacing with HobbyKing OSD module
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* @see The GNU Public License (GPL) Version 3
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "openpilot.h"
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#if FLIGHTBATTERYSTATE_SUPPORTED
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#include "flightbatterystate.h"
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#endif
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#if POSITIONACTUAL_SUPPORTED
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#include "positionactual.h"
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#endif
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#include "systemalarms.h"
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#include "attitudeactual.h"
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#include "hwsettings.h"
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static bool osdhkEnabled;
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enum osd_hk_sync {
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OSD_HK_SYNC_A = 0xCB,
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OSD_HK_SYNC_B = 0x34,
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};
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enum osd_hk_pkt_type {
|
||||
OSD_HK_PKT_TYPE_MISC = 0,
|
||||
OSD_HK_PKT_TYPE_NAV = 1,
|
||||
OSD_HK_PKT_TYPE_MAINT = 2,
|
||||
OSD_HK_PKT_TYPE_ATT = 3,
|
||||
};
|
||||
|
||||
enum osd_hk_control_mode {
|
||||
OSD_HK_CONTROL_MODE_MANUAL = 0,
|
||||
OSD_HK_CONTROL_MODE_STABILIZED = 1,
|
||||
OSD_HK_CONTROL_MODE_AUTO = 2,
|
||||
};
|
||||
|
||||
struct osd_hk_blob_misc {
|
||||
uint8_t type; /* Always OSD_HK_PKT_TYPE_MISC */
|
||||
int16_t roll;
|
||||
int16_t pitch;
|
||||
//uint16_t home; /* Big Endian */
|
||||
enum osd_hk_control_mode control_mode;
|
||||
uint8_t low_battery;
|
||||
uint16_t current; /* Big Endian */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct osd_hk_blob_att {
|
||||
uint8_t type; /* Always OSD_HK_PKT_TYPE_ATT */
|
||||
int16_t roll;
|
||||
int16_t pitch;
|
||||
int16_t yaw;
|
||||
int16_t speed; /* Big Endian */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct osd_hk_blob_nav {
|
||||
uint8_t type; /* Always OSD_HK_PKT_TYPE_NAV */
|
||||
uint32_t gps_lat; /* Big Endian */
|
||||
uint32_t gps_lon; /* Big Endian */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct osd_hk_blob_maint {
|
||||
uint8_t type; /* Always OSD_HK_PKT_TYPE_MAINT */
|
||||
uint8_t gps_speed;
|
||||
uint16_t gps_alt; /* Big Endian */
|
||||
uint16_t gps_dis; /* Big Endian */
|
||||
uint8_t status;
|
||||
uint8_t config;
|
||||
uint8_t emerg;
|
||||
} __attribute__((packed));
|
||||
|
||||
union osd_hk_pkt_blobs
|
||||
{
|
||||
struct osd_hk_blob_misc misc;
|
||||
struct osd_hk_blob_nav nav;
|
||||
struct osd_hk_blob_maint maint;
|
||||
struct osd_hk_blob_att att;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct osd_hk_msg {
|
||||
enum osd_hk_sync sync;
|
||||
enum osd_hk_pkt_type t;
|
||||
union osd_hk_pkt_blobs v;
|
||||
} __attribute__((packed));
|
||||
|
||||
#if 0
|
||||
#if sizeof(struct osd_hk_msg) != 11
|
||||
#error struct osd_hk_msg is the wrong size, something is wrong with the definition
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static struct osd_hk_msg osd_hk_msg_buf;
|
||||
|
||||
static volatile bool newPositionActualData = false;
|
||||
static volatile bool newBattData = false;
|
||||
static volatile bool newAttitudeData = false;
|
||||
static volatile bool newAlarmData = false;
|
||||
|
||||
static uint32_t osd_hk_com_id;
|
||||
static uint8_t osd_hk_msg_dropped;
|
||||
|
||||
static void send_update(UAVObjEvent * ev)
|
||||
{
|
||||
static enum osd_hk_sync sync = OSD_HK_SYNC_A;
|
||||
|
||||
struct osd_hk_msg * msg = &osd_hk_msg_buf;
|
||||
union osd_hk_pkt_blobs * blob = &(osd_hk_msg_buf.v);
|
||||
|
||||
/* Make sure we have a COM port bound */
|
||||
if (!osd_hk_com_id) {
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up the message
|
||||
*
|
||||
* NOTE: Only packet type 0 (MISC) is supported so far
|
||||
*/
|
||||
msg->sync = sync;
|
||||
msg->t = OSD_HK_PKT_TYPE_ATT;
|
||||
|
||||
if (newAttitudeData) {
|
||||
float roll;
|
||||
AttitudeActualRollGet(&roll);
|
||||
//blob->misc.roll = (int16_t) roll;
|
||||
blob->att.roll = (int16_t) roll;
|
||||
|
||||
float pitch;
|
||||
AttitudeActualPitchGet(&pitch);
|
||||
//blob->misc.pitch = (int16_t) pitch;
|
||||
blob->att.pitch = (int16_t) pitch;
|
||||
|
||||
float yaw;
|
||||
AttitudeActualYawGet(&yaw);
|
||||
blob->att.yaw = (int16_t) yaw;
|
||||
}
|
||||
|
||||
/* Field not supported yet */
|
||||
//blob->misc.control_mode = 0;
|
||||
|
||||
/*if (newAlarmData) {
|
||||
SystemAlarmsData alarms;
|
||||
SystemAlarmsGet(&alarms);
|
||||
|
||||
switch (alarms.Alarm[SYSTEMALARMS_ALARM_BATTERY]) {
|
||||
case SYSTEMALARMS_ALARM_UNINITIALISED:
|
||||
case SYSTEMALARMS_ALARM_OK:
|
||||
blob->misc.low_battery = 0;
|
||||
break;
|
||||
case SYSTEMALARMS_ALARM_WARNING:
|
||||
case SYSTEMALARMS_ALARM_ERROR:
|
||||
case SYSTEMALARMS_ALARM_CRITICAL:
|
||||
default:
|
||||
blob->misc.low_battery = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
newAlarmData = false;
|
||||
}*/
|
||||
|
||||
#if FLIGHTBATTERYSUPPORTED
|
||||
if (newBattData) {
|
||||
float consumed_energy;
|
||||
FlightBatteryStateConsumedEnergyGet(&consumed_energy);
|
||||
|
||||
uint16_t current = (uint16_t)(consumed_energy * 10);
|
||||
|
||||
/* convert to big endian */
|
||||
blob->misc.current = (
|
||||
(current & 0xFF00 >> 8) |
|
||||
(current & 0x00FF << 8));
|
||||
|
||||
newBattData = false;
|
||||
}
|
||||
#else
|
||||
//blob->misc.current = 0;
|
||||
#endif
|
||||
|
||||
#if POSITIONACTUAL_SUPPORTED
|
||||
if (newPositionActualData) {
|
||||
PositionActualData position;
|
||||
PositionActualGet(&position);
|
||||
|
||||
/* compute 3D distance */
|
||||
float d = sqrt(
|
||||
pow(position.North,2) +
|
||||
pow(position.East,2) +
|
||||
pow(position.Down,2));
|
||||
/* convert from cm to dm (10ths of m) */
|
||||
uint16_t home = (uint16_t)(d / 10);
|
||||
|
||||
/* convert to big endian */
|
||||
blob->misc.home = (
|
||||
(home & 0xFF00 >> 8) |
|
||||
(home & 0x00FF << 8));
|
||||
|
||||
newPositionActualData = false;
|
||||
}
|
||||
#else
|
||||
//blob->misc.home = 0;
|
||||
#endif
|
||||
|
||||
if (!PIOS_COM_SendBufferNonBlocking(osd_hk_com_id, (uint8_t *)&osd_hk_msg_buf, sizeof(osd_hk_msg_buf))) {
|
||||
/* Sent a packet, flip to the opposite sync */
|
||||
if (sync == OSD_HK_SYNC_A) {
|
||||
sync = OSD_HK_SYNC_B;
|
||||
} else {
|
||||
sync = OSD_HK_SYNC_A;
|
||||
}
|
||||
} else {
|
||||
/* Failed to send this update */
|
||||
osd_hk_msg_dropped++;
|
||||
}
|
||||
}
|
||||
|
||||
#if FLIGHTBATTERYSTATE_SUPPORTED
|
||||
static void FlightBatteryStateUpdatedCb(UAVObjEvent * ev)
|
||||
{
|
||||
newBattData = true;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if POSITIONACTUAL_SUPPORTED
|
||||
static void PositionActualUpdatedCb(UAVObjEvent * ev)
|
||||
{
|
||||
newPositionActualData = true;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void AttitudeActualUpdatedCb(UAVObjEvent * ev)
|
||||
{
|
||||
newAttitudeData = true;
|
||||
}
|
||||
|
||||
static void SystemAlarmsUpdatedCb(UAVObjEvent * ev)
|
||||
{
|
||||
newAlarmData = true;
|
||||
}
|
||||
|
||||
static UAVObjEvent ev;
|
||||
|
||||
static int32_t OsdHkStart(void)
|
||||
{
|
||||
if (osdhkEnabled) {
|
||||
// Start main task
|
||||
AttitudeActualConnectCallback(AttitudeActualUpdatedCb);
|
||||
|
||||
SystemAlarmsConnectCallback(SystemAlarmsUpdatedCb);
|
||||
|
||||
#if FLIGHTBATTERYSTATE_SUPPORTED
|
||||
FlightBatteryStateConnectCallback(FlightBatteryStateUpdatedCb);
|
||||
#endif
|
||||
|
||||
#if POSITIONACTUAL_SUPPORTED
|
||||
PositionActualConnectCallback(PositionActualUpdatedCb);
|
||||
#endif
|
||||
|
||||
/* Start a periodic timer to kick sending of an update */
|
||||
EventPeriodicCallbackCreate(&ev, send_update, 25 / portTICK_RATE_MS);
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int32_t OsdHkInitialize(void)
|
||||
{
|
||||
osd_hk_com_id = PIOS_COM_OSDHK;
|
||||
#ifdef MODULE_OsdHk_BUILTIN
|
||||
osdhkEnabled = 1;
|
||||
#else
|
||||
HwSettingsInitialize();
|
||||
uint8_t optionalModules[HWSETTINGS_OPTIONALMODULES_NUMELEM];
|
||||
HwSettingsOptionalModulesGet(optionalModules);
|
||||
if (optionalModules[HWSETTINGS_OPTIONALMODULES_OSDHK] == HWSETTINGS_OPTIONALMODULES_ENABLED) {
|
||||
osdhkEnabled = 1;
|
||||
} else {
|
||||
osdhkEnabled = 0;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
MODULE_INITCALL(OsdHkInitialize, OsdHkStart)
|
||||
|
||||
/**
|
||||
* @}
|
||||
* @}
|
||||
*/
|
41
flight/Modules/Osd/OsdHk/inc/OsdHk.h
Normal file
41
flight/Modules/Osd/OsdHk/inc/OsdHk.h
Normal file
@ -0,0 +1,41 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @addtogroup OpenPilotModules OpenPilot Modules
|
||||
* @{
|
||||
* @addtogroup HKOSDModule HK OSD Module
|
||||
* @brief On screen display support
|
||||
* @{
|
||||
*
|
||||
* @file OsdHk.h
|
||||
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
|
||||
* @brief Interfacing with HobbyKing OSD module
|
||||
*
|
||||
* @see The GNU Public License (GPL) Version 3
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef OSDHK_H
|
||||
#define OSDHK_H
|
||||
|
||||
int32_t OsdHkInitialize(void);
|
||||
|
||||
#endif /* OSDHK_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
* @}
|
||||
*/
|
@ -9,6 +9,7 @@
|
||||
#define OSDGEN_H_
|
||||
|
||||
#include "openpilot.h"
|
||||
#include "pios.h"
|
||||
|
||||
int32_t osdgenInitialize(void);
|
||||
|
||||
|
@ -173,7 +173,7 @@ void drawCircle(uint16_t x0, uint16_t y0, uint16_t radius) {
|
||||
write_pixel_lm(x0, y0 - radius,1,1);
|
||||
write_pixel_lm(x0 + radius, y0,1,1);
|
||||
write_pixel_lm(x0 - radius, y0,1,1);
|
||||
|
||||
|
||||
while(x < y)
|
||||
{
|
||||
// ddF_x == 2 * x + 1;
|
||||
@ -851,11 +851,11 @@ void write_line(uint8_t *buff, unsigned int x0, unsigned int y0, unsigned int x1
|
||||
{
|
||||
if(steep)
|
||||
{
|
||||
write_pixel(buff, y, x, mode);
|
||||
write_pixel(buff, y, x, mode);
|
||||
}
|
||||
else
|
||||
{
|
||||
write_pixel(buff, x, y, mode);
|
||||
write_pixel(buff, x, y, mode);
|
||||
}
|
||||
error -= deltay;
|
||||
if(error < 0)
|
||||
@ -2198,6 +2198,9 @@ void updateGraphics() {
|
||||
HomeLocationGet(&home);
|
||||
BaroAltitudeData baro;
|
||||
BaroAltitudeGet(&baro);
|
||||
|
||||
PIOS_Servo_Set(0,OsdSettings.White);
|
||||
PIOS_Servo_Set(1,OsdSettings.Black);
|
||||
|
||||
switch (OsdSettings.Screen) {
|
||||
case 0: // Dave simple
|
||||
@ -2229,7 +2232,7 @@ void updateGraphics() {
|
||||
else
|
||||
calcHomeArrow((int16_t)(gpsData.Heading));
|
||||
}
|
||||
break;
|
||||
break;
|
||||
case 1:
|
||||
{
|
||||
/*drawBox(2,2,GRAPHICS_WIDTH_REAL-4,GRAPHICS_HEIGHT_REAL-4);
|
||||
@ -2262,7 +2265,7 @@ void updateGraphics() {
|
||||
calcHomeArrow((int16_t)(gpsData.Heading));
|
||||
|
||||
/* Draw Attitude Indicator */
|
||||
if(OsdSettings.Attitude == OSDSETTINGS_ATTITUDE_ENABLED)
|
||||
if(OsdSettings.Attitude == OSDSETTINGS_ATTITUDE_ENABLED)
|
||||
{
|
||||
drawAttitude(APPLY_HDEADBAND(OsdSettings.AttitudeSetup[OSDSETTINGS_ATTITUDESETUP_X]),APPLY_VDEADBAND(OsdSettings.AttitudeSetup[OSDSETTINGS_ATTITUDESETUP_Y]),attitude.Pitch,attitude.Roll,96);
|
||||
}
|
||||
@ -2294,11 +2297,11 @@ void updateGraphics() {
|
||||
/* Print ADC voltage */
|
||||
//sprintf(temp,"Rssi:%4dV",(int)(PIOS_ADC_PinGet(4)*3000/4096));
|
||||
//write_string(temp, (GRAPHICS_WIDTH_REAL - 2),15, 0, 0, TEXT_VA_TOP, TEXT_HA_RIGHT, 0, 2);
|
||||
sprintf(temp,"Rssi:%4.2fV",(PIOS_ADC_PinGet(4)*3.0f/4096.0f));
|
||||
sprintf(temp,"Rssi:%4.2fV",(PIOS_ADC_PinGet(5)*3.0f/4096.0f));
|
||||
write_string(temp, APPLY_HDEADBAND((GRAPHICS_RIGHT - 8)),APPLY_VDEADBAND(15), 0, 0, TEXT_VA_TOP, TEXT_HA_RIGHT, 0, 2);
|
||||
|
||||
/* Print CPU temperature */
|
||||
sprintf(temp,"Temp:%4.2fC",(PIOS_ADC_PinGet(6)*0.29296875f-264));
|
||||
sprintf(temp,"Temp:%4.2fC",(PIOS_ADC_PinGet(3)*0.29296875f-264));
|
||||
write_string(temp, APPLY_HDEADBAND((GRAPHICS_RIGHT - 8)),APPLY_VDEADBAND(25), 0, 0, TEXT_VA_TOP, TEXT_HA_RIGHT, 0, 2);
|
||||
|
||||
/* Print ADC voltage FLIGHT*/
|
||||
@ -2306,7 +2309,7 @@ void updateGraphics() {
|
||||
write_string(temp, APPLY_HDEADBAND((GRAPHICS_RIGHT - 8)),APPLY_VDEADBAND(35), 0, 0, TEXT_VA_TOP, TEXT_HA_RIGHT, 0, 2);
|
||||
|
||||
/* Print ADC voltage VIDEO*/
|
||||
sprintf(temp,"VidV:%4.2fV",(PIOS_ADC_PinGet(3)*3.0f*6.1f/4096.0f));
|
||||
sprintf(temp,"VidV:%4.2fV",(PIOS_ADC_PinGet(4)*3.0f*6.1f/4096.0f));
|
||||
write_string(temp, APPLY_HDEADBAND((GRAPHICS_RIGHT - 8)),APPLY_VDEADBAND(45), 0, 0, TEXT_VA_TOP, TEXT_HA_RIGHT, 0, 2);
|
||||
|
||||
/* Print ADC voltage RSSI */
|
||||
@ -2371,7 +2374,7 @@ void updateGraphics() {
|
||||
draw_artificial_horizon(-attitude.Roll,attitude.Pitch,APPLY_HDEADBAND(x),APPLY_VDEADBAND(y),size);
|
||||
hud_draw_vertical_scale((int)gpsData.Groundspeed, 20, +1, APPLY_HDEADBAND(GRAPHICS_RIGHT-(x-1)),
|
||||
APPLY_VDEADBAND(y+(size/2)), size, 5, 10, 4, 7, 10, 100, HUD_VSCALE_FLAG_NO_NEGATIVE);
|
||||
if(1)
|
||||
if(OsdSettings.AltitudeSource == OSDSETTINGS_ALTITUDESOURCE_BARO)
|
||||
{
|
||||
hud_draw_vertical_scale((int)baro.Altitude, 50, -1, APPLY_HDEADBAND((x+size+1)),
|
||||
APPLY_VDEADBAND(y+(size/2)), size, 10, 20, 4, 7, 10, 500, 0);
|
||||
@ -2389,10 +2392,21 @@ void updateGraphics() {
|
||||
lamas();
|
||||
}
|
||||
break;
|
||||
default:
|
||||
write_vline_lm( APPLY_HDEADBAND(GRAPHICS_RIGHT/2),APPLY_VDEADBAND(0),APPLY_VDEADBAND(GRAPHICS_BOTTOM),1,1);
|
||||
write_hline_lm( APPLY_HDEADBAND(0),APPLY_HDEADBAND(GRAPHICS_RIGHT),APPLY_VDEADBAND(GRAPHICS_BOTTOM/2),1,1);
|
||||
case 4:
|
||||
case 5:
|
||||
case 6:
|
||||
{
|
||||
int image=OsdSettings.Screen-4;
|
||||
struct splashEntry splash_info;
|
||||
splash_info = splash[image];
|
||||
|
||||
copyimage(APPLY_HDEADBAND(GRAPHICS_RIGHT/2-(splash_info.width)/2), APPLY_VDEADBAND(GRAPHICS_BOTTOM/2-(splash_info.height)/2),image);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
write_vline_lm( APPLY_HDEADBAND(GRAPHICS_RIGHT/2),APPLY_VDEADBAND(0),APPLY_VDEADBAND(GRAPHICS_BOTTOM),1,1);
|
||||
write_hline_lm( APPLY_HDEADBAND(0),APPLY_HDEADBAND(GRAPHICS_RIGHT),APPLY_VDEADBAND(GRAPHICS_BOTTOM/2),1,1);
|
||||
break;
|
||||
}
|
||||
|
||||
// Must mask out last half-word because SPI keeps clocking it out otherwise
|
||||
@ -2420,7 +2434,7 @@ int32_t osdgenStart(void)
|
||||
// Start gps task
|
||||
vSemaphoreCreateBinary( osdSemaphore);
|
||||
xTaskCreate(osdgenTask, (signed char *)"OSDGEN", STACK_SIZE_BYTES/4, NULL, TASK_PRIORITY, &osdgenTaskHandle);
|
||||
//TaskMonitorAdd(TASKINFO_RUNNING_GPS, osdgenTaskHandle);
|
||||
TaskMonitorAdd(TASKINFO_RUNNING_OSDGEN, osdgenTaskHandle);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -2460,6 +2474,11 @@ static void osdgenTask(void *parameters)
|
||||
//portTickType lastSysTime;
|
||||
// Loop forever
|
||||
//lastSysTime = xTaskGetTickCount();
|
||||
OsdSettingsData OsdSettings;
|
||||
OsdSettingsGet (&OsdSettings);
|
||||
|
||||
PIOS_Servo_Set(0,OsdSettings.White);
|
||||
PIOS_Servo_Set(1,OsdSettings.Black);
|
||||
|
||||
// intro
|
||||
for(int i=0; i<63; i++)
|
||||
|
@ -156,6 +156,10 @@ extern uint32_t pios_com_debug_id;
|
||||
#define PIOS_COM_DEBUG (pios_com_debug_id)
|
||||
#endif /* PIOS_INCLUDE_DEBUG_CONSOLE */
|
||||
|
||||
extern uint32_t pios_com_hkosd_id;
|
||||
#define PIOS_COM_OSDHK (pios_com_hkosd_id)
|
||||
|
||||
|
||||
//-------------------------
|
||||
// ADC
|
||||
// PIOS_ADC_PinGet(0) = Gyro Z
|
||||
|
@ -76,7 +76,7 @@ TIM4 | STOPWATCH |
|
||||
//#define PIOS_PERIPHERAL_CLOCK
|
||||
//#define PIOS_PERIPHERAL_CLOCK
|
||||
|
||||
#define PIOS_SYSCLK 108000000
|
||||
#define PIOS_SYSCLK 168000000
|
||||
// Peripherals that belongs to APB1 are:
|
||||
// DAC |PWR |CAN1,2
|
||||
// I2C1,2,3 |UART4,5 |USART3,2
|
||||
@ -106,12 +106,6 @@ TIM4 | STOPWATCH |
|
||||
#define TELEM_QUEUE_SIZE 20
|
||||
#define PIOS_TELEM_STACK_SIZE 624
|
||||
|
||||
// *****************************************************************
|
||||
// System Settings
|
||||
|
||||
#define PIOS_MASTER_CLOCK 108000000ul
|
||||
#define PIOS_PERIPHERAL_CLOCK (PIOS_MASTER_CLOCK / 2)
|
||||
|
||||
// *****************************************************************
|
||||
// Interrupt Priorities
|
||||
|
||||
@ -207,12 +201,13 @@ extern uint32_t pios_com_telem_usb_id;
|
||||
|
||||
//-------------------------
|
||||
// ADC
|
||||
// PIOS_ADC_PinGet(0) = External voltage
|
||||
// PIOS_ADC_PinGet(1) = AUX1 (PX2IO external pressure port)
|
||||
// PIOS_ADC_PinGet(2) = AUX2 (Current sensor, if available)
|
||||
// PIOS_ADC_PinGet(3) = AUX3
|
||||
// PIOS_ADC_PinGet(4) = VREF
|
||||
// PIOS_ADC_PinGet(5) = Temperature sensor
|
||||
// PIOS_ADC_PinGet(0) = Current
|
||||
// PIOS_ADC_PinGet(1) = Voltage
|
||||
// PIOS_ADC_PinGet(2) = Flight
|
||||
// PIOS_ADC_PinGet(3) = Temperature sensor
|
||||
// PIOS_ADC_PinGet(4) = Video
|
||||
// PIOS_ADC_PinGet(5) = RSSI
|
||||
// PIOS_ADC_PinGet(6) = VREF
|
||||
//-------------------------
|
||||
|
||||
#define PIOS_DMA_PIN_CONFIG \
|
||||
@ -220,10 +215,10 @@ extern uint32_t pios_com_telem_usb_id;
|
||||
{GPIOC, GPIO_Pin_0, ADC_Channel_10}, \
|
||||
{GPIOC, GPIO_Pin_1, ADC_Channel_11}, \
|
||||
{GPIOC, GPIO_Pin_2, ADC_Channel_12}, \
|
||||
{NULL, 0, ADC_Channel_TempSensor}, /* Temperature sensor */\
|
||||
{GPIOC, GPIO_Pin_3, ADC_Channel_13}, \
|
||||
{GPIOA, GPIO_Pin_7, ADC_Channel_7}, \
|
||||
{NULL, 0, ADC_Channel_Vrefint}, /* Voltage reference */\
|
||||
{NULL, 0, ADC_Channel_TempSensor} /* Temperature sensor */\
|
||||
{NULL, 0, ADC_Channel_Vrefint} /* Voltage reference */\
|
||||
}
|
||||
|
||||
/* we have to do all this to satisfy the PIOS_ADC_MAX_SAMPLES define in pios_adc.h */
|
||||
@ -232,6 +227,7 @@ extern uint32_t pios_com_telem_usb_id;
|
||||
#define PIOS_ADC_NUM_CHANNELS 7
|
||||
#define PIOS_ADC_MAX_OVERSAMPLING 10
|
||||
#define PIOS_ADC_USE_ADC2 0
|
||||
#define PIOS_ADC_USE_TEMP_SENSOR 1
|
||||
|
||||
// *****************************************************************
|
||||
// USB
|
||||
|
@ -124,11 +124,13 @@ extern uint32_t pios_com_gps_id;
|
||||
extern uint32_t pios_com_telem_usb_id;
|
||||
extern uint32_t pios_com_bridge_id;
|
||||
extern uint32_t pios_com_vcp_id;
|
||||
extern uint32_t pios_com_hkosd_id;
|
||||
#define PIOS_COM_GPS (pios_com_gps_id)
|
||||
#define PIOS_COM_TELEM_USB (pios_com_telem_usb_id)
|
||||
#define PIOS_COM_TELEM_RF (pios_com_telem_rf_id)
|
||||
#define PIOS_COM_BRIDGE (pios_com_bridge_id)
|
||||
#define PIOS_COM_VCP (pios_com_vcp_id)
|
||||
#define PIOS_COM_OSDHK (pios_com_hkosd_id)
|
||||
|
||||
#if defined(PIOS_INCLUDE_DEBUG_CONSOLE)
|
||||
extern uint32_t pios_com_debug_id;
|
||||
|
@ -95,6 +95,7 @@ TIM8 | | | |
|
||||
#define PIOS_WDG_ATTITUDE 0x0004
|
||||
#define PIOS_WDG_MANUAL 0x0008
|
||||
#define PIOS_WDG_SENSORS 0x0010
|
||||
#define PIOS_WDG_AUTOTUNE 0x0020
|
||||
|
||||
//------------------------
|
||||
// PIOS_I2C
|
||||
@ -126,6 +127,7 @@ extern uint32_t pios_com_aux_id;
|
||||
extern uint32_t pios_com_telem_usb_id;
|
||||
extern uint32_t pios_com_bridge_id;
|
||||
extern uint32_t pios_com_vcp_id;
|
||||
extern uint32_t pios_com_hkosd_id;
|
||||
#define PIOS_COM_AUX (pios_com_aux_id)
|
||||
#define PIOS_COM_GPS (pios_com_gps_id)
|
||||
#define PIOS_COM_TELEM_USB (pios_com_telem_usb_id)
|
||||
@ -133,6 +135,7 @@ extern uint32_t pios_com_vcp_id;
|
||||
#define PIOS_COM_BRIDGE (pios_com_bridge_id)
|
||||
#define PIOS_COM_VCP (pios_com_vcp_id)
|
||||
#define PIOS_COM_DEBUG PIOS_COM_AUX
|
||||
#define PIOS_COM_OSDHK (pios_com_hkosd_id)
|
||||
|
||||
//------------------------
|
||||
// TELEMETRY
|
||||
@ -236,8 +239,9 @@ extern uint32_t pios_com_vcp_id;
|
||||
// ADC
|
||||
// PIOS_ADC_PinGet(0) = Current sensor
|
||||
// PIOS_ADC_PinGet(1) = Voltage sensor
|
||||
// PIOS_ADC_PinGet(4) = VREF
|
||||
// PIOS_ADC_PinGet(5) = Temperature sensor
|
||||
// PIOS_ADC_PinGet(2) = VREF
|
||||
// PIOS_ADC_PinGet(3) = Temperature sensor
|
||||
// PIOS_ADC_PinGet(4) = Board Power
|
||||
//-------------------------
|
||||
#define PIOS_DMA_PIN_CONFIG \
|
||||
{ \
|
||||
@ -255,6 +259,7 @@ extern uint32_t pios_com_vcp_id;
|
||||
#define PIOS_ADC_MAX_OVERSAMPLING 2
|
||||
#define PIOS_ADC_USE_ADC2 0
|
||||
#define PIOS_ADC_VOLTAGE_SCALE 3.30/4096.0
|
||||
#define PIOS_ADC_USE_TEMP_SENSOR 1
|
||||
|
||||
//-------------------------
|
||||
// USB
|
||||
|
@ -29,6 +29,7 @@
|
||||
*/
|
||||
|
||||
#include "pios.h"
|
||||
#include "pios_hcsr04_priv.h"
|
||||
|
||||
#ifdef PIOS_INCLUDE_HCSR04
|
||||
|
||||
@ -37,173 +38,260 @@
|
||||
#endif
|
||||
|
||||
/* Local Variables */
|
||||
/* 100 ms timeout without updates on channels */
|
||||
const static uint32_t PWM_SUPERVISOR_TIMEOUT = 100000;
|
||||
|
||||
static TIM_ICInitTypeDef TIM_ICInitStructure;
|
||||
static uint8_t CaptureState;
|
||||
static uint16_t RiseValue;
|
||||
static uint16_t FallValue;
|
||||
static uint32_t CaptureValue;
|
||||
static uint32_t CapCounter;
|
||||
struct pios_hcsr04_dev * hcsr04_dev_loc;
|
||||
|
||||
enum pios_hcsr04_dev_magic {
|
||||
PIOS_HCSR04_DEV_MAGIC = 0xab3029AA,
|
||||
};
|
||||
|
||||
struct pios_hcsr04_dev {
|
||||
enum pios_hcsr04_dev_magic magic;
|
||||
const struct pios_hcsr04_cfg * cfg;
|
||||
|
||||
uint8_t CaptureState[PIOS_PWM_NUM_INPUTS];
|
||||
uint16_t RiseValue[PIOS_PWM_NUM_INPUTS];
|
||||
uint16_t FallValue[PIOS_PWM_NUM_INPUTS];
|
||||
uint32_t CaptureValue[PIOS_PWM_NUM_INPUTS];
|
||||
uint32_t CapCounter[PIOS_PWM_NUM_INPUTS];
|
||||
uint32_t us_since_update[PIOS_PWM_NUM_INPUTS];
|
||||
};
|
||||
|
||||
static bool PIOS_HCSR04_validate(struct pios_hcsr04_dev * hcsr04_dev)
|
||||
{
|
||||
return (hcsr04_dev->magic == PIOS_HCSR04_DEV_MAGIC);
|
||||
}
|
||||
|
||||
#if defined(PIOS_INCLUDE_FREERTOS)
|
||||
static struct pios_hcsr04_dev * PIOS_PWM_alloc(void)
|
||||
{
|
||||
struct pios_hcsr04_dev * hcsr04_dev;
|
||||
|
||||
hcsr04_dev = (struct pios_hcsr04_dev *)pvPortMalloc(sizeof(*hcsr04_dev));
|
||||
if (!hcsr04_dev) return(NULL);
|
||||
|
||||
hcsr04_dev->magic = PIOS_HCSR04_DEV_MAGIC;
|
||||
return(hcsr04_dev);
|
||||
}
|
||||
#else
|
||||
static struct pios_hcsr04_dev pios_hcsr04_devs[PIOS_PWM_MAX_DEVS];
|
||||
static uint8_t pios_hcsr04_num_devs;
|
||||
static struct pios_hcsr04_dev * PIOS_PWM_alloc(void)
|
||||
{
|
||||
struct pios_hcsr04_dev * hcsr04_dev;
|
||||
|
||||
if (pios_pwm_num_devs >= PIOS_PWM_MAX_DEVS) {
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
hcsr04_dev = &pios_hcsr04_devs[pios_hcsr04_num_devs++];
|
||||
hcsr04_dev->magic = PIOS_HCSR04_DEV_MAGIC;
|
||||
|
||||
return (hcsr04_dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void PIOS_HCSR04_tim_overflow_cb (uint32_t id, uint32_t context, uint8_t channel, uint16_t count);
|
||||
static void PIOS_HCSR04_tim_edge_cb (uint32_t id, uint32_t context, uint8_t channel, uint16_t count);
|
||||
const static struct pios_tim_callbacks tim_callbacks = {
|
||||
.overflow = PIOS_HCSR04_tim_overflow_cb,
|
||||
.edge = PIOS_HCSR04_tim_edge_cb,
|
||||
};
|
||||
|
||||
#define PIOS_HCSR04_TRIG_GPIO_PORT GPIOD
|
||||
#define PIOS_HCSR04_TRIG_PIN GPIO_Pin_2
|
||||
|
||||
/**
|
||||
* Initialise the HC-SR04 sensor
|
||||
* Initialises all the pins
|
||||
*/
|
||||
void PIOS_HCSR04_Init(void)
|
||||
int32_t PIOS_HCSR04_Init(uint32_t * pwm_id, const struct pios_hcsr04_cfg * cfg)
|
||||
{
|
||||
/* Init triggerpin */
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_StructInit(&GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStructure.GPIO_Pin = PIOS_HCSR04_TRIG_PIN;
|
||||
GPIO_Init(PIOS_HCSR04_TRIG_GPIO_PORT, &GPIO_InitStructure);
|
||||
PIOS_HCSR04_TRIG_GPIO_PORT->BSRR = PIOS_HCSR04_TRIG_PIN;
|
||||
PIOS_DEBUG_Assert(pwm_id);
|
||||
PIOS_DEBUG_Assert(cfg);
|
||||
|
||||
/* Flush counter variables */
|
||||
CaptureState = 0;
|
||||
RiseValue = 0;
|
||||
FallValue = 0;
|
||||
CaptureValue = 0;
|
||||
struct pios_hcsr04_dev * hcsr04_dev;
|
||||
|
||||
/* Setup RCC */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
|
||||
hcsr04_dev = (struct pios_hcsr04_dev *) PIOS_PWM_alloc();
|
||||
if (!hcsr04_dev) goto out_fail;
|
||||
|
||||
/* Enable timer interrupts */
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
/* Bind the configuration to the device instance */
|
||||
hcsr04_dev->cfg = cfg;
|
||||
hcsr04_dev_loc = hcsr04_dev;
|
||||
|
||||
/* Partial pin remap for TIM3 (PB5) */
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap_TIM3, ENABLE);
|
||||
for (uint8_t i = 0; i < PIOS_PWM_NUM_INPUTS; i++) {
|
||||
/* Flush counter variables */
|
||||
hcsr04_dev->CaptureState[i] = 0;
|
||||
hcsr04_dev->RiseValue[i] = 0;
|
||||
hcsr04_dev->FallValue[i] = 0;
|
||||
hcsr04_dev->CaptureValue[i] = PIOS_RCVR_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Configure input pins */
|
||||
GPIO_StructInit(&GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
uint32_t tim_id;
|
||||
if (PIOS_TIM_InitChannels(&tim_id, cfg->channels, cfg->num_channels, &tim_callbacks, (uint32_t)hcsr04_dev)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Configure timer for input capture */
|
||||
TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
|
||||
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
|
||||
TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
|
||||
TIM_ICInitStructure.TIM_ICFilter = 0x0;
|
||||
TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
|
||||
TIM_ICInit(TIM3, &TIM_ICInitStructure);
|
||||
/* Configure the channels to be in capture/compare mode */
|
||||
for (uint8_t i = 0; i < cfg->num_channels; i++) {
|
||||
const struct pios_tim_channel * chan = &cfg->channels[i];
|
||||
|
||||
/* Configure timer clocks */
|
||||
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
||||
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
|
||||
TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = (PIOS_MASTER_CLOCK / 500000) - 1;
|
||||
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_InternalClockConfig(TIM3);
|
||||
TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
|
||||
/* Configure timer for input capture */
|
||||
TIM_ICInitTypeDef TIM_ICInitStructure = cfg->tim_ic_init;
|
||||
TIM_ICInitStructure.TIM_Channel = chan->timer_chan;
|
||||
TIM_ICInit(chan->timer, &TIM_ICInitStructure);
|
||||
|
||||
/* Enable the Capture Compare Interrupt Request */
|
||||
//TIM_ITConfig(PIOS_PWM_CH8_TIM_PORT, PIOS_PWM_CH8_CCR, ENABLE);
|
||||
TIM_ITConfig(TIM3, TIM_IT_CC2, DISABLE);
|
||||
/* Enable the Capture Compare Interrupt Request */
|
||||
switch (chan->timer_chan) {
|
||||
case TIM_Channel_1:
|
||||
TIM_ITConfig(chan->timer, TIM_IT_CC1, ENABLE);
|
||||
break;
|
||||
case TIM_Channel_2:
|
||||
TIM_ITConfig(chan->timer, TIM_IT_CC2, ENABLE);
|
||||
break;
|
||||
case TIM_Channel_3:
|
||||
TIM_ITConfig(chan->timer, TIM_IT_CC3, ENABLE);
|
||||
break;
|
||||
case TIM_Channel_4:
|
||||
TIM_ITConfig(chan->timer, TIM_IT_CC4, ENABLE);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable timers */
|
||||
TIM_Cmd(TIM3, ENABLE);
|
||||
// Need the update event for that timer to detect timeouts
|
||||
TIM_ITConfig(chan->timer, TIM_IT_Update, ENABLE);
|
||||
|
||||
/* Setup local variable which stays in this scope */
|
||||
/* Doing this here and using a local variable saves doing it in the ISR */
|
||||
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
|
||||
TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
|
||||
TIM_ICInitStructure.TIM_ICFilter = 0x0;
|
||||
}
|
||||
|
||||
#ifndef STM32F4XX
|
||||
/* Enable the peripheral clock for the GPIO */
|
||||
switch ((uint32_t)hcsr04_dev->cfg->trigger.gpio) {
|
||||
case (uint32_t) GPIOA:
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
break;
|
||||
case (uint32_t) GPIOB:
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
break;
|
||||
case (uint32_t) GPIOC:
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
break;
|
||||
default:
|
||||
PIOS_Assert(0);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
GPIO_Init(hcsr04_dev->cfg->trigger.gpio, &hcsr04_dev->cfg->trigger.init);
|
||||
|
||||
*pwm_id = (uint32_t) hcsr04_dev;
|
||||
|
||||
return (0);
|
||||
|
||||
out_fail:
|
||||
return (-1);
|
||||
}
|
||||
|
||||
void PIOS_HCSR04_Trigger(void)
|
||||
{
|
||||
GPIO_SetBits(hcsr04_dev_loc->cfg->trigger.gpio,hcsr04_dev_loc->cfg->trigger.init.GPIO_Pin);
|
||||
PIOS_DELAY_WaituS(15);
|
||||
GPIO_ResetBits(hcsr04_dev_loc->cfg->trigger.gpio,hcsr04_dev_loc->cfg->trigger.init.GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the value of an sonar timer
|
||||
* \output >0 timer value
|
||||
* Get the value of an input channel
|
||||
* \param[in] Channel Number of the channel desired
|
||||
* \output -1 Channel not available
|
||||
* \output >0 Channel value
|
||||
*/
|
||||
int32_t PIOS_HCSR04_Get(void)
|
||||
{
|
||||
return CaptureValue;
|
||||
return hcsr04_dev_loc->CaptureValue[0];
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the value of an sonar timer
|
||||
* \output >0 timer value
|
||||
*/
|
||||
int32_t PIOS_HCSR04_Completed(void)
|
||||
{
|
||||
return CapCounter;
|
||||
}
|
||||
/**
|
||||
* Trigger sonar sensor
|
||||
*/
|
||||
void PIOS_HCSR04_Trigger(void)
|
||||
{
|
||||
CapCounter=0;
|
||||
PIOS_HCSR04_TRIG_GPIO_PORT->BSRR = PIOS_HCSR04_TRIG_PIN;
|
||||
PIOS_DELAY_WaituS(15);
|
||||
PIOS_HCSR04_TRIG_GPIO_PORT->BRR = PIOS_HCSR04_TRIG_PIN;
|
||||
TIM_ITConfig(TIM3, TIM_IT_CC2, ENABLE);
|
||||
return hcsr04_dev_loc->CapCounter[0];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Handle TIM3 global interrupt request
|
||||
*/
|
||||
//void PIOS_PWM_irq_handler(TIM_TypeDef * timer)
|
||||
void TIM3_IRQHandler(void)
|
||||
static void PIOS_HCSR04_tim_overflow_cb (uint32_t tim_id, uint32_t context, uint8_t channel, uint16_t count)
|
||||
{
|
||||
/* Zero value always will be changed but this prevents compiler warning */
|
||||
int32_t i = 0;
|
||||
struct pios_hcsr04_dev * hcsr04_dev = (struct pios_hcsr04_dev *)context;
|
||||
|
||||
/* Do this as it's more efficient */
|
||||
if (TIM_GetITStatus(TIM3, TIM_IT_CC2) == SET) {
|
||||
i = 7;
|
||||
if (CaptureState == 0) {
|
||||
RiseValue = TIM_GetCapture2(TIM3);
|
||||
} else {
|
||||
FallValue = TIM_GetCapture2(TIM3);
|
||||
}
|
||||
if (!PIOS_HCSR04_validate(hcsr04_dev)) {
|
||||
/* Invalid device specified */
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clear TIM3 Capture compare interrupt pending bit */
|
||||
TIM_ClearITPendingBit(TIM3, TIM_IT_CC2);
|
||||
if (channel >= hcsr04_dev->cfg->num_channels) {
|
||||
/* Channel out of range */
|
||||
return;
|
||||
}
|
||||
|
||||
hcsr04_dev->us_since_update[channel] += count;
|
||||
if(hcsr04_dev->us_since_update[channel] >= PWM_SUPERVISOR_TIMEOUT) {
|
||||
hcsr04_dev->CaptureState[channel] = 0;
|
||||
hcsr04_dev->RiseValue[channel] = 0;
|
||||
hcsr04_dev->FallValue[channel] = 0;
|
||||
hcsr04_dev->CaptureValue[channel] = PIOS_RCVR_TIMEOUT;
|
||||
hcsr04_dev->us_since_update[channel] = 0;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void PIOS_HCSR04_tim_edge_cb (uint32_t tim_id, uint32_t context, uint8_t chan_idx, uint16_t count)
|
||||
{
|
||||
/* Recover our device context */
|
||||
struct pios_hcsr04_dev * hcsr04_dev = (struct pios_hcsr04_dev *)context;
|
||||
|
||||
if (!PIOS_HCSR04_validate(hcsr04_dev)) {
|
||||
/* Invalid device specified */
|
||||
return;
|
||||
}
|
||||
|
||||
if (chan_idx >= hcsr04_dev->cfg->num_channels) {
|
||||
/* Channel out of range */
|
||||
return;
|
||||
}
|
||||
|
||||
const struct pios_tim_channel * chan = &hcsr04_dev->cfg->channels[chan_idx];
|
||||
|
||||
if (hcsr04_dev->CaptureState[chan_idx] == 0) {
|
||||
hcsr04_dev->RiseValue[chan_idx] = count;
|
||||
hcsr04_dev->us_since_update[chan_idx] = 0;
|
||||
} else {
|
||||
hcsr04_dev->FallValue[chan_idx] = count;
|
||||
}
|
||||
|
||||
// flip state machine and capture value here
|
||||
/* Simple rise or fall state machine */
|
||||
if (CaptureState == 0) {
|
||||
TIM_ICInitTypeDef TIM_ICInitStructure = hcsr04_dev->cfg->tim_ic_init;
|
||||
if (hcsr04_dev->CaptureState[chan_idx] == 0) {
|
||||
/* Switch states */
|
||||
CaptureState = 1;
|
||||
hcsr04_dev->CaptureState[chan_idx] = 1;
|
||||
|
||||
/* Switch polarity of input capture */
|
||||
TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;
|
||||
TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
|
||||
TIM_ICInit(TIM3, &TIM_ICInitStructure);
|
||||
|
||||
TIM_ICInitStructure.TIM_Channel = chan->timer_chan;
|
||||
TIM_ICInit(chan->timer, &TIM_ICInitStructure);
|
||||
} else {
|
||||
/* Capture computation */
|
||||
if (FallValue > RiseValue) {
|
||||
CaptureValue = (FallValue - RiseValue);
|
||||
if (hcsr04_dev->FallValue[chan_idx] > hcsr04_dev->RiseValue[chan_idx]) {
|
||||
hcsr04_dev->CaptureValue[chan_idx] = (hcsr04_dev->FallValue[chan_idx] - hcsr04_dev->RiseValue[chan_idx]);
|
||||
} else {
|
||||
CaptureValue = ((0xFFFF - RiseValue) + FallValue);
|
||||
hcsr04_dev->CaptureValue[chan_idx] = ((chan->timer->ARR - hcsr04_dev->RiseValue[chan_idx]) + hcsr04_dev->FallValue[chan_idx]);
|
||||
}
|
||||
|
||||
/* Switch states */
|
||||
CaptureState = 0;
|
||||
hcsr04_dev->CaptureState[chan_idx] = 0;
|
||||
|
||||
/* Increase supervisor counter */
|
||||
CapCounter++;
|
||||
TIM_ITConfig(TIM3, TIM_IT_CC2, DISABLE);
|
||||
hcsr04_dev->CapCounter[chan_idx]++;
|
||||
|
||||
/* Switch polarity of input capture */
|
||||
TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
|
||||
TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
|
||||
TIM_ICInit(TIM3, &TIM_ICInitStructure);
|
||||
|
||||
TIM_ICInitStructure.TIM_Channel = chan->timer_chan;
|
||||
TIM_ICInit(chan->timer, &TIM_ICInitStructure);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif /* PIOS_INCLUDE_HCSR04 */
|
||||
|
@ -33,10 +33,18 @@
|
||||
|
||||
#ifdef PIOS_INCLUDE_VIDEO
|
||||
|
||||
extern xSemaphoreHandle osdSemaphore;
|
||||
// Private methods
|
||||
static void configure_hsync_timers();
|
||||
static void stop_hsync_timers();
|
||||
static void reset_hsync_timers();
|
||||
static void prepare_line(uint32_t line_num);
|
||||
static void flush_spi();
|
||||
|
||||
// Private variables
|
||||
extern xSemaphoreHandle osdSemaphore;
|
||||
static const struct pios_video_cfg * dev_cfg;
|
||||
|
||||
|
||||
// Define the buffers.
|
||||
// For 256x192 pixel mode:
|
||||
// buffer0_level/buffer0_mask becomes buffer_level; and
|
||||
@ -69,6 +77,7 @@ volatile uint16_t gActiveLine = 0;
|
||||
volatile uint16_t gActivePixmapLine = 0;
|
||||
volatile uint16_t line=0;
|
||||
volatile uint16_t Vsync_update=0;
|
||||
volatile uint16_t Hsync_update=0;
|
||||
static int16_t m_osdLines=0;
|
||||
|
||||
/**
|
||||
@ -78,67 +87,51 @@ static int16_t m_osdLines=0;
|
||||
*/
|
||||
void swap_buffers()
|
||||
{
|
||||
// While we could use XOR swap this is more reliable and
|
||||
// dependable and it's only called a few times per second.
|
||||
// Many compliers should optimise these to EXCH instructions.
|
||||
uint8_t *tmp;
|
||||
SWAP_BUFFS(tmp, disp_buffer_mask, draw_buffer_mask);
|
||||
SWAP_BUFFS(tmp, disp_buffer_level, draw_buffer_level);
|
||||
// While we could use XOR swap this is more reliable and
|
||||
// dependable and it's only called a few times per second.
|
||||
// Many compliers should optimise these to EXCH instructions.
|
||||
uint8_t *tmp;
|
||||
SWAP_BUFFS(tmp, disp_buffer_mask, draw_buffer_mask);
|
||||
SWAP_BUFFS(tmp, disp_buffer_level, draw_buffer_level);
|
||||
}
|
||||
|
||||
bool PIOS_Hsync_ISR() {
|
||||
|
||||
if(dev_cfg->hsync->pin.gpio->IDR & dev_cfg->hsync->pin.init.GPIO_Pin) {
|
||||
//rising
|
||||
if(gLineType == LINE_TYPE_GRAPHICS)
|
||||
{
|
||||
// Activate new line
|
||||
DMA_Cmd(dev_cfg->level.dma.tx.channel, ENABLE);
|
||||
DMA_Cmd(dev_cfg->mask.dma.tx.channel, ENABLE);
|
||||
}
|
||||
} else {
|
||||
//falling
|
||||
gLineType = LINE_TYPE_UNKNOWN; // Default case
|
||||
gActiveLine++;
|
||||
|
||||
if ((gActiveLine >= GRAPHICS_LINE) && (gActiveLine < (GRAPHICS_LINE + GRAPHICS_HEIGHT))) {
|
||||
gLineType = LINE_TYPE_GRAPHICS;
|
||||
gActivePixmapLine = (gActiveLine - GRAPHICS_LINE);
|
||||
line = gActivePixmapLine*GRAPHICS_WIDTH;
|
||||
}
|
||||
|
||||
if(gLineType == LINE_TYPE_GRAPHICS)
|
||||
{
|
||||
// Load new line
|
||||
DMA_Cmd(dev_cfg->mask.dma.tx.channel, DISABLE);
|
||||
DMA_Cmd(dev_cfg->level.dma.tx.channel, DISABLE);
|
||||
DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel,(uint32_t)&disp_buffer_level[line],DMA_Memory_0);
|
||||
DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel,(uint32_t)&disp_buffer_mask[line],DMA_Memory_0);
|
||||
DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel,BUFFER_LINE_LENGTH);
|
||||
DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel,BUFFER_LINE_LENGTH);
|
||||
}
|
||||
bool PIOS_Hsync_ISR()
|
||||
{
|
||||
// On tenth line prepare data which will start clocking out on GRAPHICS_LINE+1
|
||||
if(Hsync_update==GRAPHICS_LINE)
|
||||
{
|
||||
prepare_line(0);
|
||||
gActiveLine = 1;
|
||||
}
|
||||
|
||||
return false;
|
||||
Hsync_update++;
|
||||
}
|
||||
|
||||
bool PIOS_Vsync_ISR() {
|
||||
static portBASE_TYPE xHigherPriorityTaskWoken;
|
||||
//PIOS_LED_Toggle(LED3);
|
||||
|
||||
//if(gActiveLine > 200)
|
||||
|
||||
xHigherPriorityTaskWoken = pdFALSE;
|
||||
m_osdLines = gActiveLine;
|
||||
|
||||
stop_hsync_timers();
|
||||
|
||||
// Wait for previous word to clock out of each
|
||||
TIM_Cmd(dev_cfg->pixel_timer.timer, ENABLE);
|
||||
flush_spi();
|
||||
TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
|
||||
|
||||
gActiveLine = 0;
|
||||
Hsync_update = 0;
|
||||
Vsync_update++;
|
||||
if(Vsync_update>=2)
|
||||
{
|
||||
gActiveLine = 0;
|
||||
Vsync_update++;
|
||||
if(Vsync_update>=2)
|
||||
{
|
||||
swap_buffers();
|
||||
Vsync_update=0;
|
||||
xHigherPriorityTaskWoken = xSemaphoreGiveFromISR(osdSemaphore, &xHigherPriorityTaskWoken);
|
||||
}
|
||||
// load second image buffer
|
||||
swap_buffers();
|
||||
Vsync_update=0;
|
||||
|
||||
// trigger redraw every second field
|
||||
xHigherPriorityTaskWoken = xSemaphoreGiveFromISR(osdSemaphore, &xHigherPriorityTaskWoken);
|
||||
}
|
||||
|
||||
portEND_SWITCHING_ISR(xHigherPriorityTaskWoken); //portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
|
||||
|
||||
return xHigherPriorityTaskWoken == pdTRUE;
|
||||
@ -148,134 +141,342 @@ uint16_t PIOS_Video_GetOSDLines(void) {
|
||||
return m_osdLines;
|
||||
}
|
||||
|
||||
void PIOS_Video_Init(const struct pios_video_cfg * cfg){
|
||||
/**
|
||||
* Stops the pixel clock and ensures it ignores the rising edge. To be used after a
|
||||
* vsync until the first line is to be displayed
|
||||
*/
|
||||
static void stop_hsync_timers()
|
||||
{
|
||||
// This removes the slave mode configuration
|
||||
TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
|
||||
TIM_InternalClockConfig(dev_cfg->pixel_timer.timer);
|
||||
}
|
||||
|
||||
const struct pios_tim_callbacks px_callback = {
|
||||
.overflow = NULL,
|
||||
.edge = NULL,
|
||||
};
|
||||
|
||||
#ifdef PAL
|
||||
const uint32_t period = 10;
|
||||
const uint32_t dc = (10 / 2);
|
||||
#else
|
||||
const uint32_t period = 11;
|
||||
const uint32_t dc = (11 / 2);
|
||||
#endif
|
||||
/**
|
||||
* Reset the timer and configure for next call. Keeps them synced. Ideally this won't even be needed
|
||||
* since I don't think the slave mode gets lost, and this can simply be disable timer
|
||||
*/
|
||||
uint32_t failcount = 0;
|
||||
static void reset_hsync_timers()
|
||||
{
|
||||
// Stop both timers
|
||||
TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
|
||||
|
||||
uint32_t tim_id;
|
||||
const struct pios_tim_channel *channels = &dev_cfg->hsync_capture;
|
||||
|
||||
//BUG: This is nuts this line is needed. It simply results in allocating
|
||||
//all the memory but somehow leaving it out breaks the timer functionality.
|
||||
// I do not see how these can be related
|
||||
if (failcount == 0) {
|
||||
if(PIOS_TIM_InitChannels(&tim_id, channels, 1, &px_callback, 0) < 0)
|
||||
failcount++;
|
||||
}
|
||||
|
||||
dev_cfg->pixel_timer.timer->CNT = 0xFFFF - 100; //dc;
|
||||
|
||||
// Listen to Channel1 (HSYNC)
|
||||
switch(dev_cfg->hsync_capture.timer_chan) {
|
||||
case TIM_Channel_1:
|
||||
TIM_SelectInputTrigger(dev_cfg->pixel_timer.timer, TIM_TS_TI1FP1);
|
||||
break;
|
||||
case TIM_Channel_2:
|
||||
TIM_SelectInputTrigger(dev_cfg->pixel_timer.timer, TIM_TS_TI2FP2);
|
||||
break;
|
||||
default:
|
||||
PIOS_Assert(0);
|
||||
}
|
||||
TIM_SelectSlaveMode(dev_cfg->pixel_timer.timer, TIM_SlaveMode_Trigger);
|
||||
}
|
||||
|
||||
|
||||
static void configure_hsync_timers()
|
||||
{
|
||||
// Stop both timers
|
||||
TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
|
||||
|
||||
// This is overkill but used for consistency. No interrupts used for pixel clock
|
||||
// but this function calls the GPIO_Remap
|
||||
uint32_t tim_id;
|
||||
const struct pios_tim_channel *channels;
|
||||
|
||||
// Init the channel to output the pixel clock
|
||||
channels = &dev_cfg->pixel_timer;
|
||||
PIOS_TIM_InitChannels(&tim_id, channels, 1, &px_callback, 0);
|
||||
|
||||
// Init the channel to capture the pulse
|
||||
channels = &dev_cfg->hsync_capture;
|
||||
PIOS_TIM_InitChannels(&tim_id, channels, 1, &px_callback, 0);
|
||||
|
||||
// Configure the input capture channel
|
||||
TIM_ICInitTypeDef TIM_ICInitStructure;
|
||||
switch(dev_cfg->hsync_capture.timer_chan) {
|
||||
case TIM_Channel_1:
|
||||
TIM_ICInitStructure.TIM_Channel = TIM_Channel_1;
|
||||
break;
|
||||
case TIM_Channel_2:
|
||||
TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
|
||||
break;
|
||||
default:
|
||||
PIOS_Assert(0);
|
||||
}
|
||||
TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;
|
||||
//TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
|
||||
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
|
||||
TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
|
||||
TIM_ICInitStructure.TIM_ICFilter = 0;
|
||||
TIM_ICInit(dev_cfg->pixel_timer.timer, &TIM_ICInitStructure);
|
||||
|
||||
// Set up the channel to output the pixel clock
|
||||
switch(dev_cfg->pixel_timer.timer_chan) {
|
||||
case TIM_Channel_1:
|
||||
TIM_OC1Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
|
||||
TIM_OC1PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
|
||||
TIM_SetCompare1(dev_cfg->pixel_timer.timer, dc);
|
||||
break;
|
||||
case TIM_Channel_2:
|
||||
TIM_OC2Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
|
||||
TIM_OC2PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
|
||||
TIM_SetCompare2(dev_cfg->pixel_timer.timer, dc);
|
||||
break;
|
||||
case TIM_Channel_3:
|
||||
TIM_OC3Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
|
||||
TIM_OC3PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
|
||||
TIM_SetCompare3(dev_cfg->pixel_timer.timer, dc);
|
||||
break;
|
||||
case TIM_Channel_4:
|
||||
TIM_OC4Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
|
||||
TIM_OC4PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
|
||||
TIM_SetCompare4(dev_cfg->pixel_timer.timer, dc);
|
||||
break;
|
||||
}
|
||||
TIM_ARRPreloadConfig(dev_cfg->pixel_timer.timer, ENABLE);
|
||||
TIM_CtrlPWMOutputs(dev_cfg->pixel_timer.timer, ENABLE);
|
||||
|
||||
// This shouldn't be needed as it should come from the config struture. Something
|
||||
// is clobbering that
|
||||
TIM_PrescalerConfig(dev_cfg->pixel_timer.timer, 0, TIM_PSCReloadMode_Immediate);
|
||||
TIM_SetAutoreload(dev_cfg->pixel_timer.timer, period);
|
||||
}
|
||||
|
||||
DMA_TypeDef * main_dma;
|
||||
DMA_TypeDef * mask_dma;
|
||||
DMA_Stream_TypeDef * main_stream;
|
||||
DMA_Stream_TypeDef * mask_stream;
|
||||
void PIOS_Video_Init(const struct pios_video_cfg * cfg)
|
||||
{
|
||||
dev_cfg = cfg; // store config before enabling interrupt
|
||||
|
||||
if (cfg->mask.remap) {
|
||||
GPIO_PinAFConfig(cfg->mask.sclk.gpio,
|
||||
__builtin_ctz(cfg->mask.sclk.init.GPIO_Pin),
|
||||
cfg->mask.remap);
|
||||
GPIO_PinAFConfig(cfg->mask.mosi.gpio,
|
||||
__builtin_ctz(cfg->mask.mosi.init.GPIO_Pin),
|
||||
cfg->mask.remap);
|
||||
}
|
||||
if (cfg->level.remap)
|
||||
{
|
||||
GPIO_PinAFConfig(cfg->level.sclk.gpio,
|
||||
__builtin_ctz(cfg->level.sclk.init.GPIO_Pin),
|
||||
cfg->level.remap);
|
||||
GPIO_PinAFConfig(cfg->level.miso.gpio,
|
||||
__builtin_ctz(cfg->level.miso.init.GPIO_Pin),
|
||||
cfg->level.remap);
|
||||
}
|
||||
configure_hsync_timers();
|
||||
|
||||
/* SPI3 MASTER MASKBUFFER */
|
||||
/* needed for HW hack */
|
||||
const GPIO_InitTypeDef initStruct = {
|
||||
.GPIO_Pin = GPIO_Pin_12,
|
||||
.GPIO_Speed = GPIO_Speed_100MHz,
|
||||
.GPIO_Mode = GPIO_Mode_IN ,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_NOPULL
|
||||
};
|
||||
GPIO_Init(GPIOC, &initStruct);
|
||||
|
||||
/* SPI3 - MASKBUFFER */
|
||||
GPIO_Init(cfg->mask.sclk.gpio, (GPIO_InitTypeDef*)&(cfg->mask.sclk.init));
|
||||
GPIO_Init(cfg->mask.mosi.gpio, (GPIO_InitTypeDef*)&(cfg->mask.mosi.init));
|
||||
GPIO_Init(cfg->mask.miso.gpio, (GPIO_InitTypeDef*)&(cfg->mask.miso.init));
|
||||
|
||||
/* SPI1 SLAVE FRAMEBUFFER */
|
||||
GPIO_Init(cfg->level.sclk.gpio, (GPIO_InitTypeDef*)&(cfg->level.sclk.init));
|
||||
GPIO_Init(cfg->level.miso.gpio, (GPIO_InitTypeDef*)&(cfg->level.miso.init));
|
||||
|
||||
if (cfg->mask.remap) {
|
||||
GPIO_PinAFConfig(cfg->mask.sclk.gpio,
|
||||
__builtin_ctz(cfg->mask.sclk.init.GPIO_Pin),
|
||||
cfg->mask.remap);
|
||||
GPIO_PinAFConfig(cfg->mask.miso.gpio,
|
||||
__builtin_ctz(cfg->mask.miso.init.GPIO_Pin),
|
||||
cfg->mask.remap);
|
||||
}
|
||||
if (cfg->level.remap)
|
||||
{
|
||||
GPIO_PinAFConfig(cfg->level.sclk.gpio,
|
||||
__builtin_ctz(cfg->level.sclk.init.GPIO_Pin),
|
||||
cfg->level.remap);
|
||||
GPIO_PinAFConfig(cfg->level.miso.gpio,
|
||||
__builtin_ctz(cfg->level.miso.init.GPIO_Pin),
|
||||
cfg->level.remap);
|
||||
}
|
||||
|
||||
/* Initialize the SPI block */
|
||||
SPI_Init(cfg->level.regs, (SPI_InitTypeDef*)&(cfg->level.init));
|
||||
SPI_Init(cfg->mask.regs, (SPI_InitTypeDef*)&(cfg->mask.init));
|
||||
|
||||
|
||||
/* Enable SPI */
|
||||
SPI_Cmd(cfg->level.regs, ENABLE);
|
||||
SPI_Cmd(cfg->mask.regs, ENABLE);
|
||||
|
||||
/* Configure DMA for SPI Tx MASTER */
|
||||
/* Configure DMA for SPI Tx SLAVE Maskbuffer */
|
||||
DMA_Cmd(cfg->mask.dma.tx.channel, DISABLE);
|
||||
DMA_Init(cfg->mask.dma.tx.channel, (DMA_InitTypeDef*)&(cfg->mask.dma.tx.init));
|
||||
|
||||
/* Configure DMA for SPI Tx SLAVE */
|
||||
/* Configure DMA for SPI Tx SLAVE Framebuffer*/
|
||||
DMA_Cmd(cfg->level.dma.tx.channel, DISABLE);
|
||||
DMA_Init(cfg->level.dma.tx.channel, (DMA_InitTypeDef*)&(cfg->level.dma.tx.init));
|
||||
|
||||
|
||||
/* Trigger interrupt when for half conversions too to indicate double buffer */
|
||||
DMA_ITConfig(cfg->mask.dma.tx.channel, DMA_IT_TC, ENABLE);
|
||||
/*DMA_ClearFlag(cfg->mask.dma.tx.channel,DMA_FLAG_TCIF5);
|
||||
DMA_ClearITPendingBit(cfg->mask.dma.tx.channel, DMA_IT_TCIF5);
|
||||
|
||||
DMA_ClearFlag(cfg->level.dma.tx.channel,DMA_FLAG_TCIF5);
|
||||
DMA_ClearITPendingBit(cfg->level.dma.tx.channel, DMA_IT_TCIF5);
|
||||
*/
|
||||
|
||||
/* Configure DMA interrupt */
|
||||
NVIC_Init(&cfg->level.dma.irq.init);
|
||||
NVIC_Init(&cfg->mask.dma.irq.init);
|
||||
|
||||
/* Enable SPI interrupts to DMA */
|
||||
SPI_I2S_DMACmd(cfg->level.regs, SPI_I2S_DMAReq_Tx, ENABLE);
|
||||
SPI_I2S_DMACmd(cfg->mask.regs, SPI_I2S_DMAReq_Tx, ENABLE);
|
||||
|
||||
/* Configure the Video Line interrupt */
|
||||
PIOS_EXTI_Init(cfg->hsync);
|
||||
PIOS_EXTI_Init(cfg->vsync);
|
||||
|
||||
DMA_ITConfig(cfg->level.dma.tx.channel, DMA_IT_TC, ENABLE);
|
||||
|
||||
/* Configure and clear buffers */
|
||||
draw_buffer_level = buffer0_level;
|
||||
draw_buffer_mask = buffer0_mask;
|
||||
disp_buffer_level = buffer1_level;
|
||||
disp_buffer_mask = buffer1_mask;
|
||||
memset(disp_buffer_mask, 0, GRAPHICS_WIDTH*GRAPHICS_HEIGHT);
|
||||
memset(disp_buffer_level, 0, GRAPHICS_WIDTH*GRAPHICS_HEIGHT);
|
||||
memset(draw_buffer_mask, 0, GRAPHICS_WIDTH*GRAPHICS_HEIGHT);
|
||||
memset(draw_buffer_level, 0, GRAPHICS_WIDTH*GRAPHICS_HEIGHT);
|
||||
|
||||
/* Configure DMA interrupt */
|
||||
|
||||
NVIC_Init(&cfg->level.dma.irq.init);
|
||||
|
||||
/* Enable SPI interrupts to DMA */
|
||||
SPI_I2S_DMACmd(cfg->mask.regs, SPI_I2S_DMAReq_Tx, ENABLE);
|
||||
SPI_I2S_DMACmd(cfg->level.regs, SPI_I2S_DMAReq_Tx, ENABLE);
|
||||
|
||||
mask_dma = DMA1;
|
||||
main_dma = DMA2;
|
||||
main_stream = cfg->level.dma.tx.channel;
|
||||
mask_stream = cfg->mask.dma.tx.channel;
|
||||
/* Configure the Video Line interrupt */
|
||||
PIOS_EXTI_Init(cfg->hsync);
|
||||
PIOS_EXTI_Init(cfg->vsync);
|
||||
|
||||
//set levels to zero
|
||||
PIOS_Servo_Set(0,0);
|
||||
PIOS_Servo_Set(1,0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Interrupt for half and full buffer transfer
|
||||
*
|
||||
* This interrupt handler swaps between the two halfs of the double buffer to make
|
||||
* sure the ahrs uses the most recent data. Only swaps data when AHRS is idle, but
|
||||
* really this is a pretense of a sanity check since the DMA engine is consantly
|
||||
* running in the background. Keep an eye on the ekf_too_slow variable to make sure
|
||||
* it's keeping up.
|
||||
* Prepare the system to watch for a HSYNC pulse to trigger the pixel
|
||||
* clock and clock out the next line
|
||||
*/
|
||||
static void prepare_line(uint32_t line_num)
|
||||
{
|
||||
if(line_num<GRAPHICS_HEIGHT)
|
||||
{
|
||||
uint32_t buf_offset = line_num * GRAPHICS_WIDTH;
|
||||
|
||||
dev_cfg->pixel_timer.timer->CNT = dc;
|
||||
|
||||
DMA_ClearFlag(dev_cfg->mask.dma.tx.channel, DMA_FLAG_TCIF7 | DMA_FLAG_HTIF7 | DMA_FLAG_FEIF7 | DMA_FLAG_TEIF7);
|
||||
DMA_ClearFlag(dev_cfg->level.dma.tx.channel, DMA_FLAG_FEIF5 | DMA_FLAG_TEIF5);
|
||||
|
||||
// Load new line
|
||||
DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel,(uint32_t)&disp_buffer_level[buf_offset],DMA_Memory_0);
|
||||
DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel,(uint32_t)&disp_buffer_mask[buf_offset],DMA_Memory_0);
|
||||
|
||||
// Enable DMA, Slave first
|
||||
DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel, BUFFER_LINE_LENGTH);
|
||||
DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel, BUFFER_LINE_LENGTH);
|
||||
|
||||
SPI_Cmd(dev_cfg->level.regs, ENABLE);
|
||||
SPI_Cmd(dev_cfg->mask.regs, ENABLE);
|
||||
|
||||
/* Enable SPI interrupts to DMA */
|
||||
SPI_I2S_DMACmd(dev_cfg->mask.regs, SPI_I2S_DMAReq_Tx, ENABLE);
|
||||
SPI_I2S_DMACmd(dev_cfg->level.regs, SPI_I2S_DMAReq_Tx, ENABLE);
|
||||
|
||||
DMA_Cmd(dev_cfg->level.dma.tx.channel, ENABLE);
|
||||
DMA_Cmd(dev_cfg->mask.dma.tx.channel, ENABLE);
|
||||
}
|
||||
reset_hsync_timers();
|
||||
}
|
||||
|
||||
void PIOS_VIDEO_DMA_Handler(void);
|
||||
void DMA1_Stream7_IRQHandler(void) __attribute__ ((alias("PIOS_VIDEO_DMA_Handler")));
|
||||
void DMA2_Stream5_IRQHandler(void) __attribute__ ((alias("PIOS_VIDEO_DMA_Handler")));
|
||||
|
||||
/**
|
||||
* Check both SPI for the stop sequence before disabling them
|
||||
*/
|
||||
static void flush_spi()
|
||||
{
|
||||
bool level_empty = false;
|
||||
bool mask_empty = false;
|
||||
bool level_stopped = false;
|
||||
bool mask_stopped = false;
|
||||
|
||||
// Can't flush if clock not running
|
||||
while((dev_cfg->pixel_timer.timer->CR1 & 0x0001) && ( !level_stopped | !mask_stopped )) {
|
||||
|
||||
level_empty |= SPI_I2S_GetFlagStatus(dev_cfg->level.regs ,SPI_I2S_FLAG_TXE) == SET;
|
||||
mask_empty |= SPI_I2S_GetFlagStatus(dev_cfg->mask.regs ,SPI_I2S_FLAG_TXE) == SET;
|
||||
|
||||
if (level_empty && !level_stopped) { // && SPI_I2S_GetFlagStatus(dev_cfg->level.regs ,SPI_I2S_FLAG_BSY) == RESET) {
|
||||
SPI_Cmd(dev_cfg->level.regs, DISABLE);
|
||||
level_stopped = true;
|
||||
}
|
||||
|
||||
if (mask_empty && !mask_stopped) { // && SPI_I2S_GetFlagStatus(dev_cfg->mask.regs ,SPI_I2S_FLAG_BSY) == RESET) {
|
||||
SPI_Cmd(dev_cfg->mask.regs, DISABLE);
|
||||
mask_stopped = true;
|
||||
}
|
||||
}
|
||||
/*
|
||||
uint32_t i = 0;
|
||||
while(SPI_I2S_GetFlagStatus(dev_cfg->level.regs ,SPI_I2S_FLAG_TXE) == RESET && i < 30000) i++;
|
||||
while(SPI_I2S_GetFlagStatus(dev_cfg->mask.regs ,SPI_I2S_FLAG_TXE) == RESET && i < 30000) i++;
|
||||
while(SPI_I2S_GetFlagStatus(dev_cfg->level.regs ,SPI_I2S_FLAG_BSY) == SET && i < 30000) i++;
|
||||
while(SPI_I2S_GetFlagStatus(dev_cfg->mask.regs ,SPI_I2S_FLAG_BSY) == SET && i < 30000) i++;*/
|
||||
SPI_Cmd(dev_cfg->mask.regs, DISABLE);
|
||||
SPI_Cmd(dev_cfg->level.regs, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Interrupt for half and full buffer transfer
|
||||
*/
|
||||
void PIOS_VIDEO_DMA_Handler(void)
|
||||
{
|
||||
if (DMA_GetFlagStatus(DMA1_Stream7,DMA_FLAG_TCIF7)) { // transfer completed load next line
|
||||
DMA_ClearFlag(DMA1_Stream7,DMA_FLAG_TCIF7);
|
||||
//PIOS_LED_Off(LED2);
|
||||
/*if(gLineType == LINE_TYPE_GRAPHICS)
|
||||
// Handle flags from stream channel
|
||||
if (DMA_GetFlagStatus(dev_cfg->level.dma.tx.channel,DMA_FLAG_TCIF5)) { // whole double buffer filled
|
||||
DMA_ClearFlag(dev_cfg->level.dma.tx.channel,DMA_FLAG_TCIF5);
|
||||
if(gActiveLine < GRAPHICS_HEIGHT)
|
||||
{
|
||||
// Load new line
|
||||
flush_spi();
|
||||
stop_hsync_timers();
|
||||
|
||||
dev_cfg->pixel_timer.timer->CNT = dc;
|
||||
|
||||
prepare_line(gActiveLine);
|
||||
}
|
||||
else if(gActiveLine >= GRAPHICS_HEIGHT)
|
||||
{
|
||||
//last line completed
|
||||
flush_spi();
|
||||
stop_hsync_timers();
|
||||
|
||||
// STOP DMA, master first
|
||||
DMA_Cmd(dev_cfg->mask.dma.tx.channel, DISABLE);
|
||||
DMA_Cmd(dev_cfg->level.dma.tx.channel, DISABLE);
|
||||
DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel,(uint32_t)&disp_buffer_level[line],DMA_Memory_0);
|
||||
DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel,(uint32_t)&disp_buffer_mask[line],DMA_Memory_0);
|
||||
//DMA_ClearFlag(dev_cfg->mask.dma.tx.channel,DMA_FLAG_TCIF5); // <-- TODO: HARDCODED
|
||||
//DMA_ClearFlag(dev_cfg->level.dma.tx.channel,DMA_FLAG_TCIF5); // <-- TODO: HARDCODED
|
||||
DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel,BUFFER_LINE_LENGTH);
|
||||
DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel,BUFFER_LINE_LENGTH);
|
||||
}*/
|
||||
//PIOS_LED_Toggle(LED2);
|
||||
}
|
||||
gActiveLine++;
|
||||
}
|
||||
else if (DMA_GetFlagStatus(DMA1_Stream7,DMA_FLAG_HTIF7)) {
|
||||
DMA_ClearFlag(DMA1_Stream7,DMA_FLAG_HTIF7);
|
||||
else if (DMA_GetFlagStatus(dev_cfg->level.dma.tx.channel,DMA_FLAG_HTIF5)) {
|
||||
DMA_ClearFlag(dev_cfg->level.dma.tx.channel,DMA_FLAG_HTIF5);
|
||||
}
|
||||
else {
|
||||
|
||||
}
|
||||
|
||||
if (DMA_GetFlagStatus(DMA2_Stream5,DMA_FLAG_TCIF5)) { // whole double buffer filled
|
||||
DMA_ClearFlag(DMA2_Stream5,DMA_FLAG_TCIF5);
|
||||
//PIOS_LED_Toggle(LED3);
|
||||
}
|
||||
else if (DMA_GetFlagStatus(DMA2_Stream5,DMA_FLAG_HTIF5)) {
|
||||
DMA_ClearFlag(DMA2_Stream5,DMA_FLAG_HTIF5);
|
||||
}
|
||||
else {
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif /* PIOS_INCLUDE_VIDEO */
|
||||
|
@ -134,7 +134,7 @@ int32_t PIOS_TIM_InitChannels(uint32_t * tim_id, const struct pios_tim_channel *
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
break;
|
||||
case (uint32_t) GPIOC:
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
break;
|
||||
default:
|
||||
PIOS_Assert(0);
|
||||
|
@ -1,552 +1,553 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 24-January-2012
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F4xx devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f4xx_Clock_Configuration_V1.0.1.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*=============================================================================
|
||||
* Supported STM32F4xx device revision | Rev A
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 108000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 108000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 8000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 216
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 9
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* I2S input clock | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD(V) | 3.3
|
||||
*-----------------------------------------------------------------------------
|
||||
* Main regulator output voltage | Scale2 mode
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 3
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | OFF
|
||||
*-----------------------------------------------------------------------------
|
||||
* Instruction cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Data cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F4xx devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f4xx_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*=============================================================================
|
||||
* Supported STM32F4xx device revision | Rev A
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 168000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 168000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 8000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 10
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 420
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* I2S input clock | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD(V) | 3.3
|
||||
*-----------------------------------------------------------------------------
|
||||
* Main regulator output voltage | Scale1 mode
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 5
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | OFF
|
||||
*-----------------------------------------------------------------------------
|
||||
* Instruction cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Data cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Enabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM mounted
|
||||
on STM324xG_EVAL board as data memory */
|
||||
on STM324xG_EVAL board as data memory */
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/************************* PLL Parameters *************************************/
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
|
||||
#define PLL_M 4
|
||||
#define PLL_N 216
|
||||
#define PLL_M 10
|
||||
#define PLL_N 420
|
||||
|
||||
/* SYSCLK = PLL_VCO / PLL_P */
|
||||
#define PLL_P 4
|
||||
#define PLL_P 2
|
||||
|
||||
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
|
||||
#define PLL_Q 9
|
||||
#define PLL_Q 7
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 108000000;
|
||||
uint32_t SystemCoreClock = 168000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
SetSysClock();
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @Note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @Note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR &= (uint32_t)~(PWR_CR_VOS);
|
||||
|
||||
/* HCLK = SYSCLK / 1*/
|
||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 2*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
||||
|
||||
/* PCLK1 = HCLK / 4*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
||||
|
||||
/* Configure the main PLL */
|
||||
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||
|
||||
/* Enable the main PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till the main PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till the main PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
|
||||
/* HCLK = SYSCLK / 1*/
|
||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 2*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
||||
|
||||
/* PCLK1 = HCLK / 4*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
||||
|
||||
/* Configure the main PLL */
|
||||
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||
|
||||
/* Enable the main PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till the main PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till the main PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
|
||||
* before jump to __main
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
|
||||
* before jump to __main
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f4xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on STM324xG_EVAL board
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f4xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on STM324xG_EVAL board
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/*
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
+ SRAM pins assignment +
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
|
||||
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
|
||||
| PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
|
||||
| PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
|
||||
| PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
|
||||
| PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
|
||||
| PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
|
||||
| PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
|
||||
| PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
|
||||
| PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
|
||||
| PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
|
||||
| PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
|
||||
| | PE15 <-> FSMC_D12 |
|
||||
+-------------------+--------------------+
|
||||
*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR = 0x00000078;
|
||||
|
||||
/* Connect PDx pins to FSMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00cc00cc;
|
||||
GPIOD->AFR[1] = 0xcc0ccccc;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xaaaa0a0a;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xffff0f0f;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FSMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xc00cc0cc;
|
||||
GPIOE->AFR[1] = 0xcccccccc;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xaaaa828a;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xffffc3cf;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00cccccc;
|
||||
GPIOF->AFR[1] = 0xcccc0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xaa000aaa;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xff000fff;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00cccccc;
|
||||
GPIOG->AFR[1] = 0x000000c0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00080aaa;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000c0fff;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR = 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001015;
|
||||
FSMC_Bank1->BTCR[3] = 0x00010603;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
/*
|
||||
Bank1_SRAM2 is configured as follow:
|
||||
|
||||
p.FSMC_AddressSetupTime = 3;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 6;
|
||||
p.FSMC_BusTurnAroundDuration = 1;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
*/
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/*
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
+ SRAM pins assignment +
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
|
||||
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
|
||||
| PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
|
||||
| PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
|
||||
| PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
|
||||
| PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
|
||||
| PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
|
||||
| PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
|
||||
| PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
|
||||
| PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
|
||||
| PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
|
||||
| PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
|
||||
| | PE15 <-> FSMC_D12 |
|
||||
+-------------------+--------------------+
|
||||
*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR = 0x00000078;
|
||||
|
||||
/* Connect PDx pins to FSMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00cc00cc;
|
||||
GPIOD->AFR[1] = 0xcc0ccccc;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xaaaa0a0a;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xffff0f0f;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FSMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xc00cc0cc;
|
||||
GPIOE->AFR[1] = 0xcccccccc;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xaaaa828a;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xffffc3cf;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00cccccc;
|
||||
GPIOF->AFR[1] = 0xcccc0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xaa000aaa;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xff000fff;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00cccccc;
|
||||
GPIOG->AFR[1] = 0x000000c0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00080aaa;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000c0fff;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR = 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001015;
|
||||
FSMC_Bank1->BTCR[3] = 0x00010603;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
/*
|
||||
Bank1_SRAM2 is configured as follow:
|
||||
|
||||
p.FSMC_AddressSetupTime = 3;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 6;
|
||||
p.FSMC_BusTurnAroundDuration = 1;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
*/
|
||||
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
@ -32,7 +32,6 @@
|
||||
#define PIOS_HCSR04_H
|
||||
|
||||
/* Public Functions */
|
||||
extern void PIOS_HCSR04_Init(void);
|
||||
extern int32_t PIOS_HCSR04_Get(void);
|
||||
extern int32_t PIOS_HCSR04_Completed(void);
|
||||
extern void PIOS_HCSR04_Trigger(void);
|
||||
|
55
flight/PiOS/inc/pios_hcsr04_priv.h
Normal file
55
flight/PiOS/inc/pios_hcsr04_priv.h
Normal file
@ -0,0 +1,55 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @addtogroup PIOS PIOS Core hardware abstraction layer
|
||||
* @{
|
||||
* @addtogroup PIOS_SERVO Servo Functions
|
||||
* @brief PIOS interface to read and write from servo PWM ports
|
||||
* @{
|
||||
*
|
||||
* @file pios_servo_priv.h
|
||||
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
|
||||
* @brief Servo private structures.
|
||||
* @see The GNU Public License (GPL) Version 3
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef PIOS_HCSR04_PRIV_H
|
||||
#define PIOS_HCSR04_PRIV_H
|
||||
|
||||
#include <pios.h>
|
||||
#include <pios_stm32.h>
|
||||
|
||||
#include <pios_tim_priv.h>
|
||||
|
||||
struct pios_hcsr04_cfg {
|
||||
TIM_ICInitTypeDef tim_ic_init;
|
||||
const struct pios_tim_channel * channels;
|
||||
uint8_t num_channels;
|
||||
struct stm32_gpio trigger;
|
||||
};
|
||||
|
||||
extern const struct pios_rcvr_driver pios_pwm_rcvr_driver;
|
||||
|
||||
extern int32_t PIOS_HCSR04_Init(uint32_t * pwm_id, const struct pios_hcsr04_cfg * cfg);
|
||||
|
||||
#endif /* PIOS_HCSR04_PRIV_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
* @}
|
||||
*/
|
@ -42,12 +42,10 @@ struct pios_video_cfg {
|
||||
const struct pios_exti_cfg * hsync;
|
||||
const struct pios_exti_cfg * vsync;
|
||||
|
||||
/*struct stm32_exti hsync;
|
||||
struct stm32_exti vsync;
|
||||
struct stm32_gpio hsync_io;
|
||||
struct stm32_gpio vsync_io;
|
||||
struct stm32_irq hsync_irq;
|
||||
struct stm32_irq vsync_irq;*/
|
||||
struct pios_tim_channel pixel_timer;
|
||||
struct pios_tim_channel hsync_capture;
|
||||
|
||||
TIM_OCInitTypeDef tim_oc_init;
|
||||
};
|
||||
|
||||
// Time vars
|
||||
@ -65,20 +63,21 @@ extern bool PIOS_Hsync_ISR();
|
||||
extern bool PIOS_Vsync_ISR();
|
||||
|
||||
// First OSD line
|
||||
#define GRAPHICS_LINE 32
|
||||
#define GRAPHICS_LINE 25
|
||||
|
||||
//top/left deadband
|
||||
#define GRAPHICS_HDEADBAND 32
|
||||
#define GRAPHICS_HDEADBAND 80
|
||||
#define GRAPHICS_VDEADBAND 0
|
||||
|
||||
#define PAL
|
||||
|
||||
// Real OSD size
|
||||
#ifdef PAL
|
||||
#define GRAPHICS_WIDTH_REAL (336+GRAPHICS_HDEADBAND)
|
||||
//#define GRAPHICS_WIDTH_REAL (352+GRAPHICS_HDEADBAND)
|
||||
#define GRAPHICS_WIDTH_REAL 416
|
||||
#define GRAPHICS_HEIGHT_REAL (270+GRAPHICS_VDEADBAND)
|
||||
#else
|
||||
#define GRAPHICS_WIDTH_REAL (320+GRAPHICS_HDEADBAND)
|
||||
#define GRAPHICS_WIDTH_REAL (312+GRAPHICS_HDEADBAND)
|
||||
#define GRAPHICS_HEIGHT_REAL (225+GRAPHICS_VDEADBAND)
|
||||
#endif
|
||||
|
||||
|
4
flight/Project/gdb/osd
Normal file
4
flight/Project/gdb/osd
Normal file
@ -0,0 +1,4 @@
|
||||
define connect
|
||||
target remote localhost:3333
|
||||
file ./build/fw_osd/fw_osd.elf
|
||||
end
|
@ -59,6 +59,8 @@ uint32_t pios_rcvr_group_map[MANUALCONTROLSETTINGS_CHANNELGROUPS_NONE];
|
||||
#define PIOS_COM_BRIDGE_RX_BUF_LEN 65
|
||||
#define PIOS_COM_BRIDGE_TX_BUF_LEN 12
|
||||
|
||||
#define PIOS_COM_HKOSD_TX_BUF_LEN 22
|
||||
|
||||
#if defined(PIOS_INCLUDE_DEBUG_CONSOLE)
|
||||
#define PIOS_COM_DEBUGCONSOLE_TX_BUF_LEN 40
|
||||
uint32_t pios_com_debug_id;
|
||||
@ -69,6 +71,7 @@ uint32_t pios_com_telem_usb_id;
|
||||
uint32_t pios_com_vcp_id;
|
||||
uint32_t pios_com_gps_id;
|
||||
uint32_t pios_com_bridge_id;
|
||||
uint32_t pios_com_hkosd_id;
|
||||
|
||||
uint32_t pios_usb_rctx_id;
|
||||
|
||||
@ -526,6 +529,22 @@ void PIOS_Board_Init(void) {
|
||||
}
|
||||
}
|
||||
break;
|
||||
case HWSETTINGS_CC_MAINPORT_OSDHK:
|
||||
{
|
||||
uint32_t pios_usart_hkosd_id;
|
||||
if (PIOS_USART_Init(&pios_usart_hkosd_id, &pios_usart_hkosd_main_cfg)) {
|
||||
PIOS_Assert(0);
|
||||
}
|
||||
|
||||
uint8_t * tx_buffer = (uint8_t *) pvPortMalloc(PIOS_COM_HKOSD_TX_BUF_LEN);
|
||||
PIOS_Assert(tx_buffer);
|
||||
if (PIOS_COM_Init(&pios_com_hkosd_id, &pios_usart_com_driver, pios_usart_hkosd_id,
|
||||
NULL, 0,
|
||||
tx_buffer, PIOS_COM_HKOSD_TX_BUF_LEN)) {
|
||||
PIOS_Assert(0);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Configure the flexi port */
|
||||
@ -675,6 +694,22 @@ void PIOS_Board_Init(void) {
|
||||
}
|
||||
#endif /* PIOS_INCLUDE_I2C */
|
||||
break;
|
||||
case HWSETTINGS_CC_FLEXIPORT_OSDHK:
|
||||
{
|
||||
uint32_t pios_usart_hkosd_id;
|
||||
if (PIOS_USART_Init(&pios_usart_hkosd_id, &pios_usart_hkosd_flexi_cfg)) {
|
||||
PIOS_Assert(0);
|
||||
}
|
||||
|
||||
uint8_t * tx_buffer = (uint8_t *) pvPortMalloc(PIOS_COM_HKOSD_TX_BUF_LEN);
|
||||
PIOS_Assert(tx_buffer);
|
||||
if (PIOS_COM_Init(&pios_com_hkosd_id, &pios_usart_com_driver, pios_usart_hkosd_id,
|
||||
NULL, 0,
|
||||
tx_buffer, PIOS_COM_HKOSD_TX_BUF_LEN)) {
|
||||
PIOS_Assert(0);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Configure the rcvr port */
|
||||
@ -683,6 +718,12 @@ void PIOS_Board_Init(void) {
|
||||
|
||||
switch (hwsettings_rcvrport) {
|
||||
case HWSETTINGS_CC_RCVRPORT_DISABLED:
|
||||
#if defined(PIOS_INCLUDE_HCSR04)
|
||||
{
|
||||
uint32_t pios_hcsr04_id;
|
||||
PIOS_HCSR04_Init(&pios_hcsr04_id, &pios_hcsr04_cfg);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
case HWSETTINGS_CC_RCVRPORT_PWM:
|
||||
#if defined(PIOS_INCLUDE_PWM)
|
||||
|
@ -98,7 +98,7 @@
|
||||
/* PIOS common peripherals */
|
||||
#define PIOS_INCLUDE_LED
|
||||
#define PIOS_INCLUDE_IAP
|
||||
/* #define PIOS_INCLUDE_SERVO */
|
||||
#define PIOS_INCLUDE_SERVO
|
||||
/* #define PIOS_INCLUDE_I2C_ESC */
|
||||
/* #define PIOS_INCLUDE_OVERO */
|
||||
/* #define PIOS_OVERO_SPI */
|
||||
|
@ -85,8 +85,8 @@ void PIOS_ADC_DMC_irq_handler(void)
|
||||
static void Clock(uint32_t spektrum_id);
|
||||
|
||||
|
||||
#define PIOS_COM_TELEM_RF_RX_BUF_LEN 512
|
||||
#define PIOS_COM_TELEM_RF_TX_BUF_LEN 512
|
||||
#define PIOS_COM_TELEM_RF_RX_BUF_LEN 128
|
||||
#define PIOS_COM_TELEM_RF_TX_BUF_LEN 128
|
||||
|
||||
#define PIOS_COM_AUX_RX_BUF_LEN 512
|
||||
#define PIOS_COM_AUX_TX_BUF_LEN 512
|
||||
@ -104,7 +104,42 @@ uint32_t pios_com_gps_id;
|
||||
uint32_t pios_com_telem_usb_id;
|
||||
uint32_t pios_com_telem_rf_id;
|
||||
|
||||
/**
|
||||
* TIM3 is triggered by the HSYNC signal into its ETR line and will divide the
|
||||
* APB1_CLOCK to generate a pixel clock that is used by the SPI CLK lines.
|
||||
* TIM4 will be synced to it and will divide by that times the pixel width to
|
||||
* fire an IRQ when the last pixel of the line has been output. Then the timer will
|
||||
* be rearmed and wait for the next HSYNC signal.
|
||||
* The critical timing detail is that the task be _DISABLED_ at the end of the line
|
||||
* before an extra pixel is clocked out
|
||||
* or we will need to configure the DMA task per line
|
||||
*/
|
||||
#include "pios_tim_priv.h"
|
||||
#define NTSC_PX_CLOCK 6797088
|
||||
#define PAL_PX_CLOCK 6750130
|
||||
#define PX_PERIOD ((PIOS_PERIPHERAL_APB1_CLOCK / NTSC_PX_CLOCK) + 1)
|
||||
#define LINE_PERIOD PX_PERIOD * GRAPHICS_WIDTH
|
||||
|
||||
static const TIM_TimeBaseInitTypeDef tim_4_time_base = {
|
||||
.TIM_Prescaler = 0, //PIOS_PERIPHERAL_APB1_CLOCK,
|
||||
.TIM_ClockDivision = TIM_CKD_DIV1,
|
||||
.TIM_CounterMode = TIM_CounterMode_Up,
|
||||
.TIM_Period = LINE_PERIOD - 1,
|
||||
.TIM_RepetitionCounter = 0x0000,
|
||||
};
|
||||
|
||||
const static struct pios_tim_clock_cfg pios_tim4_cfg = {
|
||||
.timer = TIM4,
|
||||
.time_base_init = &tim_4_time_base,
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = TIM4_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
void PIOS_Board_Init(void) {
|
||||
|
||||
@ -119,9 +154,11 @@ void PIOS_Board_Init(void) {
|
||||
PIOS_Assert(0);
|
||||
}
|
||||
|
||||
#if defined(PIOS_INCLUDE_SDCARD)
|
||||
/* Enable and mount the SDCard */
|
||||
PIOS_SDCARD_Init(pios_spi_sdcard_id);
|
||||
PIOS_SDCARD_MountFS(0);
|
||||
#endif
|
||||
#endif /* PIOS_INCLUDE_SPI */
|
||||
|
||||
/* Initialize UAVObject libraries */
|
||||
@ -148,6 +185,7 @@ void PIOS_Board_Init(void) {
|
||||
AlarmsSet(SYSTEMALARMS_ALARM_BOOTFAULT, SYSTEMALARMS_ALARM_CRITICAL);
|
||||
}
|
||||
|
||||
|
||||
#if defined(PIOS_INCLUDE_RTC)
|
||||
/* Initialize the real-time clock and its associated tick */
|
||||
PIOS_RTC_Init(&pios_rtc_main_cfg);
|
||||
@ -403,6 +441,10 @@ void PIOS_Board_Init(void) {
|
||||
#endif
|
||||
|
||||
#if defined(PIOS_INCLUDE_VIDEO)
|
||||
PIOS_TIM_InitClock(&tim_8_cfg);
|
||||
PIOS_Servo_Init(&pios_servo_cfg);
|
||||
// Start the pixel and line clock counter
|
||||
//PIOS_TIM_InitClock(&pios_tim4_cfg);
|
||||
PIOS_Video_Init(&pios_video_cfg);
|
||||
#endif
|
||||
}
|
||||
|
@ -44,8 +44,9 @@ MODULES += FirmwareIAP
|
||||
MODULES += Radio
|
||||
MODULES += PathPlanner
|
||||
MODULES += FixedWingPathFollower
|
||||
MODULES += Osd/OsdHk
|
||||
MODULES += Telemetry
|
||||
#MODULES += VtolPathFollower ## OP-700: VtolPathFollower disabled because its currently unsafe - remove this line once Sambas code has been merged
|
||||
MODULES += VtolPathFollower ## OP-700: VtolPathFollower disabled because its currently unsafe - remove this line once Sambas code has been merged
|
||||
|
||||
OPTMODULES =
|
||||
|
||||
|
@ -209,6 +209,9 @@ uint32_t pios_rcvr_group_map[MANUALCONTROLSETTINGS_CHANNELGROUPS_NONE];
|
||||
#define PIOS_COM_RFM22B_RF_RX_BUF_LEN 512
|
||||
#define PIOS_COM_RFM22B_RF_TX_BUF_LEN 512
|
||||
|
||||
#define PIOS_COM_HKOSD_RX_BUF_LEN 22
|
||||
#define PIOS_COM_HKOSD_TX_BUF_LEN 22
|
||||
|
||||
#if defined(PIOS_INCLUDE_DEBUG_CONSOLE)
|
||||
#define PIOS_COM_DEBUGCONSOLE_TX_BUF_LEN 40
|
||||
uint32_t pios_com_debug_id;
|
||||
@ -219,6 +222,7 @@ uint32_t pios_com_telem_usb_id = 0;
|
||||
uint32_t pios_com_telem_rf_id = 0;
|
||||
uint32_t pios_com_bridge_id = 0;
|
||||
uint32_t pios_com_overo_id = 0;
|
||||
uint32_t pios_com_hkosd_id = 0;
|
||||
#if defined(PIOS_INCLUDE_RFM22B)
|
||||
uint32_t pios_rfm22b_id = 0;
|
||||
#endif
|
||||
@ -549,7 +553,9 @@ void PIOS_Board_Init(void) {
|
||||
case HWSETTINGS_RM_MAINPORT_COMBRIDGE:
|
||||
PIOS_Board_configure_com(&pios_usart_main_cfg, PIOS_COM_BRIDGE_RX_BUF_LEN, PIOS_COM_BRIDGE_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_bridge_id);
|
||||
break;
|
||||
|
||||
case HWSETTINGS_RM_MAINPORT_OSDHK:
|
||||
PIOS_Board_configure_com(&pios_usart_hkosd_main_cfg, PIOS_COM_HKOSD_RX_BUF_LEN, PIOS_COM_HKOSD_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_hkosd_id);
|
||||
break;
|
||||
} /* hwsettings_rm_mainport */
|
||||
|
||||
if (hwsettings_mainport != HWSETTINGS_RM_MAINPORT_SBUS) {
|
||||
@ -612,7 +618,11 @@ void PIOS_Board_Init(void) {
|
||||
case HWSETTINGS_RM_FLEXIPORT_COMBRIDGE:
|
||||
PIOS_Board_configure_com(&pios_usart_flexi_cfg, PIOS_COM_BRIDGE_RX_BUF_LEN, PIOS_COM_BRIDGE_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_bridge_id);
|
||||
break;
|
||||
} /* hwsettings_rv_flexiport */
|
||||
case HWSETTINGS_RM_FLEXIPORT_OSDHK:
|
||||
PIOS_Board_configure_com(&pios_usart_hkosd_flexi_cfg, PIOS_COM_HKOSD_RX_BUF_LEN, PIOS_COM_HKOSD_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_hkosd_id);
|
||||
break;
|
||||
} /* hwsettings_rm_flexiport */
|
||||
|
||||
|
||||
/* Initalize the RFM22B radio COM device. */
|
||||
#if defined(PIOS_INCLUDE_RFM22B)
|
||||
|
@ -292,12 +292,17 @@ uint32_t pios_rcvr_group_map[MANUALCONTROLSETTINGS_CHANNELGROUPS_NONE];
|
||||
#define PIOS_COM_AUX_RX_BUF_LEN 512
|
||||
#define PIOS_COM_AUX_TX_BUF_LEN 512
|
||||
|
||||
#define PIOS_COM_HKOSD_RX_BUF_LEN 22
|
||||
#define PIOS_COM_HKOSD_TX_BUF_LEN 22
|
||||
|
||||
|
||||
uint32_t pios_com_aux_id = 0;
|
||||
uint32_t pios_com_gps_id = 0;
|
||||
uint32_t pios_com_telem_usb_id = 0;
|
||||
uint32_t pios_com_telem_rf_id = 0;
|
||||
uint32_t pios_com_bridge_id = 0;
|
||||
uint32_t pios_com_overo_id = 0;
|
||||
uint32_t pios_com_hkosd_id = 0;
|
||||
|
||||
/*
|
||||
* Setup a com port based on the passed cfg, driver and buffer sizes. tx size of -1 make the port rx only
|
||||
@ -617,6 +622,10 @@ void PIOS_Board_Init(void) {
|
||||
case HWSETTINGS_RV_AUXPORT_COMBRIDGE:
|
||||
PIOS_Board_configure_com(&pios_usart_aux_cfg, PIOS_COM_BRIDGE_RX_BUF_LEN, PIOS_COM_BRIDGE_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_bridge_id);
|
||||
break;
|
||||
case HWSETTINGS_RV_AUXPORT_OSDHK:
|
||||
PIOS_Board_configure_com(&pios_usart_hkosd_aux_cfg, PIOS_COM_HKOSD_RX_BUF_LEN, PIOS_COM_HKOSD_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_hkosd_id);
|
||||
break;
|
||||
|
||||
} /* hwsettings_rv_auxport */
|
||||
/* Configure AUXSbusPort */
|
||||
//TODO: ensure that the serial invertion pin is setted correctly
|
||||
@ -679,6 +688,9 @@ void PIOS_Board_Init(void) {
|
||||
case HWSETTINGS_RV_AUXSBUSPORT_COMBRIDGE:
|
||||
PIOS_Board_configure_com(&pios_usart_auxsbus_cfg, PIOS_COM_BRIDGE_RX_BUF_LEN, PIOS_COM_BRIDGE_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_bridge_id);
|
||||
break;
|
||||
case HWSETTINGS_RV_AUXSBUSPORT_OSDHK:
|
||||
PIOS_Board_configure_com(&pios_usart_hkosd_auxsbus_cfg, PIOS_COM_HKOSD_RX_BUF_LEN, PIOS_COM_HKOSD_TX_BUF_LEN, &pios_usart_com_driver, &pios_com_hkosd_id);
|
||||
break;
|
||||
} /* hwsettings_rv_auxport */
|
||||
|
||||
/* Configure FlexiPort */
|
||||
@ -797,6 +809,15 @@ void PIOS_Board_Init(void) {
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(PIOS_INCLUDE_HCSR04)
|
||||
{
|
||||
PIOS_TIM_InitClock(&tim_8_cfg);
|
||||
uint32_t pios_hcsr04_id;
|
||||
PIOS_HCSR04_Init(&pios_hcsr04_id, &pios_hcsr04_cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(PIOS_INCLUDE_GCSRCVR)
|
||||
GCSReceiverInitialize();
|
||||
uint32_t pios_gcsrcvr_id;
|
||||
|
@ -1083,6 +1083,82 @@ static const struct pios_sbus_cfg pios_sbus_cfg = {
|
||||
|
||||
#endif /* PIOS_INCLUDE_SBUS */
|
||||
|
||||
/*
|
||||
* HK OSD
|
||||
*/
|
||||
static const struct pios_usart_cfg pios_usart_hkosd_main_cfg = {
|
||||
.regs = USART1,
|
||||
.init = {
|
||||
.USART_BaudRate = 57600,
|
||||
.USART_WordLength = USART_WordLength_8b,
|
||||
.USART_Parity = USART_Parity_No,
|
||||
.USART_StopBits = USART_StopBits_1,
|
||||
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
|
||||
.USART_Mode = USART_Mode_Rx | USART_Mode_Tx,
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = USART1_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
.rx = {
|
||||
.gpio = GPIOA,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_10,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_IPU,
|
||||
},
|
||||
},
|
||||
.tx = {
|
||||
.gpio = GPIOA,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_9,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF_PP,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pios_usart_cfg pios_usart_hkosd_flexi_cfg = {
|
||||
.regs = USART3,
|
||||
.init = {
|
||||
.USART_BaudRate = 57600,
|
||||
.USART_WordLength = USART_WordLength_8b,
|
||||
.USART_Parity = USART_Parity_No,
|
||||
.USART_StopBits = USART_StopBits_1,
|
||||
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
|
||||
.USART_Mode = USART_Mode_Rx | USART_Mode_Tx,
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = USART3_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
.rx = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_11,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_IPU,
|
||||
},
|
||||
},
|
||||
.tx = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_10,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF_PP,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
#endif /* PIOS_INCLUDE_USART */
|
||||
|
||||
#if defined(PIOS_INCLUDE_COM)
|
||||
@ -1224,6 +1300,50 @@ const struct pios_pwm_cfg pios_pwm_with_ppm_cfg = {
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* SONAR Inputs
|
||||
*/
|
||||
#if defined(PIOS_INCLUDE_HCSR04)
|
||||
#include <pios_hcsr04_priv.h>
|
||||
|
||||
static const struct pios_tim_channel pios_tim_hcsr04_port_all_channels[] = {
|
||||
{
|
||||
.timer = TIM3,
|
||||
.timer_chan = TIM_Channel_2,
|
||||
.pin = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_5,
|
||||
.GPIO_Mode = GPIO_Mode_IPD,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
},
|
||||
},
|
||||
.remap = GPIO_PartialRemap_TIM3,
|
||||
},
|
||||
};
|
||||
|
||||
const struct pios_hcsr04_cfg pios_hcsr04_cfg = {
|
||||
.tim_ic_init = {
|
||||
.TIM_ICPolarity = TIM_ICPolarity_Rising,
|
||||
.TIM_ICSelection = TIM_ICSelection_DirectTI,
|
||||
.TIM_ICPrescaler = TIM_ICPSC_DIV1,
|
||||
.TIM_ICFilter = 0x0,
|
||||
},
|
||||
.channels = pios_tim_hcsr04_port_all_channels,
|
||||
.num_channels = NELEMENTS(pios_tim_hcsr04_port_all_channels),
|
||||
.trigger = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_6,
|
||||
.GPIO_Mode = GPIO_Mode_Out_PP,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(PIOS_INCLUDE_I2C)
|
||||
|
||||
#include <pios_i2c_priv.h>
|
||||
|
@ -35,9 +35,9 @@
|
||||
static const struct pios_led pios_leds[] = {
|
||||
[PIOS_LED_HEARTBEAT] = {
|
||||
.pin = {
|
||||
.gpio = GPIOC,
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_5,
|
||||
.GPIO_Pin = GPIO_Pin_0,
|
||||
.GPIO_Speed = GPIO_Speed_50MHz,
|
||||
.GPIO_Mode = GPIO_Mode_OUT,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
@ -49,7 +49,7 @@ static const struct pios_led pios_leds[] = {
|
||||
.pin = {
|
||||
.gpio = GPIOC,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_4,
|
||||
.GPIO_Pin = GPIO_Pin_5,
|
||||
.GPIO_Speed = GPIO_Speed_50MHz,
|
||||
.GPIO_Mode = GPIO_Mode_OUT,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
@ -202,6 +202,7 @@ void PIOS_SPI_sdcard_irq_handler(void)
|
||||
#include <pios_usart_priv.h>
|
||||
|
||||
#if defined(PIOS_INCLUDE_GPS)
|
||||
|
||||
/*
|
||||
* GPS USART
|
||||
*/
|
||||
@ -246,7 +247,6 @@ static const struct pios_usart_cfg pios_usart_gps_cfg = {
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* PIOS_INCLUDE_GPS */
|
||||
|
||||
#ifdef PIOS_INCLUDE_COM_AUX
|
||||
@ -521,14 +521,91 @@ const struct pios_usb_cdc_cfg pios_usb_cdc_cfg = {
|
||||
|
||||
#if defined(PIOS_INCLUDE_VIDEO)
|
||||
|
||||
static const TIM_TimeBaseInitTypeDef tim_8_time_base = {
|
||||
.TIM_Prescaler = (PIOS_PERIPHERAL_APB2_CLOCK / 1000000) - 1,
|
||||
.TIM_ClockDivision = TIM_CKD_DIV1,
|
||||
.TIM_CounterMode = TIM_CounterMode_Up,
|
||||
.TIM_Period = ((1000000 / 50000) - 1),
|
||||
.TIM_RepetitionCounter = 0x0000,
|
||||
};
|
||||
|
||||
static const struct pios_tim_clock_cfg tim_8_cfg = {
|
||||
.timer = TIM8,
|
||||
.time_base_init = &tim_8_time_base,
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = TIM8_CC_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* Pios servo configuration structures
|
||||
*/
|
||||
#include <pios_servo_priv.h>
|
||||
static const struct pios_tim_channel pios_tim_servoport_all_pins[] = {
|
||||
{
|
||||
.timer = TIM8,
|
||||
.timer_chan = TIM_Channel_3,
|
||||
.pin = {
|
||||
.gpio = GPIOC,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_8,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
.pin_source = GPIO_PinSource8,
|
||||
},
|
||||
.remap = GPIO_AF_TIM8,
|
||||
},
|
||||
{
|
||||
.timer = TIM8,
|
||||
.timer_chan = TIM_Channel_4,
|
||||
.pin = {
|
||||
.gpio = GPIOC,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_9,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
.pin_source = GPIO_PinSource9,
|
||||
},
|
||||
.remap = GPIO_AF_TIM8,
|
||||
},
|
||||
};
|
||||
|
||||
const struct pios_servo_cfg pios_servo_cfg = {
|
||||
.tim_oc_init = {
|
||||
.TIM_OCMode = TIM_OCMode_PWM1,
|
||||
.TIM_OutputState = TIM_OutputState_Enable,
|
||||
.TIM_OutputNState = TIM_OutputNState_Disable,
|
||||
.TIM_Pulse = 0,
|
||||
.TIM_OCPolarity = TIM_OCPolarity_High,
|
||||
.TIM_OCNPolarity = TIM_OCPolarity_High,
|
||||
.TIM_OCIdleState = TIM_OCIdleState_Reset,
|
||||
.TIM_OCNIdleState = TIM_OCNIdleState_Reset,
|
||||
},
|
||||
.channels = pios_tim_servoport_all_pins,
|
||||
.num_channels = NELEMENTS(pios_tim_servoport_all_pins),
|
||||
};
|
||||
|
||||
|
||||
|
||||
#include <pios_video.h>
|
||||
static const struct pios_exti_cfg pios_exti_hsync_cfg __exti_config = {
|
||||
.vector = PIOS_Hsync_ISR,
|
||||
.line = EXTI_Line2,
|
||||
.line = EXTI_Line7,
|
||||
.pin = {
|
||||
.gpio = GPIOD,
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_2,
|
||||
.GPIO_Pin = GPIO_Pin_7,
|
||||
.GPIO_Speed = GPIO_Speed_100MHz,
|
||||
.GPIO_Mode = GPIO_Mode_IN,
|
||||
.GPIO_OType = GPIO_OType_OD,
|
||||
@ -537,28 +614,30 @@ static const struct pios_exti_cfg pios_exti_hsync_cfg __exti_config = {
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = EXTI2_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = 0,
|
||||
.NVIC_IRQChannel = EXTI9_5_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGH,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
.exti = {
|
||||
.init = {
|
||||
.EXTI_Line = EXTI_Line2, // matches above GPIO pin
|
||||
.EXTI_Line = EXTI_Line7, // matches above GPIO pin
|
||||
.EXTI_Mode = EXTI_Mode_Interrupt,
|
||||
.EXTI_Trigger = EXTI_Trigger_Rising_Falling,
|
||||
//.EXTI_Trigger = EXTI_Trigger_Rising_Falling,
|
||||
.EXTI_Trigger = EXTI_Trigger_Falling,
|
||||
//.EXTI_Trigger = EXTI_Trigger_Rising,
|
||||
.EXTI_LineCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct pios_exti_cfg pios_exti_vsync_cfg __exti_config = {
|
||||
.vector = PIOS_Vsync_ISR,
|
||||
.line = EXTI_Line11,
|
||||
.line = EXTI_Line5,
|
||||
.pin = {
|
||||
.gpio = GPIOC,
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_11,
|
||||
.GPIO_Pin = GPIO_Pin_5,
|
||||
.GPIO_Speed = GPIO_Speed_100MHz,
|
||||
.GPIO_Mode = GPIO_Mode_IN,
|
||||
.GPIO_OType = GPIO_OType_OD,
|
||||
@ -567,7 +646,7 @@ static const struct pios_exti_cfg pios_exti_vsync_cfg __exti_config = {
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = EXTI15_10_IRQn,
|
||||
.NVIC_IRQChannel = EXTI9_5_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGH,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
@ -575,7 +654,7 @@ static const struct pios_exti_cfg pios_exti_vsync_cfg __exti_config = {
|
||||
},
|
||||
.exti = {
|
||||
.init = {
|
||||
.EXTI_Line = EXTI_Line11, // matches above GPIO pin
|
||||
.EXTI_Line = EXTI_Line5, // matches above GPIO pin
|
||||
.EXTI_Mode = EXTI_Mode_Interrupt,
|
||||
.EXTI_Trigger = EXTI_Trigger_Falling,
|
||||
.EXTI_LineCmd = ENABLE,
|
||||
@ -589,7 +668,7 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.regs = SPI3,
|
||||
.remap = GPIO_AF_SPI3,
|
||||
.init = {
|
||||
.SPI_Mode = SPI_Mode_Master,
|
||||
.SPI_Mode = SPI_Mode_Slave,
|
||||
.SPI_Direction = SPI_Direction_1Line_Tx,
|
||||
.SPI_DataSize = SPI_DataSize_8b,
|
||||
.SPI_NSS = SPI_NSS_Soft,
|
||||
@ -597,7 +676,7 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.SPI_CRCPolynomial = 7,
|
||||
.SPI_CPOL = SPI_CPOL_Low,
|
||||
.SPI_CPHA = SPI_CPHA_2Edge,
|
||||
.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4,
|
||||
.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2,
|
||||
},
|
||||
.use_crc = false,
|
||||
.dma = {
|
||||
@ -606,12 +685,11 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.flags = (DMA_IT_TCIF7),
|
||||
.init = {
|
||||
.NVIC_IRQChannel = DMA1_Stream7_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = 0,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGH,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
|
||||
.rx = {},
|
||||
.tx = {
|
||||
.channel = DMA1_Stream7,
|
||||
@ -626,9 +704,9 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.DMA_MemoryDataSize = DMA_MemoryDataSize_Word,
|
||||
.DMA_Mode = DMA_Mode_Normal,
|
||||
.DMA_Priority = DMA_Priority_VeryHigh,
|
||||
.DMA_FIFOMode = DMA_FIFOMode_Disable,
|
||||
.DMA_FIFOMode = DMA_FIFOMode_Enable,
|
||||
.DMA_FIFOThreshold = DMA_FIFOThreshold_Full,
|
||||
.DMA_MemoryBurst = DMA_MemoryBurst_Single,
|
||||
.DMA_MemoryBurst = DMA_MemoryBurst_INC4,
|
||||
.DMA_PeripheralBurst = DMA_PeripheralBurst_Single,
|
||||
},
|
||||
},
|
||||
@ -653,16 +731,7 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.GPIO_PuPd = GPIO_PuPd_NOPULL
|
||||
},
|
||||
},
|
||||
.mosi = {
|
||||
.gpio = GPIOC,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_12,
|
||||
.GPIO_Speed = GPIO_Speed_50MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_NOPULL
|
||||
},
|
||||
},
|
||||
.mosi = {},
|
||||
.slave_count = 1,
|
||||
},
|
||||
.level = {
|
||||
@ -685,12 +754,11 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.flags = (DMA_IT_TCIF5),
|
||||
.init = {
|
||||
.NVIC_IRQChannel = DMA2_Stream5_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGH,
|
||||
.NVIC_IRQChannelPreemptionPriority = 0,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
|
||||
.rx = {},
|
||||
.tx = {
|
||||
.channel = DMA2_Stream5,
|
||||
@ -705,9 +773,9 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.DMA_MemoryDataSize = DMA_MemoryDataSize_Word,
|
||||
.DMA_Mode = DMA_Mode_Normal,
|
||||
.DMA_Priority = DMA_Priority_VeryHigh,
|
||||
.DMA_FIFOMode = DMA_FIFOMode_Disable,
|
||||
.DMA_FIFOMode = DMA_FIFOMode_Enable,
|
||||
.DMA_FIFOThreshold = DMA_FIFOThreshold_Full,
|
||||
.DMA_MemoryBurst = DMA_MemoryBurst_Single,
|
||||
.DMA_MemoryBurst = DMA_MemoryBurst_INC4,
|
||||
.DMA_PeripheralBurst = DMA_PeripheralBurst_Single,
|
||||
},
|
||||
},
|
||||
@ -732,23 +800,56 @@ static const struct pios_video_cfg pios_video_cfg = {
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
.mosi = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_5,
|
||||
.GPIO_Speed = GPIO_Speed_50MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
.mosi = {},
|
||||
.slave_count = 1,
|
||||
|
||||
},
|
||||
/////////////////
|
||||
|
||||
.hsync = &pios_exti_hsync_cfg,
|
||||
.vsync = &pios_exti_vsync_cfg,
|
||||
|
||||
.pixel_timer = {
|
||||
.timer = TIM4,
|
||||
.timer_chan = TIM_Channel_1,
|
||||
.pin = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_6,
|
||||
.GPIO_Speed = GPIO_Speed_100MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
.pin_source = GPIO_PinSource6,
|
||||
},
|
||||
.remap = GPIO_AF_TIM4,
|
||||
},
|
||||
.hsync_capture = {
|
||||
.timer = TIM4,
|
||||
.timer_chan = TIM_Channel_2,
|
||||
.pin = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_7,
|
||||
.GPIO_Speed = GPIO_Speed_100MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
.pin_source = GPIO_PinSource7,
|
||||
},
|
||||
.remap = GPIO_AF_TIM4,
|
||||
},
|
||||
.tim_oc_init = {
|
||||
.TIM_OCMode = TIM_OCMode_PWM1,
|
||||
.TIM_OutputState = TIM_OutputState_Enable,
|
||||
.TIM_OutputNState = TIM_OutputNState_Disable,
|
||||
.TIM_Pulse = 1,
|
||||
.TIM_OCPolarity = TIM_OCPolarity_High,
|
||||
.TIM_OCNPolarity = TIM_OCPolarity_High,
|
||||
.TIM_OCIdleState = TIM_OCIdleState_Reset,
|
||||
.TIM_OCNIdleState = TIM_OCNIdleState_Reset,
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
|
@ -1020,7 +1020,7 @@ static const struct pios_dsm_cfg pios_dsm_flexi_cfg = {
|
||||
|
||||
static const struct pios_usart_cfg pios_usart_sbus_auxsbus_cfg = {
|
||||
.regs = UART4,
|
||||
.remap = GPIO_AF_UART4,
|
||||
.remap = GPIO_AF_UART4,
|
||||
.init = {
|
||||
.USART_BaudRate = 100000,
|
||||
.USART_WordLength = USART_WordLength_8b,
|
||||
@ -1078,6 +1078,91 @@ static const struct pios_sbus_cfg pios_sbus_cfg = {
|
||||
|
||||
#endif /* PIOS_INCLUDE_SBUS */
|
||||
|
||||
/*
|
||||
* HK OSD
|
||||
*/
|
||||
static const struct pios_usart_cfg pios_usart_hkosd_auxsbus_cfg = {
|
||||
.regs = UART4,
|
||||
.remap = GPIO_AF_UART4,
|
||||
.init = {
|
||||
.USART_BaudRate = 57600,
|
||||
.USART_WordLength = USART_WordLength_8b,
|
||||
.USART_Parity = USART_Parity_No,
|
||||
.USART_StopBits = USART_StopBits_1,
|
||||
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
|
||||
.USART_Mode = USART_Mode_Rx | USART_Mode_Tx,
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = UART4_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
.rx = {
|
||||
.gpio = GPIOA,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_1,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
.tx = {
|
||||
.gpio = GPIOA,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_0,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pios_usart_cfg pios_usart_hkosd_aux_cfg = {
|
||||
.regs = USART6,
|
||||
.remap = GPIO_AF_USART6,
|
||||
.init = {
|
||||
.USART_BaudRate = 57600,
|
||||
.USART_WordLength = USART_WordLength_8b,
|
||||
.USART_Parity = USART_Parity_No,
|
||||
.USART_StopBits = USART_StopBits_1,
|
||||
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
|
||||
.USART_Mode = USART_Mode_Rx | USART_Mode_Tx,
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = USART6_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
.rx = {
|
||||
.gpio = GPIOC,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_7,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
.tx = {
|
||||
.gpio = GPIOC,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_6,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#if defined(PIOS_INCLUDE_COM)
|
||||
|
||||
#include <pios_com_priv.h>
|
||||
@ -1363,7 +1448,15 @@ static const TIM_TimeBaseInitTypeDef tim_1_time_base = {
|
||||
.TIM_RepetitionCounter = 0x0000,
|
||||
};
|
||||
|
||||
// Set up timers that only have inputs on APB2
|
||||
static const TIM_TimeBaseInitTypeDef tim_8_time_base = {
|
||||
.TIM_Prescaler = (PIOS_PERIPHERAL_APB2_CLOCK / 1000000) - 1,
|
||||
.TIM_ClockDivision = TIM_CKD_DIV1,
|
||||
.TIM_CounterMode = TIM_CounterMode_Up,
|
||||
.TIM_Period = 0xFFFF,
|
||||
.TIM_RepetitionCounter = 0x0000,
|
||||
};
|
||||
|
||||
// Set up timers that only have inputs on APB1
|
||||
static const TIM_TimeBaseInitTypeDef tim_4_time_base = {
|
||||
.TIM_Prescaler = (PIOS_PERIPHERAL_APB1_CLOCK / 1000000) - 1,
|
||||
.TIM_ClockDivision = TIM_CKD_DIV1,
|
||||
@ -1415,6 +1508,19 @@ static const struct pios_tim_clock_cfg tim_5_cfg = {
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pios_tim_clock_cfg tim_8_cfg = {
|
||||
.timer = TIM8,
|
||||
.time_base_init = &tim_8_time_base,
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = TIM8_CC_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pios_tim_clock_cfg tim_9_cfg = {
|
||||
.timer = TIM9,
|
||||
.time_base_init = &tim_9_10_11_time_base,
|
||||
@ -1841,6 +1947,52 @@ static const struct pios_ppm_cfg pios_ppm_cfg = {
|
||||
#include "pios_rcvr_priv.h"
|
||||
#endif /* PIOS_INCLUDE_RCVR */
|
||||
|
||||
/*
|
||||
* SONAR Inputs
|
||||
*/
|
||||
#if defined(PIOS_INCLUDE_HCSR04)
|
||||
#include <pios_hcsr04_priv.h>
|
||||
|
||||
static const struct pios_tim_channel pios_tim_hcsr04_port_all_channels[] = {
|
||||
{
|
||||
.timer = TIM8,
|
||||
.timer_chan = TIM_Channel_3,
|
||||
.pin = {
|
||||
.gpio = GPIOC,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_8,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_PuPd = GPIO_PuPd_DOWN
|
||||
},
|
||||
.pin_source = GPIO_PinSource8,
|
||||
},
|
||||
.remap = GPIO_AF_TIM8,
|
||||
},
|
||||
};
|
||||
|
||||
const struct pios_hcsr04_cfg pios_hcsr04_cfg = {
|
||||
.tim_ic_init = {
|
||||
.TIM_ICPolarity = TIM_ICPolarity_Rising,
|
||||
.TIM_ICSelection = TIM_ICSelection_DirectTI,
|
||||
.TIM_ICPrescaler = TIM_ICPSC_DIV1,
|
||||
.TIM_ICFilter = 0x0,
|
||||
},
|
||||
.channels = pios_tim_hcsr04_port_all_channels,
|
||||
.num_channels = NELEMENTS(pios_tim_hcsr04_port_all_channels),
|
||||
.trigger = {
|
||||
.gpio = GPIOD,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_10,
|
||||
.GPIO_Mode = GPIO_Mode_OUT,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(PIOS_INCLUDE_USB)
|
||||
#include "pios_usb_priv.h"
|
||||
|
||||
|
@ -865,6 +865,91 @@ static const struct pios_dsm_cfg pios_dsm_flexi_cfg = {
|
||||
|
||||
#endif /* PIOS_INCLUDE_DSM */
|
||||
|
||||
/*
|
||||
* HK OSD
|
||||
*/
|
||||
static const struct pios_usart_cfg pios_usart_hkosd_main_cfg = {
|
||||
.regs = USART1,
|
||||
.remap = GPIO_AF_USART1,
|
||||
.init = {
|
||||
.USART_BaudRate = 57600,
|
||||
.USART_WordLength = USART_WordLength_8b,
|
||||
.USART_Parity = USART_Parity_No,
|
||||
.USART_StopBits = USART_StopBits_1,
|
||||
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
|
||||
.USART_Mode = USART_Mode_Rx | USART_Mode_Tx,
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = USART1_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
.rx = {
|
||||
.gpio = GPIOA,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_10,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
.tx = {
|
||||
.gpio = GPIOA,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_9,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pios_usart_cfg pios_usart_hkosd_flexi_cfg = {
|
||||
.regs = USART3,
|
||||
.remap = GPIO_AF_USART3,
|
||||
.init = {
|
||||
.USART_BaudRate = 57600,
|
||||
.USART_WordLength = USART_WordLength_8b,
|
||||
.USART_Parity = USART_Parity_No,
|
||||
.USART_StopBits = USART_StopBits_1,
|
||||
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
|
||||
.USART_Mode = USART_Mode_Rx | USART_Mode_Tx,
|
||||
},
|
||||
.irq = {
|
||||
.init = {
|
||||
.NVIC_IRQChannel = USART3_IRQn,
|
||||
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
|
||||
.NVIC_IRQChannelSubPriority = 0,
|
||||
.NVIC_IRQChannelCmd = ENABLE,
|
||||
},
|
||||
},
|
||||
.rx = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_11,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
.tx = {
|
||||
.gpio = GPIOB,
|
||||
.init = {
|
||||
.GPIO_Pin = GPIO_Pin_10,
|
||||
.GPIO_Speed = GPIO_Speed_2MHz,
|
||||
.GPIO_Mode = GPIO_Mode_AF,
|
||||
.GPIO_OType = GPIO_OType_PP,
|
||||
.GPIO_PuPd = GPIO_PuPd_UP
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#if defined(PIOS_INCLUDE_COM)
|
||||
|
||||
#include <pios_com_priv.h>
|
||||
|
@ -20,9 +20,9 @@ BL_BANK_SIZE := 0x00008000 # Should include BD_INFO region
|
||||
# Leave the remaining 16KB and 64KB sectors for other uses
|
||||
|
||||
FW_BANK_BASE := 0x08020000 # Start of firmware flash
|
||||
FW_BANK_SIZE := 0x00040000 # Should include FW_DESC_SIZE
|
||||
FW_BANK_SIZE := 0x00060000 # Should include FW_DESC_SIZE
|
||||
|
||||
FW_DESC_SIZE := 0x00000064
|
||||
|
||||
OSCILLATOR_FREQ := 8000000
|
||||
SYSCLK_FREQ := 108000000
|
||||
SYSCLK_FREQ := 168000000
|
||||
|
@ -4,7 +4,7 @@
|
||||
<field name="Armed" units="" type="enum" elements="1" options="Disarmed,Arming,Armed" defaultvalue="Disarmed"/>
|
||||
|
||||
<!-- Note these enumerated values should be the same as ManualControlSettings -->
|
||||
<field name="FlightMode" units="" type="enum" elements="1" options="Manual,Stabilized1,Stabilized2,Stabilized3,Autotune,AltitudeHold,VelocityControl,PositionHold,ReturnToBase,PathPlanner"/>
|
||||
<field name="FlightMode" units="" type="enum" elements="1" options="Manual,Stabilized1,Stabilized2,Stabilized3,Autotune,AltitudeHold,VelocityControl,PositionHold,ReturnToBase,Land,PathPlanner,POI"/>
|
||||
|
||||
<access gcs="readwrite" flight="readwrite"/>
|
||||
<telemetrygcs acked="false" updatemode="manual" period="0"/>
|
||||
|
@ -2,19 +2,19 @@
|
||||
<object name="HwSettings" singleinstance="true" settings="true">
|
||||
<description>Selection of optional hardware configurations.</description>
|
||||
<field name="CC_RcvrPort" units="function" type="enum" elements="1" options="Disabled,PWM,PPM,PPM+PWM,PPM+Outputs,Outputs" defaultvalue="PWM"/>
|
||||
<field name="CC_MainPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,S.Bus,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge" defaultvalue="Telemetry"/>
|
||||
<field name="CC_FlexiPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,I2C,PPM,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge" defaultvalue="Disabled"/>
|
||||
<field name="CC_MainPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,S.Bus,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge,OsdHk" defaultvalue="Telemetry"/>
|
||||
<field name="CC_FlexiPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,I2C,PPM,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge,OsdHk" defaultvalue="Disabled"/>
|
||||
|
||||
<field name="RV_RcvrPort" units="function" type="enum" elements="1" options="Disabled,PWM,PPM,PPM+Outputs,Outputs" defaultvalue="PWM"/>
|
||||
<field name="RV_AuxPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,DSM2,DSMX (10bit),DSMX (11bit),ComAux,ComBridge" defaultvalue="Disabled"/>
|
||||
<field name="RV_AuxSBusPort" units="function" type="enum" elements="1" options="Disabled,S.Bus,DSM2,DSMX (10bit),DSMX (11bit),ComAux,ComBridge" defaultvalue="Disabled"/>
|
||||
<field name="RV_AuxPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,DSM2,DSMX (10bit),DSMX (11bit),ComAux,ComBridge,OsdHk" defaultvalue="Disabled"/>
|
||||
<field name="RV_AuxSBusPort" units="function" type="enum" elements="1" options="Disabled,S.Bus,DSM2,DSMX (10bit),DSMX (11bit),ComAux,ComBridge,OsdHk" defaultvalue="Disabled"/>
|
||||
<field name="RV_FlexiPort" units="function" type="enum" elements="1" options="Disabled,I2C,DSM2,DSMX (10bit),DSMX (11bit),ComAux,ComBridge" defaultvalue="Disabled"/>
|
||||
<field name="RV_TelemetryPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,ComAux,ComBridge" defaultvalue="Telemetry"/>
|
||||
<field name="RV_GPSPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,ComAux,ComBridge" defaultvalue="GPS"/>
|
||||
|
||||
<field name="RM_RcvrPort" units="function" type="enum" elements="1" options="Disabled,PWM,PPM,PPM+PWM,PPM+Outputs,Outputs" defaultvalue="PWM"/>
|
||||
<field name="RM_MainPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,S.Bus,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge" defaultvalue="Telemetry"/>
|
||||
<field name="RM_FlexiPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,I2C,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge" defaultvalue="Disabled"/>
|
||||
<field name="RM_MainPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,S.Bus,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge,OsdHk" defaultvalue="Telemetry"/>
|
||||
<field name="RM_FlexiPort" units="function" type="enum" elements="1" options="Disabled,Telemetry,GPS,I2C,DSM2,DSMX (10bit),DSMX (11bit),DebugConsole,ComBridge,OsdHk" defaultvalue="Disabled"/>
|
||||
|
||||
<field name="RadioPort" units="function" type="enum" elements="1" options="Disabled,Telemetry" defaultvalue="Disabled"/>
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
<field name="USB_HIDPort" units="function" type="enum" elements="1" options="USBTelemetry,RCTransmitter,Disabled" defaultvalue="USBTelemetry"/>
|
||||
<field name="USB_VCPPort" units="function" type="enum" elements="1" options="USBTelemetry,ComBridge,DebugConsole,Disabled" defaultvalue="Disabled"/>
|
||||
|
||||
<field name="OptionalModules" units="" type="enum" elementnames="CameraStab,GPS,ComUsbBridge,Fault,Altitude,Airspeed,TxPID,Autotune,VtolPathFollower,FixedWingPathFollower,Battery,Overo" options="Disabled,Enabled" defaultvalue="Disabled"/>
|
||||
<field name="OptionalModules" units="" type="enum" elementnames="CameraStab,GPS,ComUsbBridge,Fault,Altitude,Airspeed,TxPID,Autotune,VtolPathFollower,FixedWingPathFollower,Battery,Overo,MagBaro,OsdHk" options="Disabled,Enabled" defaultvalue="Disabled"/>
|
||||
<field name="ADCRouting" units="" type="enum" elementnames="ADC0,ADC1,ADC2,ADC3" options="Disabled,BatteryVoltage,BatteryCurrent,AnalogAirspeed,Generic" defaultvalue="Disabled"/>
|
||||
<field name="DSMxBind" units="" type="uint8" elements="1" defaultvalue="0"/>
|
||||
|
||||
|
@ -26,7 +26,7 @@
|
||||
|
||||
<!-- Note these options values should be identical to those defined in FlightMode -->
|
||||
<field name="FlightModeNumber" units="" type="uint8" elements="1" defaultvalue="3"/>
|
||||
<field name="FlightModePosition" units="" type="enum" elements="6" options="Manual,Stabilized1,Stabilized2,Stabilized3,Autotune,AltitudeHold,VelocityControl,PositionHold,ReturnToBase,Land,PathPlanner" defaultvalue="Manual,Stabilized1,Stabilized2,Stabilized3,AltitudeHold,PositionHold" limits="%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune"/>
|
||||
<field name="FlightModePosition" units="" type="enum" elements="6" options="Manual,Stabilized1,Stabilized2,Stabilized3,Autotune,AltitudeHold,VelocityControl,PositionHold,ReturnToBase,Land,PathPlanner,POI" defaultvalue="Manual,Stabilized1,Stabilized2,Stabilized3,AltitudeHold,PositionHold" limits="%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI,%0401NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI;%0402NE:AltitudeHold:VelocityControl:PositionHold:Autotune:POI"/>
|
||||
|
||||
<field name="ArmedTimeout" units="ms" type="uint16" elements="1" defaultvalue="30000"/>
|
||||
<field name="FailsafeBehavior" units="" type="enum" elements="1" options="None" defaultvalue="None"/>
|
||||
|
@ -14,6 +14,9 @@
|
||||
<field name="Heading" units="" type="enum" elements="1" options="Disabled,Enabled" defaultvalue="Enabled"/>
|
||||
<field name="HeadingSetup" units="" type="int16" elements="2" elementnames="X,Y" defaultvalue="168,240"/>
|
||||
<field name="Screen" units="" type="uint8" elements="1" defaultvalue="0"/>
|
||||
<field name="White" units="" type="uint8" elements="1" defaultvalue="4"/>
|
||||
<field name="Black" units="" type="uint8" elements="1" defaultvalue="1"/>
|
||||
<field name="AltitudeSource" units="" type="enum" elements="1" options="GPS,Baro" defaultvalue="GPS"/>
|
||||
<access gcs="readwrite" flight="readwrite"/>
|
||||
<telemetrygcs acked="true" updatemode="onchange" period="0"/>
|
||||
<telemetryflight acked="true" updatemode="onchange" period="0"/>
|
||||
|
@ -27,6 +27,8 @@
|
||||
<elementname>ModemStat</elementname>
|
||||
<elementname>Autotune</elementname>
|
||||
<elementname>EventDispatcher</elementname>
|
||||
<elementname>MagBaro</elementname>
|
||||
<elementname>OSDGen</elementname>
|
||||
</elementnames>
|
||||
</field>
|
||||
<field name="Running" units="bool" type="enum">
|
||||
@ -55,6 +57,8 @@
|
||||
<elementname>ModemStat</elementname>
|
||||
<elementname>Autotune</elementname>
|
||||
<elementname>EventDispatcher</elementname>
|
||||
<elementname>MagBaro</elementname>
|
||||
<elementname>OSDGen</elementname>
|
||||
</elementnames>
|
||||
<options>
|
||||
<option>False</option>
|
||||
@ -87,6 +91,8 @@
|
||||
<elementname>ModemStat</elementname>
|
||||
<elementname>Autotune</elementname>
|
||||
<elementname>EventDispatcher</elementname>
|
||||
<elementname>MagBaro</elementname>
|
||||
<elementname>OSDGen</elementname>
|
||||
</elementnames>
|
||||
</field>
|
||||
<access gcs="readwrite" flight="readwrite"/>
|
||||
|
Loading…
x
Reference in New Issue
Block a user