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Code Issues Releases Activity

Changed to older (but working) ST USB drivers.

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git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@145 ebee16cc-31ac-478f-84a7-5cbb03baadba
This commit is contained in:
gussy 2010-01-31 17:10:12 +00:00 committed by gussy
parent efdb5c5f2b
commit 888d0a62ab
24 changed files with 112 additions and 5484 deletions
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259
flight/Libraries/STM32_USB-FS-Device_Driver/inc/otgd_fs_cal.h
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/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_cal.h
* Author : STMicroelectronics
* Version : V3.1.0
* Date : 10/30/2009
* Description : Header of OTG FS Device Core Access Layer interface.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __OTG_CORE_H__
#define __OTG_CORE_H__
#ifdef STM32F10X_CL
#include "stm32f10x.h"
#include "usb_type.h"
#if defined ( __CC_ARM )
#define __packed __packed /*!< packing keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __packed __packed /*!< packing keyword for IAR Compiler */
#elif defined ( __GNUC__ )
#define __packed __attribute__ ((__packed__)) /*!< packing keyword for GNU Compiler */
#endif /* __CC_ARM */
/*******************************************************************************
define and types
*******************************************************************************/
#define DEVICE_MODE_ENABLED
#ifndef NULL
#define NULL ((void *)0)
#endif
#define DEV_EP_TX_DIS 0x0000
#define DEV_EP_TX_STALL 0x0010
#define DEV_EP_TX_NAK 0x0020
#define DEV_EP_TX_VALID 0x0030
#define DEV_EP_RX_DIS 0x0000
#define DEV_EP_RX_STALL 0x1000
#define DEV_EP_RX_NAK 0x2000
#define DEV_EP_RX_VALID 0x3000
/***************** GLOBAL DEFINES ***************************/
#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
#define GAHBCFG_GLBINT_ENABLE 1
#define GAHBCFG_INT_DMA_BURST_SINGLE 0
#define GAHBCFG_INT_DMA_BURST_INCR 1
#define GAHBCFG_INT_DMA_BURST_INCR4 3
#define GAHBCFG_INT_DMA_BURST_INCR8 5
#define GAHBCFG_INT_DMA_BURST_INCR16 7
#define GAHBCFG_DMAENABLE 1
#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
#define GRXSTS_PKTSTS_IN 2
#define GRXSTS_PKTSTS_IN_XFER_COMP 3
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
#define GRXSTS_PKTSTS_CH_HALTED 7
#define DEVICE_MODE 0
#define HOST_MODE 1
/***************** DEVICE DEFINES ***************************/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
#define DCFG_FRAME_INTERVAL_80 0
#define DCFG_FRAME_INTERVAL_85 1
#define DCFG_FRAME_INTERVAL_90 2
#define DCFG_FRAME_INTERVAL_95 3
#define DEP0CTL_MPS_64 0
#define DEP0CTL_MPS_32 1
#define DEP0CTL_MPS_16 2
#define DEP0CTL_MPS_8 3
#define EP_SPEED_LOW 0
#define EP_SPEED_FULL 1
#define EP_SPEED_HIGH 2
#define EP_TYPE_CTRL 0
#define EP_TYPE_ISOC 1
#define EP_TYPE_BULK 2
#define EP_TYPE_INTR 3
#define STS_GOUT_NAK 1
#define STS_DATA_UPDT 2
#define STS_XFER_COMP 3
#define STS_SETUP_COMP 4
#define STS_SETUP_UPDT 6
typedef enum {
USB_OTG_OK,
USB_OTG_FAIL
}USB_OTG_Status;
typedef struct USB_OTG_hc
{
uint8_t hc_num;
uint8_t dev_addr ;
uint8_t ep_num;
uint8_t ep_is_in;
uint8_t speed;
uint8_t ep_type;
uint16_t max_packet;
uint8_t data_pid;
uint16_t multi_count;
uint8_t *xfer_buff;
uint32_t xfer_len;
}
USB_OTG_HC , *PUSB_OTG_HC;
typedef struct USB_OTG_ep
{
uint8_t num;
uint8_t is_in;
uint32_t tx_fifo_num;
uint32_t type;
uint8_t data_pid_start;
uint8_t even_odd_frame;
uint32_t maxpacket;
uint8_t *xfer_buff;
uint32_t xfer_len;
uint32_t xfer_count;
}
USB_OTG_EP , *PUSB_OTG_EP;
/********************************************************************************
MACRO'S
********************************************************************************/
#define CLEAR_IN_EP_INTR(epnum,intr) \
diepint.d32=0; \
diepint.b.intr = 1; \
WRITE_REG32(&core_regs.inep_regs[epnum]->dev_in_ep_int,diepint.d32);
#define CLEAR_OUT_EP_INTR(epnum,intr) \
doepint.d32=0; \
doepint.b.intr = 1; \
WRITE_REG32(&core_regs.outep_regs[epnum]->dev_out_ep_int,doepint.d32);
#define READ_REG32(reg) (*(__IO uint32_t *)reg)
#define WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value)
#define MODIFY_REG32(reg,clear_mask,set_mask) \
WRITE_REG32(reg, (((READ_REG32(reg)) & ~clear_mask) | set_mask ) )
#define uDELAY(usec) udelay(usec)
#define mDELAY(msec) uDELAY(msec * 1000)
#define _OTGD_FS_GATE_PHYCLK *(__IO uint32_t*)(0x50000E00) = 0x03
#define _OTGD_FS_UNGATE_PHYCLK *(__IO uint32_t*)(0x50000E00) = 0x00
/*******************************************************************************
this can be changed for real time base
*******************************************************************************/
static void udelay (const uint32_t usec)
{
uint32_t count = 0;
const uint32_t utime = usec * 10;
do
{
if ( ++count > utime )
{
return ;
}
}
while (1);
}
/********************************************************************************
EXPORTED FUNCTIONS FROM THE OTGD_FS_CAL LAYER
********************************************************************************/
USB_OTG_Status OTGD_FS_CoreInit(void);
USB_OTG_Status OTGD_FS_SetAddress(uint32_t BaseAddress);
USB_OTG_Status OTGD_FS_EnableGlobalInt(void);
USB_OTG_Status OTGD_FS_DisableGlobalInt(void);
USB_OTG_Status USB_OTG_CoreInitHost(void);
USB_OTG_Status USB_OTG_EnableHostInt(void);
USB_OTG_Status USB_OTG_DisableHostInt(void);
void* OTGD_FS_ReadPacket(uint8_t *dest, uint16_t bytes);
USB_OTG_Status OTGD_FS_WritePacket(uint8_t *src, uint8_t ch_ep_num, uint16_t bytes);
USB_OTG_Status USB_OTG_HcInit(USB_OTG_HC *hc);
USB_OTG_Status USB_OTG_StartXfer(USB_OTG_HC *hc);
uint32_t USB_OTG_ResetPort( void);
uint32_t USB_OTG_ReadHPRT0(void);
uint32_t OTGD_FS_ReadDevAllInEPItr(void);
uint32_t OTGD_FS_ReadCoreItr(void);
uint32_t OTGD_FS_ReadOtgItr (void);
uint32_t USB_OTG_ReadHostAllChannels_intr (void);
uint8_t IsHostMode(void);
uint8_t IsDeviceMode(void);
USB_OTG_Status USB_OTG_HcInit(USB_OTG_HC *hc);
USB_OTG_Status USB_OTG_HcHalt(uint8_t hc_num);
USB_OTG_Status OTGD_FS_FlushTxFifo (uint32_t num);
USB_OTG_Status OTGD_FS_FlushRxFifo (void);
USB_OTG_Status OTGD_FS_SetHostMode (void);
USB_OTG_Status OTGD_FS_PhyInit(void);
USB_OTG_Status USB_OTG_HcStartXfer(USB_OTG_HC *hc);
USB_OTG_Status OTGD_FS_CoreInitDev (void);
USB_OTG_Status OTGD_FS_EnableDevInt(void);
USB_OTG_Status OTGD_FS_EP0Activate(void);
USB_OTG_Status OTGD_FS_EPActivate(USB_OTG_EP *ep);
USB_OTG_Status OTGD_FS_EPDeactivate(USB_OTG_EP *ep);
USB_OTG_Status OTGD_FS_EPStartXfer(USB_OTG_EP *ep);
USB_OTG_Status OTGD_FS_EP0StartXfer(USB_OTG_EP *ep);
USB_OTG_Status OTGD_FS_EPSetStall(USB_OTG_EP *ep);
USB_OTG_Status OTGD_FS_EPClearStall(USB_OTG_EP *ep);
uint32_t OTGD_FS_ReadDevAllOutEp_itr(void);
uint32_t OTGD_FS_ReadDevOutEP_itr(USB_OTG_EP *ep);
uint32_t OTGD_FS_ReadDevAllInEPItr(void);
uint32_t OTGD_FS_Dev_GetEPStatus(USB_OTG_EP *ep);
void OTGD_FS_Dev_SetEPStatus(USB_OTG_EP *ep, uint32_t Status);
void OTGD_FS_Dev_SetRemoteWakeup(void);
void OTGD_FS_Dev_ResetRemoteWakeup(void);
#endif /* STM32F10X_CL */
#endif
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

121
flight/Libraries/STM32_USB-FS-Device_Driver/inc/otgd_fs_dev.h
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/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otg_dev.h
* Author : STMicroelectronics
* Version : V3.1.0
* Date : 10/30/2009
* Description : linking defines
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __OTG_DEV_H__
#define __OTG_DEV_H__
#ifdef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
#include "usb_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Endpoint types */
#define OTG_DEV_EP_TYPE_CONTROL 0
#define OTG_DEV_EP_TYPE_ISOC 1
#define OTG_DEV_EP_TYPE_BULK 2
#define OTG_DEV_EP_TYPE_INT 3
/* Endpoint Addresses (w/direction) */
#define EP0_OUT 0x00
#define EP0_IN 0x80
#define EP1_OUT 0x01
#define EP1_IN 0x81
#define EP2_OUT 0x02
#define EP2_IN 0x82
#define EP3_OUT 0x03
#define EP3_IN 0x83
/*-*-*-*-*-*-*-*-*-* Replace the usb_regs.h defines -*-*-*-*-*-*-*-*-*-*-*-*-*/
/* endpoints enumeration */
#define ENDP0 ((uint8_t)0)
#define ENDP1 ((uint8_t)1)
#define ENDP2 ((uint8_t)2)
#define ENDP3 ((uint8_t)3)
#define ENDP4 ((uint8_t)4)
#define ENDP5 ((uint8_t)5)
#define ENDP6 ((uint8_t)6)
#define ENDP7 ((uint8_t)7)
/* EP Transmit status defines */
#define EP_TX_DIS DEV_EP_TX_DIS) /* EndPoint TX DISabled */
#define EP_TX_STALL DEV_EP_TX_STALL /* EndPoint TX STALLed */
#define EP_TX_NAK DEV_EP_TX_NAK /* EndPoint TX NAKed */
#define EP_TX_VALID DEV_EP_TX_VALID /* EndPoint TX VALID */
/* EP Transmit status defines */
#define EP_RX_DIS DEV_EP_RX_DIS /* EndPoint RX DISabled */
#define EP_RX_STALL DEV_EP_RX_STALL /* EndPoint RX STALLed */
#define EP_RX_NAK DEV_EP_RX_NAK /* EndPoint RX NAKed */
#define EP_RX_VALID DEV_EP_RX_VALID /* EndPoint RX VALID */
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
/* Exported macro ------------------------------------------------------------*/
#define _GetEPTxStatus(bEpNum) ((uint16_t)OTG_DEV_GetEPTxStatus(bEpNum))
#define _GetEPRxStatus(bEpNum) ((uint16_t)OTG_DEV_GetEPRxStatus(bEpNum))
#define _SetEPTxStatus(bEpNum,wState) (OTG_DEV_SetEPTxStatus(bEpNum, wState))
#define _SetEPRxStatus(bEpNum,wState) (OTG_DEV_SetEPRxStatus(bEpNum, wState))
#define _SetEPTxValid(bEpNum) (OTG_DEV_SetEPTxStatus(bEpNum, EP_TX_VALID))
#define _SetEPRxValid(bEpNum) (OTG_DEV_SetEPRxStatus(bEpNum, EP_RX_VALID))
#define _GetTxStallStatus(bEpNum) (OTG_DEV_GetEPTxStatus(bEpNum) == EP_TX_STALL)
#define _GetRxStallStatus(bEpNum) (OTG_DEV_GetEPRxStatus(bEpNum) == EP_RX_STALL)
/* Define the callbacks for updating the USB state machine */
#define OTGD_FS_DEVICE_RESET Device_Property.Reset()
/* Exported define -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void OTG_DEV_Init(void);
void OTG_DEV_EP_Init(uint8_t bEpAdd, uint8_t bEpType, uint16_t wEpMaxPackSize);
void OTG_DEV_SetEPRxStatus(uint8_t bEpnum, uint32_t status);
void OTG_DEV_SetEPTxStatus(uint8_t bEpnum, uint32_t status);
uint32_t OTG_DEV_GetEPRxStatus(uint8_t bEpnum);
uint32_t OTG_DEV_GetEPTxStatus(uint8_t bEpnum);
void USB_DevDisconnect(void);
void USB_DevConnect(void);
/*-*-*-*-*-*-*-*-*-* Replace the usb_regs.h prototypes *-*-*-*-*-*-*-*-*-*-*-*/
void SetEPTxStatus(uint8_t bEpNum, uint16_t wState);
void SetEPRxStatus(uint8_t bEpNum, uint16_t wState);
uint16_t GetEPTxStatus(uint8_t bEpNum);
uint16_t GetEPRxStatus(uint8_t bEpNum);
void SetEPTxValid(uint8_t bEpNum);
void SetEPRxValid(uint8_t bEpNum);
uint16_t GetTxStallStatus(uint8_t bEpNum);
uint16_t GetRxStallStatus(uint8_t bEpNum);
void SetEPTxCount(uint8_t bEpNum, uint16_t wCount);
void SetEPRxCount(uint8_t bEpNum, uint16_t wCount);
uint16_t ToWord(uint8_t, uint8_t);
uint16_t ByteSwap(uint16_t);
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
#endif /* STM32F10X_CL */
#endif /* __OTG_DEV_H__ */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

54
flight/Libraries/STM32_USB-FS-Device_Driver/inc/otgd_fs_int.h
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/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_int.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Description : Endpoint interrupt's service routines prototypes.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_INT_H
#define __USB_INT_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#ifdef STM32F10X_CL
/* Interrupt Handlers functions */
uint32_t OTGD_FS_Handle_ModeMismatch_ISR(void);
uint32_t OTGD_FS_Handle_Sof_ISR(void);
uint32_t OTGD_FS_Handle_RxStatusQueueLevel_ISR(void);
uint32_t OTGD_FS_Handle_NPTxFE_ISR(void);
uint32_t OTGD_FS_Handle_GInNakEff_ISR(void);
uint32_t OTGD_FS_Handle_GOutNakEff_ISR(void);
uint32_t OTGD_FS_Handle_EarlySuspend_ISR(void);
uint32_t OTGD_FS_Handle_USBSuspend_ISR(void);
uint32_t OTGD_FS_Handle_UsbReset_ISR(void);
uint32_t OTGD_FS_Handle_EnumDone_ISR(void);
uint32_t OTGD_FS_Handle_IsoOutDrop_ISR(void);
uint32_t OTGD_FS_Handle_EOPF_ISR(void);
uint32_t OTGD_FS_Handle_EPMismatch_ISR(void);
uint32_t OTGD_FS_Handle_InEP_ISR(void);
uint32_t OTGD_FS_Handle_OutEP_ISR(void);
uint32_t OTGD_FS_Handle_IncomplIsoIn_ISR(void);
uint32_t OTGD_FS_Handle_IncomplIsoOut_ISR(void);
uint32_t OTGD_FS_Handle_Wakeup_ISR(void);
#endif /* STM32F10X_CL */
/* External variables --------------------------------------------------------*/
#endif /* __USB_INT_H */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

87
flight/Libraries/STM32_USB-FS-Device_Driver/inc/otgd_fs_pcd.h
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/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_pcd.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Description : Header file of the High Layer device mode interface and
* wrapping layer
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __USB_OTG_PCD_H__
#define __USB_OTG_PCD_H__
#include "otgd_fs_regs.h"
#define MAX_EP0_SIZE 0x40
#define MAX_PACKET_SIZE 0x400
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_XFERTYPE_MASK 3
/********************************************************************************
ENUMERATION TYPE
********************************************************************************/
enum usb_device_speed {
USB_SPEED_UNKNOWN = 0,
USB_SPEED_LOW, USB_SPEED_FULL,
USB_SPEED_HIGH
};
/********************************************************************************
Data structure type
********************************************************************************/
typedef struct usb_ep_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
}
EP_DESCRIPTOR , *PEP_DESCRIPTOR;
/********************************************************************************
USBF LAYER UNION AND STRUCTURES
********************************************************************************/
typedef struct USB_OTG_USBF
{
USB_OTG_EP ep0;
uint8_t ep0state;
USB_OTG_EP in_ep[ MAX_TX_FIFOS - 1];
USB_OTG_EP out_ep[ MAX_TX_FIFOS - 1];
}
USB_OTG_PCD_DEV , *USB_OTG_PCD_PDEV;
/********************************************************************************
EXPORTED FUNCTION FROM THE USB_OTG LAYER
********************************************************************************/
void OTGD_FS_PCD_Init(void);
void OTGD_FS_PCD_DevConnect (void);
void OTGD_FS_PCD_DevDisconnect (void);
void OTGD_FS_PCD_EP_SetAddress (uint8_t address);
uint32_t OTGD_FS_PCD_EP_Open(EP_DESCRIPTOR *epdesc);
uint32_t OTGD_FS_PCD_EP_Close ( uint8_t ep_addr);
uint32_t OTGD_FS_PCD_EP_Read ( uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
uint32_t OTGD_FS_PCD_EP_Write ( uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
uint32_t OTGD_FS_PCD_EP_Stall (uint8_t epnum);
uint32_t OTGD_FS_PCD_EP_ClrStall (uint8_t epnum);
uint32_t OTGD_FS_PCD_EP_Flush (uint8_t epnum);
uint32_t OTGD_FS_PCD_Handle_ISR(void);
USB_OTG_EP* OTGD_FS_PCD_GetOutEP(uint32_t ep_num) ;
USB_OTG_EP* OTGD_FS_PCD_GetInEP(uint32_t ep_num);
void OTGD_FS_PCD_EP0_OutStart(void);
#endif
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

1597
flight/Libraries/STM32_USB-FS-Device_Driver/inc/otgd_fs_regs.h
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/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_regs.h
* Author : STMicroelectronics
* Version : V3.1.0
* Date : 10/30/2009
* Description : USB OTG IP hardware registers.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __USB_OTG_REGS_H__
#define __USB_OTG_REGS_H__
#ifdef STM32F10X_CL
#include "stm32f10x.h"
#include "usb_type.h"
#define USB_OTG_FS1_BASE_ADDR 0x50000000
#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000
#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800
#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900
#define USB_OTG_EP_REG_OFFSET 0x20
#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00
#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400
#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440
#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500
#define USB_OTG_CHAN_REGS_OFFSET 0x20
#define USB_OTG_PCGCCTL_OFFSET 0xE00
#define USB_OTG_DATA_FIFO_OFFSET 0x1000
#define USB_OTG_DATA_FIFO_SIZE 0x1000
#define MAX_PERIO_FIFOS 8
#define MAX_TX_FIFOS 4
#define MAX_EPS_CHANNELS 8
#define DEV_NP_TX_FIFO_SIZE 160
#define RX_FIFO_SIZE 160
#define TX_FIFO_SIZE 160
/*******************************************************************************
* USB_OTG Core registers .
* The USB_OTG_core_regs structure defines the size
* and relative field offsets for the Core Global registers.
******************************************************************************/
typedef struct _USB_OTG_common_regs //000h
{
__IO uint32_t otg_ctl; /* USB_OTG Control and Status Register 000h*/
__IO uint32_t otg_int; /* USB_OTG Interrupt Register 004h*/
__IO uint32_t ahb_cfg; /* Core AHB Configuration Register 008h*/
__IO uint32_t usb_cfg; /* Core USB Configuration Register 00Ch*/
__IO uint32_t rst_ctl; /* Core Reset Register 010h*/
__IO uint32_t int_sts; /* Core Interrupt Register 014h*/
__IO uint32_t int_msk; /* Core Interrupt Mask Register 018h*/
__IO uint32_t rx_stsr; /* Receive Sts Q Read Register 01Ch*/
__IO uint32_t rx_stsp; /* Receive Sts Q Read & POP Register 020h*/
__IO uint32_t rx_fifo_siz; /* Receive FIFO Size Register 024h*/
__IO uint32_t np_tx_fifo_siz; /* Non Periodic Tx FIFO Size Register 028h*/
__IO uint32_t np_tx_sts; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
__IO uint32_t i2c_ctl; /* I2C Access Register 030h*/
__IO uint32_t phy_vnd_ctl; /* PHY Vendor Control Register 034h*/
__IO uint32_t gpio; /* General Purpose IO Register 038h*/
__IO uint32_t usr_id; /* User ID Register 03Ch*/
__IO uint32_t snps_id; /* Synopsys ID Register 040h*/
__IO uint32_t hw_cfg1; /* User HW Config1 Register (RO) 044h*/
__IO uint32_t hw_cfg2; /* User HW Config2 Register (RO) 048h*/
__IO uint32_t hw_cfg3; /* User HW Config3 Register (RO) 04Ch*/
__IO uint32_t hw_cfg4; /* User HW Config4 Register (RO) 050h*/
uint32_t reserved[43]; /* Reserved 054h-0FFh*/
__IO uint32_t host_p_tx_fifo_siz; /* Host Periodic Tx FIFO Size Reg 100h*/
__IO uint32_t dev_p_tx_fsiz_dieptxf[15];/* dev Periodic Transmit FIFO */
}
USB_OTG_common_regs;
/*******************************************************************************
* dev Registers
* dev Global Registers : Offsets 800h-BFFh
* The following structures define the size and relative field offsets
* for the dev Mode Registers.
* These registers are visible only in dev mode and must not be
* accessed in Host mode, as the results are unknown
******************************************************************************/
typedef struct _USB_OTG_dev_regs // 800h
{
__IO uint32_t dev_cfg; /* dev Configuration Register 800h*/
__IO uint32_t dev_ctl; /* dev Control Register 804h*/
__IO uint32_t dev_sts; /* dev Status Register (RO) 808h*/
uint32_t reserved3; /* Reserved 80Ch*/
__IO uint32_t dev_in_ep_msk; /* dev IN Endpoint Mask 810h*/
__IO uint32_t dev_out_ep_msk; /* dev OUT Endpoint Mask 814h*/
__IO uint32_t dev_all_int; /* dev All Endpoints Itr Reg 818h*/
__IO uint32_t dev_all_int_msk; /* dev All Endpoints Itr Mask 81Ch*/
uint32_t Reserved8; /* Reserved 820h*/
__IO uint32_t Reserved9; /* Reserved 824h*/
__IO uint32_t dev_vbus_dis; /* dev VBUS discharge Register 828h*/
__IO uint32_t dev_vbus_pulse; /* dev VBUS Pulse Register 82Ch*/
__IO uint32_t dev_thr_ctl; /* dev thr 830h*/
__IO uint32_t dev_fifo_empty_msk; /* dev empty msk 834h*/
}
USB_OTG_dev_regs;
/*******************************************************************************
* dev Logical IN Endpoint-Specific Registers: Offsets 900h-AFCh
* There will be one set of endpoint registers per logical endpointimplemented.
* These registers are visible only in dev mode and must not be
* accessed in Host mode, as the results are unknown
*******************************************************************************/
typedef struct _USB_OTG_dev_in_ep_regs
{
__IO uint32_t dev_in_ep_ctl; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t dev_in_ep_int; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t dev_in_ep_txfer_siz; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
__IO uint32_t dev_in_ep_dma; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
__IO uint32_t dev_tx_fifo_sts;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
}
USB_OTG_dev_in_ep_regs;
/*******************************************************************************
* dev Logical OUT Endpoint-Specific Registers Offsets: B00h-CFCh
* There will be one set of endpoint registers per logical endpoint
* implemented.
* These registers are visible only in dev mode and must not be
* accessed in Host mode, as the results are unknown
******************************************************************************/
typedef struct _USB_OTG_dev_out_ep_regs
{
__IO uint32_t dev_out_ep_ctl; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
__IO uint32_t dev_out_ep_frm_nbr; /* dev OUT Endpoint Frame number B00h + (ep_num * 20h) + 04h*/
__IO uint32_t dev_out_ep_int; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t dev_out_ep_txfer_siz; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
__IO uint32_t dev_out_ep_dma; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
uint32_t reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
}
USB_OTG_dev_out_ep_regs;
/*******************************************************************************
* Host Mode Register Structures
* The Host Global Registers structure defines the size and relative
* field offsets for the Host Mode Global Registers.
* Host Global Registers offsets 400h-7FFh.
*******************************************************************************/
typedef struct _USB_OTG_host_regs
{
__IO uint32_t host_cfg; /* Host Configuration Register 400h*/
__IO uint32_t host_frm_intrvl; /* Host Frame Interval Register 404h*/
__IO uint32_t host_frm_nbr; /* Host Frame Nbr/Frame Remaining 408h*/
uint32_t reserved40C; /* Reserved 40Ch*/
__IO uint32_t host_p_tx_sts; /* Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t host_all_int; /* Host All Channels Interrupt Register 414h*/
__IO uint32_t host_all_int_msk; /* Host All Channels Interrupt Mask 418h*/
}
USB_OTG_host_regs;
/*******************************************************************************
* Host Channel Specific Registers 500h-5FCh
*******************************************************************************/
typedef struct _USB_OTG_hc_regs
{
__IO uint32_t hc_char;
__IO uint32_t hc_split;
__IO uint32_t hc_int;
__IO uint32_t hc_int_msk;
__IO uint32_t hc_txfer_siz;
__IO uint32_t hc_dma;
uint32_t reserved[2];
}
USB_OTG_hc_regs;
/*******************************************************************************
* otg Core registers .
* The USB_OTG_core_regs structure defines the size
* and relative field offsets for the Core Global registers.
******************************************************************************/
typedef struct USB_OTG_core_regs //000h
{
USB_OTG_common_regs *common_regs;
USB_OTG_dev_regs *dev_regs;
USB_OTG_host_regs *host_regs;
USB_OTG_dev_in_ep_regs *inep_regs[MAX_EPS_CHANNELS];
USB_OTG_dev_out_ep_regs *outep_regs[MAX_EPS_CHANNELS];
USB_OTG_hc_regs *hc_regs[MAX_EPS_CHANNELS];
__IO uint32_t *hprt0;
__IO uint32_t *data_fifo[MAX_EPS_CHANNELS];
__IO uint32_t *pcgcctl;
}
USB_OTG_CORE_REGS , *pUSB_OTG_CORE_REGS;
/******************************************************************************/
typedef union _USB_OTG_OTG_ctl_data
{
uint32_t d32;
struct
{
uint32_t sesreqscs :
1;
uint32_t sesreq :
1;
uint32_t reserved2_7 :
6;
uint32_t hstnegscs :
1;
uint32_t hnpreq :
1;
uint32_t hstsethnpen :
1;
uint32_t devhnpen :
1;
uint32_t reserved12_15 :
4;
uint32_t conidsts :
1;
uint32_t reserved17 :
1;
uint32_t asesvld :
1;
uint32_t bsesvld :
1;
uint32_t currmod :
1;
uint32_t reserved21_31 :
11;
}
b;
} USB_OTG_OTG_ctl_data;
/******************************************************************************/
typedef union _USB_OTG_OTG_int_data
{
uint32_t d32;
struct
{
uint32_t reserved0_1 :
2;
uint32_t sesenddet :
1;
uint32_t reserved3_7 :
5;
uint32_t sesreqsucstschng :
1;
uint32_t hstnegsucstschng :
1;
uint32_t reserver10_16 :
7;
uint32_t hstnegdet :
1;
uint32_t adevtoutchng :
1;
uint32_t debdone :
1;
uint32_t reserved31_20 :
12;
}
b;
} USB_OTG_OTG_int_data;
/******************************************************************************/
typedef union _USB_OTG_ahb_cfg_data
{
uint32_t d32;
struct
{
uint32_t glblintrmsk :
1;
uint32_t hburstlen :
4;
uint32_t dmaenable :
1;
uint32_t reserved :
1;
uint32_t nptxfemplvl_txfemplvl :
1;
uint32_t ptxfemplvl :
1;
uint32_t reserved9_31 :
23;
}
b;
} USB_OTG_ahb_cfg_data;
/******************************************************************************/
typedef union _USB_OTG_usb_cfg_data
{
uint32_t d32;
struct
{
uint32_t toutcal :
3;
uint32_t phyif :
1;
uint32_t ulpi_utmi_sel :
1;
uint32_t fsintf :
1;
uint32_t physel :
1;
uint32_t ddrsel :
1;
uint32_t srpcap :
1;
uint32_t hnpcap :
1;
uint32_t usbtrdtim :
4;
uint32_t nptxfrwnden :
1;
uint32_t phylpwrclksel :
1;
uint32_t otgutmifssel :
1;
uint32_t ulpi_fsls :
1;
uint32_t ulpi_auto_res :
1;
uint32_t ulpi_clk_sus_m :
1;
uint32_t ulpi_ext_vbus_drv :
1;
uint32_t ulpi_int_vbus_indicator :
1;
uint32_t term_sel_dl_pulse :
1;
uint32_t reserved :
6;
uint32_t force_host :
1;
uint32_t force_dev :
1;
uint32_t corrupt_tx :
1;
}
b;
} USB_OTG_usb_cfg_data;
/******************************************************************************/
typedef union _USB_OTG_rst_ctl_data
{
uint32_t d32;
struct
{
uint32_t csftrst :
1;
uint32_t hsftrst :
1;
uint32_t hstfrm :
1;
uint32_t intknqflsh :
1;
uint32_t rxfflsh :
1;
uint32_t txfflsh :
1;
uint32_t txfnum :
5;
uint32_t reserved11_29 :
19;
uint32_t dmareq :
1;
uint32_t ahbidle :
1;
}
b;
} USB_OTG_rst_ctl_data;
/******************************************************************************/
typedef union _USB_OTG_int_msk_data
{
uint32_t d32;
struct
{
uint32_t reserved0 :
1;
uint32_t modemismatch :
1;
uint32_t otgintr :
1;
uint32_t sofintr :
1;
uint32_t rxstsqlvl :
1;
uint32_t nptxfempty :
1;
uint32_t ginnakeff :
1;
uint32_t goutnakeff :
1;
uint32_t reserved8 :
1;
uint32_t i2cintr :
1;
uint32_t erlysuspend :
1;
uint32_t usbsuspend :
1;
uint32_t usbreset :
1;
uint32_t enumdone :
1;
uint32_t isooutdrop :
1;
uint32_t eopframe :
1;
uint32_t reserved16 :
1;
uint32_t epmismatch :
1;
uint32_t inepintr :
1;
uint32_t outepintr :
1;
uint32_t incomplisoin :
1;
uint32_t incomplisoout :
1;
uint32_t reserved22_23 :
2;
uint32_t portintr :
1;
uint32_t hcintr :
1;
uint32_t ptxfempty :
1;
uint32_t reserved27 :
1;
uint32_t conidstschng :
1;
uint32_t disconnect :
1;
uint32_t sessreqintr :
1;
uint32_t wkupintr :
1;
}
b;
} USB_OTG_int_msk_data;
/******************************************************************************/
typedef union _USB_OTG_int_sts_data
{
uint32_t d32;
struct
{
uint32_t curmode :
1;
uint32_t modemismatch :
1;
uint32_t otgintr :
1;
uint32_t sofintr :
1;
uint32_t rxstsqlvl :
1;
uint32_t nptxfempty :
1;
uint32_t ginnakeff :
1;
uint32_t goutnakeff :
1;
uint32_t reserved8 :
1;
uint32_t i2cintr :
1;
uint32_t erlysuspend :
1;
uint32_t usbsuspend :
1;
uint32_t usbreset :
1;
uint32_t enumdone :
1;
uint32_t isooutdrop :
1;
uint32_t eopframe :
1;
uint32_t intokenrx :
1;
uint32_t epmismatch :
1;
uint32_t inepint:
1;
uint32_t outepintr :
1;
uint32_t incomplisoin :
1;
uint32_t incomplisoout :
1;
uint32_t reserved22_23 :
2;
uint32_t portintr :
1;
uint32_t hcintr :
1;
uint32_t ptxfempty :
1;
uint32_t reserved27 :
1;
uint32_t conidstschng :
1;
uint32_t disconnect :
1;
uint32_t sessreqintr :
1;
uint32_t wkupintr :
1;
}
b;
} USB_OTG_int_sts_data;
/******************************************************************************/
typedef union _USB_OTG_dev_rx_sts_data
{
uint32_t d32;
struct
{
uint32_t epnum :
4;
uint32_t bcnt :
11;
uint32_t dpid :
2;
uint32_t pktsts :
4;
uint32_t fn :
4;
uint32_t reserved :
7;
}
b;
} USB_OTG_dev_rx_sts_data;
/******************************************************************************/
typedef union _USB_OTG_host_rx_sts_data
{
uint32_t d32;
struct
{
uint32_t chnum :
4;
uint32_t bcnt :
11;
uint32_t dpid :
2;
uint32_t pktsts :
4;
uint32_t reserved :
11;
}
b;
} USB_OTG_host_rx_sts_data;
/******************************************************************************/
typedef union _USB_OTG_fifo_size_data
{
uint32_t d32;
struct
{
uint32_t startaddr :
16;
uint32_t depth :
16;
}
b;
} USB_OTG_fifo_size_data;
/******************************************************************************/
typedef union _USB_OTG_np_tx_sts_data
{
uint32_t d32;
struct
{
uint32_t nptxfspcavail :
16;
uint32_t nptxqspcavail :
8;
uint32_t nptxqtop_terminate :
1;
uint32_t nptxqtop_token :
2;
uint32_t nptxqtop_chnep :
4;
uint32_t reserved :
1;
}
b;
} USB_OTG_np_tx_sts_data;
/******************************************************************************/
typedef union _USB_OTG_dev_tx_fifo_sts_data
{
uint32_t d32;
struct
{
uint32_t txfspcavail :
16;
uint32_t reserved :
16;
}
b;
} USB_OTG_dev_tx_fifo_sts_data;
/******************************************************************************/
typedef union _USB_OTG_i2c_ctl_data
{
uint32_t d32;
struct
{
uint32_t rwdata :
8;
uint32_t regaddr :
8;
uint32_t addr :
7;
uint32_t i2cen :
1;
uint32_t ack :
1;
uint32_t i2csuspctl :
1;
uint32_t i2cdevaddr :
2;
uint32_t dat_se0:
1;
uint32_t reserved :
1;
uint32_t rw :
1;
uint32_t bsydne :
1;
}
b;
} USB_OTG_i2c_ctl_data;
/******************************************************************************/
typedef union _USB_OTG_gpio_data
{
uint32_t d32;
struct
{
/* input */
uint32_t ovrcur :
1;
uint32_t otgid :
1;
uint32_t reserved_in :
14;
/* Output */
uint32_t pwdn :
1;
uint32_t i2cifen :
1;
uint32_t vbussensingA :
1;
uint32_t vbussensingB :
1;
uint32_t SOFouten :
1;
uint32_t reserved_out :
11;
}
b;
} USB_OTG_gpio_data;
/******************************************************************************/
typedef union _USB_OTG_hw_cfg1_data
{
uint32_t d32;
struct
{
uint32_t ep_dir0 :
2;
uint32_t ep_dir1 :
2;
uint32_t ep_dir2 :
2;
uint32_t ep_dir3 :
2;
uint32_t ep_dir4 :
2;
uint32_t ep_dir5 :
2;
uint32_t ep_dir6 :
2;
uint32_t ep_dir7 :
2;
uint32_t ep_dir8 :
2;
uint32_t ep_dir9 :
2;
uint32_t ep_dir10 :
2;
uint32_t ep_dir11 :
2;
uint32_t ep_dir12 :
2;
uint32_t ep_dir13 :
2;
uint32_t ep_dir14 :
2;
uint32_t ep_dir15 :
2;
}
b;
} USB_OTG_hw_cfg1_data;
/******************************************************************************/
typedef union _USB_OTG_hw_cfg2_data
{
uint32_t d32;
struct
{
uint32_t op_mode :
3;
uint32_t architecture :
2;
uint32_t point2point :
1;
uint32_t hs_phy_type :
2;
uint32_t fs_phy_type :
2;
uint32_t num_dev_ep :
4;
uint32_t num_host_chan :
4;
uint32_t perio_ep_supported :
1;
uint32_t dynamic_fifo :
1;
uint32_t rx_status_q_depth :
2;
uint32_t nonperio_tx_q_depth :
2;
uint32_t host_perio_tx_q_depth :
2;
uint32_t dev_token_q_depth :
5;
uint32_t reserved31 :
1;
}
b;
} USB_OTG_hw_cfg2_data;
/******************************************************************************/
typedef union _USB_OTG_hw_cfg3_data
{
uint32_t d32;
struct
{
uint32_t xfer_size_cntr_width :
4;
uint32_t packet_size_cntr_width :
3;
uint32_t otg_func :
1;
uint32_t i2c :
1;
uint32_t vendor_ctrl_if :
1;
uint32_t optional_features :
1;
uint32_t synch_reset_type :
1;
uint32_t ahb_phy_clock_synch :
1;
uint32_t reserved15_13 :
3;
uint32_t dfifo_depth :
16;
}
b;
} USB_OTG_hw_cfg3_data;
/******************************************************************************/
typedef union _USB_OTG_hw_cfg4_data
{
uint32_t d32;
struct
{
uint32_t num_dev_perio_in_ep :
4;
uint32_t power_optimiz :
1;
uint32_t min_ahb_freq :
9;
uint32_t utmi_phy_data_width :
2;
uint32_t num_dev_mode_ctrl_ep :
4;
uint32_t iddig_filt_en :
1;
uint32_t vbus_valid_filt_en :
1;
uint32_t a_valid_filt_en :
1;
uint32_t b_valid_filt_en :
1;
uint32_t session_end_filt_en :
1;
uint32_t ded_fifo_en :
1;
uint32_t num_in_eps :
4;
uint32_t reserved31_30 :
2;
}
b;
} USB_OTG_hw_cfg4_data;
/******************************************************************************/
typedef union _USB_OTG_dev_cfg_data
{
uint32_t d32;
struct
{
uint32_t devspd :
2;
uint32_t nzstsouthshk :
1;
uint32_t reserved3 :
1;
uint32_t devaddr :
7;
uint32_t perfrint :
2;
uint32_t reserved13_17 :
5;
uint32_t epmscnt :
4;
}
b;
} USB_OTG_dev_cfg_data;
/******************************************************************************/
typedef union _USB_OTG_dev_ctl_data
{
uint32_t d32;
struct
{
uint32_t rmtwkupsig :
1;
uint32_t sftdiscon :
1;
uint32_t gnpinnaksts :
1;
uint32_t goutnaksts :
1;
uint32_t tstctl :
3;
uint32_t sgnpinnak :
1;
uint32_t cgnpinnak :
1;
uint32_t sgoutnak :
1;
uint32_t cgoutnak :
1;
uint32_t reserved :
21;
}
b;
} USB_OTG_dev_ctl_data;
/******************************************************************************/
typedef union _USB_OTG_dev_sts_data
{
uint32_t d32;
struct
{
uint32_t suspsts :
1;
uint32_t enumspd :
2;
uint32_t errticerr :
1;
uint32_t reserved4_7:
4;
uint32_t soffn :
14;
uint32_t reserved22_31 :
10;
}
b;
} USB_OTG_dev_sts_data;
/******************************************************************************/
typedef union _USB_OTG_dev_in_ep_int_data
{
uint32_t d32;
struct
{
uint32_t xfercompl :
1;
uint32_t epdisabled :
1;
uint32_t ahberr :
1;
uint32_t timeout :
1;
uint32_t intktxfemp :
1;
uint32_t intknepmis :
1;
uint32_t inepnakeff :
1;
uint32_t emptyintr :
1;
uint32_t txfifoundrn :
1;
uint32_t reserved08_31 :
23;
}
b;
} USB_OTG_dev_in_ep_int_data;
/******************************************************************************/
typedef union _USB_OTG_dev_in_ep_int_data USB_OTG_dev_in_ep_msk_data;
/******************************************************************************/
typedef union _USB_OTG_dev_out_ep_int_data
{
uint32_t d32;
struct
{
uint32_t xfercompl :
1;
uint32_t epdisabled :
1;
uint32_t ahberr :
1;
uint32_t setup :
1;
uint32_t reserved04_31 :
28;
}
b;
} USB_OTG_dev_out_ep_int_data;
/******************************************************************************/
typedef union _USB_OTG_dev_out_ep_int_data USB_OTG_dev_out_ep_msk_data;
/******************************************************************************/
typedef union _USB_OTG_dev_all_int_data
{
uint32_t d32;
struct
{
uint32_t in :
16;
uint32_t out :
16;
}
ep;
struct
{
/** IN Endpoint bits */
uint32_t inep0 :
1;
uint32_t inep1 :
1;
uint32_t inep2 :
1;
uint32_t inep3 :
1;
uint32_t inep4 :
1;
uint32_t inep5 :
1;
uint32_t inep6 :
1;
uint32_t inep7 :
1;
uint32_t inep8 :
1;
uint32_t inep9 :
1;
uint32_t inep10 :
1;
uint32_t inep11 :
1;
uint32_t inep12 :
1;
uint32_t inep13 :
1;
uint32_t inep14 :
1;
uint32_t inep15 :
1;
/** OUT Endpoint bits */
uint32_t outep0 :
1;
uint32_t outep1 :
1;
uint32_t outep2 :
1;
uint32_t outep3 :
1;
uint32_t outep4 :
1;
uint32_t outep5 :
1;
uint32_t outep6 :
1;
uint32_t outep7 :
1;
uint32_t outep8 :
1;
uint32_t outep9 :
1;
uint32_t outep10 :
1;
uint32_t outep11 :
1;
uint32_t outep12 :
1;
uint32_t outep13 :
1;
uint32_t outep14 :
1;
uint32_t outep15 :
1;
}
b;
} USB_OTG_dev_all_int_data;
/******************************************************************************/
typedef union _USB_OTG_token_qr1_data
{
uint32_t d32;
struct
{
uint32_t intknwptr :
5;
uint32_t reserved05_06 :
2;
uint32_t wrap_bit :
1;
uint32_t epnums0_5 :
24;
}
b;
} USB_OTG_token_qr1_data;
/******************************************************************************/
typedef union _USB_OTG_dev_thr_ctl_data
{
uint32_t d32;
struct
{
uint32_t non_iso_thr_en :
1;
uint32_t iso_thr_en :
1;
uint32_t tx_thr_len :
9;
uint32_t reserved11_15 :
5;
uint32_t rx_thr_en :
1;
uint32_t rx_thr_len :
9;
uint32_t reserved26_31 :
6;
}
b;
} USB_OTG_dev_thr_ctl_data;
/******************************************************************************/
typedef union _USB_OTG_dev_ep_ctl_data
{
uint32_t d32;
struct
{
uint32_t mps :
11;
uint32_t nextep :
4;
uint32_t usbactep :
1;
uint32_t dpid :
1;
uint32_t naksts :
1;
uint32_t eptype :
2;
uint32_t snp :
1;
uint32_t stall :
1;
uint32_t txfnum :
4;
uint32_t cnak :
1;
uint32_t snak :
1;
uint32_t setd0pid :
1;
uint32_t setd1pid :
1;
uint32_t epdis :
1;
uint32_t epena :
1;
}
b;
} USB_OTG_dev_ep_ctl_data;
/******************************************************************************/
typedef union _USB_OTG_dev_ep_txfer_siz_data
{
uint32_t d32;
struct
{
uint32_t xfersize :
19;
uint32_t pktcnt :
10;
uint32_t mc :
2;
uint32_t reserved :
1;
}
b;
} USB_OTG_dev_ep_txfer_siz_data;
/******************************************************************************/
typedef union _USB_OTG_dev_ep_txfer_size0_data
{
uint32_t d32;
struct
{
uint32_t xfersize :
7;
uint32_t reserved7_18 :
12;
uint32_t pktcnt :
1;
uint32_t reserved20_28 :
9;
uint32_t supcnt :
2;
uint32_t reserved31;
}
b;
} USB_OTG_dev_ep_txfer_size0_data;
/******************************************************************************/
typedef union _USB_OTG_host_cfg_data
{
uint32_t d32;
struct
{
uint32_t fslspclksel :
2;
uint32_t fslssupp :
1;
}
b;
} USB_OTG_host_cfg_data;
/******************************************************************************/
typedef union _USB_OTG_Host_frm_intrvl_data
{
uint32_t d32;
struct
{
uint32_t frint :
16;
uint32_t reserved :
16;
}
b;
} USB_OTG_Host_frm_intrvl_data;
/******************************************************************************/
#define HFNUM_MAX_FRNUM 0x3FFF
typedef union _USB_OTG_host_frm_nbr_data
{
uint32_t d32;
struct
{
uint32_t frnum :
16;
uint32_t frrem :
16;
}
b;
} USB_OTG_host_frm_nbr_data;
/******************************************************************************/
typedef union _USB_OTG_host_perio_tx_sts_data
{
uint32_t d32;
struct
{
uint32_t ptxfspcavail :
16;
uint32_t ptxqspcavail :
8;
uint32_t ptxqtop_terminate :
1;
uint32_t ptxqtop_token :
2;
uint32_t ptxqtop_chnum :
4;
uint32_t ptxqtop_odd :
1;
}
b;
} USB_OTG_host_perio_tx_sts_data;
/******************************************************************************/
typedef union _USB_OTG_hprt0_data
{
uint32_t d32;
struct
{
uint32_t prtconnsts :
1;
uint32_t prtconndet :
1;
uint32_t prtena :
1;
uint32_t prtenchng :
1;
uint32_t prtovrcurract :
1;
uint32_t prtovrcurrchng :
1;
uint32_t prtres :
1;
uint32_t prtsusp :
1;
uint32_t prtrst :
1;
uint32_t reserved9 :
1;
uint32_t prtlnsts :
2;
uint32_t prtpwr :
1;
uint32_t prttstctl :
4;
uint32_t prtspd :
2;
uint32_t reserved19_31 :
13;
}
b;
} USB_OTG_hprt0_data;
/******************************************************************************/
typedef union _USB_OTG_host_all_int_data
{
uint32_t d32;
struct
{
uint32_t ch0 :
1;
uint32_t ch1 :
1;
uint32_t ch2 :
1;
uint32_t ch3 :
1;
uint32_t ch4 :
1;
uint32_t ch5 :
1;
uint32_t ch6 :
1;
uint32_t ch7 :
1;
uint32_t ch8 :
1;
uint32_t ch9 :
1;
uint32_t ch10 :
1;
uint32_t ch11 :
1;
uint32_t ch12 :
1;
uint32_t ch13 :
1;
uint32_t ch14 :
1;
uint32_t ch15 :
1;
uint32_t reserved :
16;
}
b;
struct
{
uint32_t chint :
16;
uint32_t reserved :
16;
}
b2;
} USB_OTG_host_all_int_data;
/******************************************************************************/
typedef union _USB_OTG_host_all_int_msk_data
{
uint32_t d32;
struct
{
uint32_t ch0 :
1;
uint32_t ch1 :
1;
uint32_t ch2 :
1;
uint32_t ch3 :
1;
uint32_t ch4 :
1;
uint32_t ch5 :
1;
uint32_t ch6 :
1;
uint32_t ch7 :
1;
uint32_t ch8 :
1;
uint32_t ch9 :
1;
uint32_t ch10 :
1;
uint32_t ch11 :
1;
uint32_t ch12 :
1;
uint32_t ch13 :
1;
uint32_t ch14 :
1;
uint32_t ch15 :
1;
uint32_t reserved :
16;
}
b;
struct
{
uint32_t chint :
16;
uint32_t reserved :
16;
}
b2;
} USB_OTG_host_all_int_msk_data;
/******************************************************************************/
typedef union _USB_OTG_hc_char_data
{
uint32_t d32;
struct
{
uint32_t mps :
11;
uint32_t epnum :
4;
uint32_t epdir :
1;
uint32_t reserved :
1;
uint32_t lspddev :
1;
uint32_t eptype :
2;
uint32_t multicnt :
2;
uint32_t devaddr :
7;
uint32_t oddfrm :
1;
uint32_t chdis :
1;
uint32_t chen :
1;
}
b;
} USB_OTG_hc_char_data;
/******************************************************************************/
typedef union _USB_OTG_hc_splt_data
{
uint32_t d32;
struct
{
uint32_t prtaddr :
7;
uint32_t hubaddr :
7;
uint32_t xactpos :
2;
uint32_t compsplt :
1;
uint32_t reserved :
14;
uint32_t spltena :
1;
}
b;
} USB_OTG_hc_splt_data;
/******************************************************************************/
typedef union _USB_OTG_hc_int_data
{
uint32_t d32;
struct
{
uint32_t xfercomp :
1;
uint32_t chhltd :
1;
uint32_t ahberr :
1;
uint32_t stall :
1;
uint32_t nak :
1;
uint32_t ack :
1;
uint32_t nyet :
1;
uint32_t xacterr :
1;
uint32_t bblerr :
1;
uint32_t frmovrun :
1;
uint32_t datatglerr :
1;
uint32_t reserved :
21;
}
b;
} USB_OTG_hc_int_data;
/******************************************************************************/
typedef union _USB_OTG_hc_txfer_siz_data
{
uint32_t d32;
struct
{
uint32_t xfersize :
19;
uint32_t pktcnt :
10;
uint32_t pid :
2;
uint32_t dopng :
1;
}
b;
} USB_OTG_hc_txfer_siz_data;
/******************************************************************************/
typedef union _USB_OTG_hc_int_msk_data
{
uint32_t d32;
struct
{
uint32_t xfercompl :
1;
uint32_t chhltd :
1;
uint32_t ahberr :
1;
uint32_t stall :
1;
uint32_t nak :
1;
uint32_t ack :
1;
uint32_t nyet :
1;
uint32_t xacterr :
1;
uint32_t bblerr :
1;
uint32_t frmovrun :
1;
uint32_t datatglerr :
1;
uint32_t reserved :
21;
}
b;
} USB_OTG_hc_int_msk_data;
/******************************************************************************/
typedef union _USB_OTG_host_pcgcctl_data
{
uint32_t d32;
struct
{
uint32_t stoppclk :
1;
uint32_t gatehclk :
1;
uint32_t pwrclmp :
1;
uint32_t rstpdwnmodule :
1;
uint32_t physuspended :
1;
uint32_t reserved :
27;
}
b;
} USB_OTG_host_pcgcctl_data;
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
#endif

8
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_core.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_core.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Standard protocol processing functions prototypes
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -235,8 +235,8 @@ extern DEVICE Device_Table;
extern DEVICE_INFO Device_Info;
/* cells saving status during interrupt servicing */
extern __IO uint16_t SaveRState;
extern __IO uint16_t SaveTState;
extern uint16_t SaveRState;
extern uint16_t SaveTState;
#endif /* __USB_CORE_H */

4
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_def.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_def.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Definitions related to USB Core
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

4
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_init.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_init.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Initialization routines & global variables
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

4
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_int.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_int.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Endpoint CTR (Low and High) interrupt's service routines
* prototypes
********************************************************************************

20
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_lib.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_lib.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : USB library include files
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -24,20 +24,8 @@
#include "usb_def.h"
#include "usb_core.h"
#include "usb_init.h"
#ifndef STM32F10X_CL
#include "usb_mem.h"
#include "usb_int.h"
#endif /* STM32F10X_CL */
#include "usb_sil.h"
#ifdef STM32F10X_CL
#include "otgd_fs_cal.h"
#include "otgd_fs_pcd.h"
#include "otgd_fs_dev.h"
#include "otgd_fs_int.h"
#endif /* STM32F10X_CL */
#include "usb_mem.h"
#include "usb_int.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

4
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_mem.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_mem.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Utility prototypes functions for memory/PMA transfers
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

89
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_regs.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_regs.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Interface prototype functions to USB cell registers
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -17,8 +17,6 @@
#ifndef __USB_REGS_H
#define __USB_REGS_H
#ifndef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
typedef enum _EP_DBUF_DIR
@ -60,34 +58,15 @@ enum EP_BUF_NUM
/******************************************************************************/
#define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */
/* Endpoint Addresses (w/direction) */
#define EP0_OUT ((uint8_t)0x00)
#define EP0_IN ((uint8_t)0x80)
#define EP1_OUT ((uint8_t)0x01)
#define EP1_IN ((uint8_t)0x81)
#define EP2_OUT ((uint8_t)0x02)
#define EP2_IN ((uint8_t)0x82)
#define EP3_OUT ((uint8_t)0x03)
#define EP3_IN ((uint8_t)0x83)
#define EP4_OUT ((uint8_t)0x04)
#define EP4_IN ((uint8_t)0x84)
#define EP5_OUT ((uint8_t)0x05)
#define EP5_IN ((uint8_t)0x85)
#define EP6_OUT ((uint8_t)0x06)
#define EP6_IN ((uint8_t)0x86)
#define EP7_OUT ((uint8_t)0x07)
#define EP7_IN ((uint8_t)0x87)
/* endpoints enumeration */
#define ENDP0 ((uint8_t)0)
#define ENDP1 ((uint8_t)1)
#define ENDP2 ((uint8_t)2)
#define ENDP3 ((uint8_t)3)
#define ENDP4 ((uint8_t)4)
#define ENDP5 ((uint8_t)5)
#define ENDP6 ((uint8_t)6)
#define ENDP7 ((uint8_t)7)
#define ENDP0 ((uint8_t)0)
#define ENDP1 ((uint8_t)1)
#define ENDP2 ((uint8_t)2)
#define ENDP3 ((uint8_t)3)
#define ENDP4 ((uint8_t)4)
#define ENDP5 ((uint8_t)5)
#define ENDP6 ((uint8_t)6)
#define ENDP7 ((uint8_t)7)
/******************************************************************************/
/* ISTR interrupt events */
/******************************************************************************/
@ -231,12 +210,12 @@ enum EP_BUF_NUM
* Macro Name : SetEPType
* Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
* Input : bEpNum: Endpoint Number.
* wType
* wType
* Output : None.
* Return : None.
*******************************************************************************/
#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType )))
((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
/*******************************************************************************
* Macro Name : GetEPType
@ -264,7 +243,7 @@ enum EP_BUF_NUM
/* toggle second bit ? */ \
if((EPTX_DTOG2 & wState)!= 0) \
_wRegVal ^= EPTX_DTOG2; \
_SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
_SetENDPOINT(bEpNum, _wRegVal); \
} /* _SetEPTxStatus */
/*******************************************************************************
@ -285,36 +264,8 @@ enum EP_BUF_NUM
/* toggle second bit ? */ \
if((EPRX_DTOG2 & wState)!= 0) \
_wRegVal ^= EPRX_DTOG2; \
_SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
_SetENDPOINT(bEpNum, _wRegVal); \
} /* _SetEPRxStatus */
/*******************************************************************************
* Macro Name : SetEPRxTxStatus
* Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
* Input : bEpNum: Endpoint Number.
* wStaterx: new state.
* wStatetx: new state.
* Output : None.
* Return : None.
*******************************************************************************/
#define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\
register uint32_t _wRegVal; \
\
_wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\
/* toggle first bit ? */ \
if((EPRX_DTOG1 & wStaterx)!= 0) \
_wRegVal ^= EPRX_DTOG1; \
/* toggle second bit ? */ \
if((EPRX_DTOG2 & wStaterx)!= 0) \
_wRegVal ^= EPRX_DTOG2; \
/* toggle first bit ? */ \
if((EPTX_DTOG1 & wStatetx)!= 0) \
_wRegVal ^= EPTX_DTOG1; \
/* toggle second bit ? */ \
if((EPTX_DTOG2 & wStatetx)!= 0) \
_wRegVal ^= EPTX_DTOG2; \
_SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX); \
} /* _SetEPRxTxStatus */
/*******************************************************************************
* Macro Name : GetEPTxStatus / GetEPRxStatus
* Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
@ -358,9 +309,9 @@ enum EP_BUF_NUM
* Return : None.
*******************************************************************************/
#define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \
(EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
(_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))
#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \
(EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK))))
(_GetENDPOINT(bEpNum) & EPKIND_MASK)))
/*******************************************************************************
* Macro Name : Set_Status_Out / Clear_Status_Out.
@ -402,9 +353,9 @@ enum EP_BUF_NUM
* Return : None.
*******************************************************************************/
#define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \
EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
EP_DTOG_RX | _GetENDPOINT(bEpNum) & EPREG_MASK))
#define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \
EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
EP_DTOG_TX | _GetENDPOINT(bEpNum) & EPREG_MASK))
/*******************************************************************************
* Macro Name : ClearDTOG_RX / ClearDTOG_TX.
@ -426,7 +377,7 @@ enum EP_BUF_NUM
* Return : None.
*******************************************************************************/
#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
_GetENDPOINT(bEpNum) & EPREG_MASK | bAddr)
/*******************************************************************************
* Macro Name : GetEPAddress.
@ -664,8 +615,6 @@ void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir);
uint16_t ToWord(uint8_t, uint8_t);
uint16_t ByteSwap(uint16_t);
#endif /* STM32F10X_CL */
#endif /* __USB_REGS_H */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

34
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_sil.h
View File

@ -1,34 +0,0 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_sil.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Description : Simplified Interface Layer function prototypes.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_SIL_H
#define __USB_SIL_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
uint32_t USB_SIL_Init(void);
uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer);
/* External variables --------------------------------------------------------*/
#endif /* __USB_SIL_H */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

7
flight/Libraries/STM32_USB-FS-Device_Driver/inc/usb_type.h
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_type.h
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Type definitions used by the USB Library
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -18,7 +18,8 @@
#define __USB_TYPE_H
/* Includes ------------------------------------------------------------------*/
#include "usb_conf.h"
// TK: disabled, as not required for integration of STM32 drivers!
// #include "usb_conf.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

1273
flight/Libraries/STM32_USB-FS-Device_Driver/src/otgd_fs_cal.c
View File

@ -1,1273 +0,0 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_cal.c
* Author : STMicroelectronics
* Version : V3.1.0
* Date : 10/30/2009
* Description : OTG FS Device Core Access Layer interface.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifdef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
#include "otgd_fs_cal.h"
#include "usb_conf.h"
#include "otgd_fs_regs.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
USB_OTG_CORE_REGS core_regs;
/* Private function prototypes -----------------------------------------------*/
static uint32_t GetMode(void);
static void EnableCommonInt(void);
static USB_OTG_Status SetID(void);
static USB_OTG_Status OTGD_FS_CoreReset(void);
extern uint32_t STM32_USBH_OTG_ISR_Handler (void);
extern uint32_t STM32_PCD_OTG_ISR_Handler (void);
extern uint32_t STM32_USBO_OTG_ISR_Handler (void);
#ifdef HOST_MODE_ENABLED
static void InitFSLSPClkSel(void);
#endif
/******************************************************************************/
/* Common Core Layer */
/******************************************************************************/
/*******************************************************************************
* Function Name : OTGD_FS_PhyInit
* Description : Initialize the phy
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_PhyInit(void)
{
USB_OTG_gpio_data gpioctl;
USB_OTG_usb_cfg_data usbcfg;
USB_OTG_Status status = USB_OTG_OK;
/* Enable the I2C interface and deactivate the power down*/
gpioctl.d32 = 0;
gpioctl.b.vbussensingB = 1;
gpioctl.b.pwdn = 1;
gpioctl.b.i2cifen = 0;
WRITE_REG32 (&core_regs.common_regs->gpio, gpioctl.d32);
mDELAY(200);
/* Program GUSBCFG.OtgUtmifsSel to I2C*/
usbcfg.d32 = READ_REG32(&core_regs.common_regs->usb_cfg);
usbcfg.b.otgutmifssel = 0;
WRITE_REG32 (&core_regs.common_regs->usb_cfg, usbcfg.d32);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_WritePacket
* Description : Writes a packet into the Tx FIFO associated with the EP
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_WritePacket(uint8_t *src, uint8_t ch_ep_num, uint16_t bytes)
{
USB_OTG_Status status = USB_OTG_OK;
uint32_t dword_count , i;
__IO uint32_t *fifo;
/* Find the DWORD length, padded by extra bytes as neccessary if MPS
* is not a multiple of DWORD */
dword_count = (bytes + 3) / 4;
fifo = core_regs.data_fifo[ch_ep_num];
for (i = 0; i < dword_count; i++, src += 4)
{
WRITE_REG32( fifo, *((__packed uint32_t *)src) );
}
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_ReadPacket
* Description : Reads a packet from the Rx FIFO
* Input : None
* Output : None
* Return : status
*******************************************************************************/
void* OTGD_FS_ReadPacket(uint8_t *dest, uint16_t bytes)
{
uint32_t i;
uint32_t word_count = (bytes + 3) / 4;
__IO uint32_t *fifo = core_regs.data_fifo[0];
uint32_t *data_buff = (uint32_t *)dest;
for (i = 0; i < word_count; i++, data_buff++)
{
*data_buff = READ_REG32(fifo);
}
/* Return the buffer pointer because if the transfer is composed of several packets,
the data of the next packet must be stored following the previous packet's data */
return ((void *)data_buff);
}
/*******************************************************************************
* Function Name : EnableCommonInt
* Description : initializes the commmon interrupts, used in both device and
host modes
* Input : None
* Output : None
* Return : None
*******************************************************************************/
static void EnableCommonInt(void)
{
USB_OTG_int_msk_data int_mask;
int_mask.d32 = 0;
/* Clear any pending USB_OTG Interrupts */
WRITE_REG32( &core_regs.common_regs->otg_int, 0xFFFFFFFF);
/* Clear any pending common interrupts */
WRITE_REG32( &core_regs.common_regs->int_sts, 0xFFFFFFFF);
WRITE_REG32( &core_regs.common_regs->int_msk, int_mask.d32);
}
/*******************************************************************************
* Function Name : OTGD_FS_SetAddress
* Description : Initialize core registers addresses.
* Input : BaseAddress
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_SetAddress(uint32_t BaseAddress)
{
uint32_t i = 0;
USB_OTG_Status status = USB_OTG_OK;
core_regs.common_regs = (USB_OTG_common_regs *)(BaseAddress + USB_OTG_CORE_GLOBAL_REGS_OFFSET);
core_regs.dev_regs = (USB_OTG_dev_regs *) (BaseAddress + USB_OTG_DEV_GLOBAL_REG_OFFSET);
for (i = 0; i < MAX_EPS_CHANNELS; i++)
{
core_regs.inep_regs[i] = (USB_OTG_dev_in_ep_regs *) (BaseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + (i * USB_OTG_EP_REG_OFFSET));
core_regs.outep_regs[i] = (USB_OTG_dev_out_ep_regs *) (BaseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + (i * USB_OTG_EP_REG_OFFSET));
}
core_regs.host_regs = (USB_OTG_host_regs *)(BaseAddress + USB_OTG_HOST_GLOBAL_REG_OFFSET);
core_regs.hprt0 = (uint32_t *)(BaseAddress + USB_OTG_HOST_PORT_REGS_OFFSET);
for (i = 0; i < MAX_EPS_CHANNELS; i++)
{
core_regs.hc_regs[i] = (USB_OTG_hc_regs *)(BaseAddress + USB_OTG_HOST_CHAN_REGS_OFFSET + (i * USB_OTG_CHAN_REGS_OFFSET));
}
for (i = 0; i < MAX_EPS_CHANNELS; i++)
{
core_regs.data_fifo[i] = (uint32_t *)(BaseAddress + USB_OTG_DATA_FIFO_OFFSET + (i * USB_OTG_DATA_FIFO_SIZE));
}
core_regs.pcgcctl = (uint32_t *)(BaseAddress + USB_OTG_PCGCCTL_OFFSET);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_CoreInit
* Description : Initialize the USB_OTG controller registers and prepares the core
for device mode or host mode operation.
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_CoreInit(void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_usb_cfg_data usbcfg;
usbcfg.d32 = 0;
/* Reset the Controller */
OTGD_FS_CoreReset();
usbcfg.d32 = READ_REG32(&core_regs.common_regs->usb_cfg);
usbcfg.b.physel = 1;
WRITE_REG32 (&core_regs.common_regs->usb_cfg, usbcfg.d32);
/* init and configure the phy */
OTGD_FS_PhyInit();
/* Reset after a PHY select and set Host mode */
OTGD_FS_CoreReset();
/* Set Host or Device Mode */
SetID();
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_CoreReset
* Description : Soft reset of the core
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
static USB_OTG_Status OTGD_FS_CoreReset(void)
{
USB_OTG_Status status = USB_OTG_OK;
__IO USB_OTG_rst_ctl_data greset;
uint32_t count = 0;
greset.d32 = 0;
/* Wait for AHB master IDLE state. */
do
{
uDELAY(3);
greset.d32 = READ_REG32(&core_regs.common_regs->rst_ctl);
if (++count > 200000)
{
return USB_OTG_OK;
}
}
while (greset.b.ahbidle == 0);
/* Core Soft Reset */
count = 0;
greset.b.csftrst = 1;
WRITE_REG32(&core_regs.common_regs->rst_ctl, greset.d32 );
do
{
greset.d32 = READ_REG32(&core_regs.common_regs->rst_ctl);
if (++count > 200000)
{
break;
}
}
while (greset.b.csftrst == 1);
/* Wait for 3 PHY Clocks*/
uDELAY(10);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EnableGlobalInt
* Description : Enables the controller's Global Int in the AHB Config reg
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EnableGlobalInt(void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_ahb_cfg_data ahb_cfg;
ahb_cfg.d32 = 0;
ahb_cfg.b.glblintrmsk = 1; /* Enable interrupts */
MODIFY_REG32(&core_regs.common_regs->ahb_cfg, 0, ahb_cfg.d32);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_DisableGlobalInt
* Description : Disables the controller's Global Int in the AHB Config reg
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_DisableGlobalInt(void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_ahb_cfg_data ahbcfg;
ahbcfg.d32 = 0;
ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
MODIFY_REG32(&core_regs.common_regs->ahb_cfg, ahbcfg.d32, 0);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_FlushTxFifo
* Description : Flush a Tx FIFO
* Input : FIFO num
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_FlushTxFifo (uint32_t num )
{
USB_OTG_Status status = USB_OTG_OK;
__IO USB_OTG_rst_ctl_data greset;
int count = 0;
greset.d32 = 0;
greset.b.txfflsh = 1;
greset.b.txfnum = num;
WRITE_REG32( &core_regs.common_regs->rst_ctl, greset.d32 );
do
{
greset.d32 = READ_REG32( &core_regs.common_regs->rst_ctl);
if (++count > 200000)
{
break;
}
}
while (greset.b.txfflsh == 1);
/* Wait for 3 PHY Clocks*/
uDELAY(3);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_FlushRxFifo
* Description : Flush a Rx FIFO
* Input : None
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_FlushRxFifo( void )
{
USB_OTG_Status status = USB_OTG_OK;
__IO USB_OTG_rst_ctl_data greset;
int count = 0;
greset.d32 = 0;
greset.b.rxfflsh = 1;
WRITE_REG32( &core_regs.common_regs->rst_ctl, greset.d32 );
do
{
greset.d32 = READ_REG32( &core_regs.common_regs->rst_ctl);
if (++count > 200000)
{
break;
}
}
while (greset.b.rxfflsh == 1);
/* Wait for 3 PHY Clocks*/
uDELAY(3);
return status;
}
/*******************************************************************************
* Function Name : SetID
* Description : Set ID line
* Input : None
* Output : None
* Return : num_in_ep
*******************************************************************************/
USB_OTG_Status SetID(void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_usb_cfg_data usbcfg;
usbcfg.d32 = READ_REG32(&core_regs.common_regs->usb_cfg);
usbcfg.b.force_dev = 1;
WRITE_REG32(&core_regs.common_regs->usb_cfg, usbcfg.d32);
mDELAY(50);
return status;
}
/*******************************************************************************
* Function Name : GetMode
* Description : Get current mode
* Input : None
* Output : None
* Return : current mode
*******************************************************************************/
static uint32_t GetMode(void)
{
return (READ_REG32(&core_regs.common_regs->int_sts ) & 0x1);
}
/*******************************************************************************
* Function Name : IsDeviceMode
* Description : Check if it is device mode
* Input : None
* Output : None
* Return : num_in_ep
*******************************************************************************/
uint8_t IsDeviceMode(void)
{
return (GetMode() != HOST_MODE);
}
/*******************************************************************************
* Function Name : IsHostMode
* Description : Check if it is host mode
* Input : None
* Output : None
* Return : num_in_ep
*******************************************************************************/
uint8_t IsHostMode(void)
{
return (GetMode() == HOST_MODE);
}
/*******************************************************************************
* Function Name : OTGD_FS_ReadCoreItr
* Description : returns the Core Interrupt register
* Input : None
* Output : None
* Return : None
*******************************************************************************/
uint32_t OTGD_FS_ReadCoreItr(void)
{
uint32_t v;
v = READ_REG32(&core_regs.common_regs->int_sts);
v &= READ_REG32(&core_regs.common_regs->int_msk);
return v;
}
/*******************************************************************************
* Function Name : OTGD_FS_ReadOtgItr
* Description : returns the USB_OTG Interrupt register
* Input : None
* Output : None
* Return : None
*******************************************************************************/
uint32_t OTGD_FS_ReadOtgItr (void)
{
return (READ_REG32 (&core_regs.common_regs->otg_int));
}
/******************************************************************************/
/* PCD Core Layer */
/******************************************************************************/
/*******************************************************************************
* Function Name : InitDevSpeed
* Description : Initializes the DevSpd field of the DCFG register depending
on the PHY type and the enumeration speed of the device.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
static void InitDevSpeed(void)
{
USB_OTG_dev_cfg_data dcfg;
dcfg.d32 = READ_REG32(&core_regs.dev_regs->dev_cfg);
dcfg.b.devspd = 0x3; /* Full speed PHY */
WRITE_REG32(&core_regs.dev_regs->dev_cfg, dcfg.d32);
}
/*******************************************************************************
* Function Name : OTGD_FS_CoreInitDev
* Description : Initialize the USB_OTG controller registers for device mode
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_CoreInitDev (void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_ep_ctl_data depctl;
uint32_t i;
USB_OTG_dev_cfg_data dcfg;
USB_OTG_fifo_size_data nptxfifosize;
USB_OTG_fifo_size_data txfifosize;
USB_OTG_dev_in_ep_msk_data msk;
dcfg.d32 = 0;
/* Set device speed */
InitDevSpeed ();
/* Restart the Phy Clock */
WRITE_REG32(core_regs.pcgcctl, 0);
/* Device configuration register */
dcfg.d32 = READ_REG32( &core_regs.dev_regs->dev_cfg);
dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
WRITE_REG32( &core_regs.dev_regs->dev_cfg, dcfg.d32 );
/* set Rx FIFO size */
WRITE_REG32( &core_regs.common_regs->rx_fifo_siz, RX_FIFO_SIZE);
/* Non-periodic Tx FIFO */
nptxfifosize.b.depth = DEV_NP_TX_FIFO_SIZE;
nptxfifosize.b.startaddr = RX_FIFO_SIZE;
WRITE_REG32( &core_regs.common_regs->np_tx_fifo_siz, nptxfifosize.d32 );
txfifosize.b.depth = DEV_NP_TX_FIFO_SIZE;
WRITE_REG32( &core_regs.common_regs->dev_p_tx_fsiz_dieptxf[0], txfifosize.d32 );
txfifosize.b.startaddr += txfifosize.b.depth;
txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
/* Flush the FIFOs */
OTGD_FS_FlushTxFifo(0x10); /* all Tx FIFOs */
OTGD_FS_FlushRxFifo();
/* Clear all pending Device Interrupts */
WRITE_REG32( &core_regs.dev_regs->dev_in_ep_msk, 0 );
WRITE_REG32( &core_regs.dev_regs->dev_out_ep_msk, 0 );
WRITE_REG32( &core_regs.dev_regs->dev_all_int, 0xFFFFFFFF );
WRITE_REG32( &core_regs.dev_regs->dev_all_int_msk, 0 );
for (i = 0; i <= MAX_TX_FIFOS; i++)
{
depctl.d32 = READ_REG32(&core_regs.inep_regs[i]->dev_in_ep_ctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_ctl, depctl.d32);
WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_txfer_siz, 0);
WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_int, 0xFF);
}
for (i = 0; i < 1/* NUM_OUT_EPS*/; i++)
{
depctl.d32 = READ_REG32(&core_regs.outep_regs[i]->dev_out_ep_ctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_ctl, depctl.d32);
WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_txfer_siz, 0);
WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_int, 0xFF);
}
msk.d32 = 0;
msk.b.txfifoundrn = 1;
MODIFY_REG32(&core_regs.dev_regs->dev_in_ep_msk, msk.d32, msk.d32);
OTGD_FS_EnableDevInt();
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EnableDevInt
* Description : Enables the Device mode interrupts
* Input : None
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EnableDevInt(void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_int_msk_data intr_mask;
intr_mask.d32 = 0;
/* Disable all interrupts. */
WRITE_REG32( &core_regs.common_regs->int_msk, 0);
/* Clear any pending interrupts */
WRITE_REG32( &core_regs.common_regs->int_sts, 0xFFFFFFFF);
/* Enable the common interrupts */
EnableCommonInt();
/* Enable the defined interrupts*/
#ifdef INTR_MODEMISMATCH
intr_mask.b.modemismatch = 1;
#endif /* INTR_MODEMISMATCH */
#ifdef INTR_SOFINTR
intr_mask.b.sofintr = 1;
#endif /* INTR_SOFINTR */
#ifdef INTR_RXSTSQLVL
intr_mask.b.rxstsqlvl = 1;
#endif /* INTR_RXSTSQLVL */
#ifdef INTR_NPTXFEMPTY
intr_mask.b.nptxfempty = 1;
#endif /* INTR_NPTXFEMPTY */
#ifdef INTR_GINNAKEFF
intr_mask.b.ginnakeff = 1;
#endif /* INTR_GINNAKEFF */
#ifdef INTR_GOUTNAKEFF
intr_mask.b.goutnakeff = 1;
#endif /* INTR_GOUTNAKEFF */
#ifdef INTR_ERLYSUSPEND
intr_mask.b.erlysuspend = 1;
#endif /* INTR_ERLYSUSPEND */
#ifdef INTR_USBSUSPEND
intr_mask.b.usbsuspend = 1;
#endif /* INTR_USBSUSPEND */
#ifdef INTR_USBRESET
intr_mask.b.usbreset = 1;
#endif /* INTR_USBRESET */
#ifdef INTR_ENUMDONE
intr_mask.b.enumdone = 1;
#endif /* INTR_ENUMDONE */
#ifdef INTR_ISOOUTDROP
intr_mask.b.isooutdrop = 1;
#endif /* INTR_ISOOUTDROP */
#ifdef INTR_EOPFRAME
intr_mask.b.eopframe = 1;
#endif /* INTR_EOPFRAME */
#ifdef INTR_EPMISMATCH
intr_mask.b.epmismatch = 1;
#endif /* INTR_EPMISMATCH */
#ifdef INTR_INEPINTR
intr_mask.b.inepintr = 1;
#endif /* INTR_INEPINTR */
#ifdef INTR_OUTEPINTR
intr_mask.b.outepintr = 1;
#endif /* INTR_OUTEPINTR */
#ifdef INTR_INCOMPLISOIN
intr_mask.b.incomplisoin = 1;
#endif /* INTR_INCOMPLISOIN */
#ifdef INTR_INCOMPLISOOUT
intr_mask.b.incomplisoout = 1;
#endif /* INTR_INCOMPLISOOUT */
#ifdef INTR_DISCONNECT
intr_mask.b.disconnect = 1;
#endif /* INTR_DISCONNECT */
#ifdef INTR_WKUPINTR
intr_mask.b.wkupintr = 1;
#endif /* INTR_WKUPINTR */
MODIFY_REG32( &core_regs.common_regs->int_msk, intr_mask.d32, intr_mask.d32);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EP0Activate
* Description : enables EP0 OUT to receive SETUP packets and configures EP0
IN for transmitting packets
* Input : None
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EP0Activate(void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_sts_data dsts;
USB_OTG_dev_ep_ctl_data diepctl;
USB_OTG_dev_ctl_data dctl;
dctl.d32 = 0;
/* Read the Device Status and Endpoint 0 Control registers */
dsts.d32 = READ_REG32(&core_regs.dev_regs->dev_sts);
diepctl.d32 = READ_REG32(&core_regs.inep_regs[0]->dev_in_ep_ctl);
/* Set the MPS of the IN EP based on the enumeration speed */
switch (dsts.b.enumspd)
{
case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
case DSTS_ENUMSPD_FS_PHY_48MHZ:
diepctl.b.mps = DEP0CTL_MPS_64;
break;
case DSTS_ENUMSPD_LS_PHY_6MHZ:
diepctl.b.mps = DEP0CTL_MPS_8;
break;
}
WRITE_REG32(&core_regs.inep_regs[0]->dev_in_ep_ctl, diepctl.d32);
dctl.b.cgnpinnak = 1;
MODIFY_REG32(&core_regs.dev_regs->dev_ctl, dctl.d32, dctl.d32);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EPActivate
* Description : Activates an EP
* Input : ep
* Output : None
* Return : num_in_ep
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPActivate(USB_OTG_EP *ep)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_ep_ctl_data depctl;
__IO uint32_t *addr;
USB_OTG_dev_all_int_data daintmsk;
daintmsk.d32 = 0;
/* Read DEPCTLn register */
if (ep->is_in == 1)
{
addr = &core_regs.inep_regs[ep->num]->dev_in_ep_ctl;
daintmsk.ep.in = 1 << ep->num;
}
else
{
addr = &core_regs.outep_regs[ep->num]->dev_out_ep_ctl;
daintmsk.ep.out = 1 << ep->num;
}
/* If the EP is already active don't change the EP Control
* register. */
depctl.d32 = READ_REG32(addr);
if (!depctl.b.usbactep)
{
depctl.b.mps = ep->maxpacket;
depctl.b.eptype = ep->type;
depctl.b.txfnum = ep->tx_fifo_num;
depctl.b.setd0pid = 1;
depctl.b.usbactep = 1;
WRITE_REG32(addr, depctl.d32);
}
/* Enable the Interrupt for this EP */
MODIFY_REG32(&core_regs.dev_regs->dev_all_int_msk, 0, daintmsk.d32);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EPDeactivate
* Description : Deactivates an EP
* Input : ep
* Output : None
* Return : num_in_ep
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPDeactivate(USB_OTG_EP *ep)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_ep_ctl_data depctl;
__IO uint32_t *addr;
USB_OTG_dev_all_int_data daintmsk;
depctl.d32 = 0;
daintmsk.d32 = 0;
/* Read DEPCTLn register */
if (ep->is_in == 1)
{
addr = &core_regs.inep_regs[ep->num]->dev_in_ep_ctl;
daintmsk.ep.in = 1 << ep->num;
}
else
{
addr = &core_regs.outep_regs[ep->num]->dev_out_ep_ctl;
daintmsk.ep.out = 1 << ep->num;
}
depctl.b.usbactep = 0;
WRITE_REG32(addr, depctl.d32);
/* Disable the Interrupt for this EP */
MODIFY_REG32(&core_regs.dev_regs->dev_all_int_msk, daintmsk.d32, 0);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EPStartXfer
* Description : Handle the setup for data xfer for an EP and starts the xfer
* Input : None
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPStartXfer(USB_OTG_EP *ep)
{
USB_OTG_Status status = USB_OTG_OK;
__IO USB_OTG_dev_ep_ctl_data depctl;
USB_OTG_dev_ep_txfer_siz_data deptsiz;
/* IN endpoint */
if (ep->is_in == 1)
{
depctl.d32 = READ_REG32(&(core_regs.inep_regs[ep->num]->dev_in_ep_ctl));
deptsiz.d32 = READ_REG32(&(core_regs.inep_regs[ep->num]->dev_in_ep_txfer_siz));
/* Zero Length Packet? */
if (ep->xfer_len == 0)
{
deptsiz.b.xfersize = 0;
deptsiz.b.pktcnt = 1;
}
else
{
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
deptsiz.b.xfersize = ep->xfer_len;
deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
}
WRITE_REG32(&core_regs.inep_regs[ep->num]->dev_in_ep_txfer_siz, deptsiz.d32);
if (ep->type != EP_TYPE_ISOC)
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
uint32_t fifoemptymsk = 0;
fifoemptymsk = 1 << ep->num;
MODIFY_REG32(&core_regs.dev_regs->dev_fifo_empty_msk, 0, fifoemptymsk);
}
/* EP enable, IN data in FIFO */
depctl.b.cnak = 1;
depctl.b.epena = 1;
WRITE_REG32(&core_regs.inep_regs[ep->num]->dev_in_ep_ctl, depctl.d32);
depctl.d32 = READ_REG32 (&core_regs.inep_regs[0]->dev_in_ep_ctl);
depctl.b.nextep = ep->num;
WRITE_REG32 (&core_regs.inep_regs[0]->dev_in_ep_ctl, depctl.d32);
}
else
{
/* OUT endpoint */
depctl.d32 = READ_REG32(&(core_regs.outep_regs[ep->num]->dev_out_ep_ctl));
deptsiz.d32 = READ_REG32(&(core_regs.outep_regs[ep->num]->dev_out_ep_txfer_siz));
/* Program the transfer size and packet count as follows:
* pktcnt = N
* xfersize = N * maxpacket
*/
if (ep->xfer_len == 0)
{
deptsiz.b.xfersize = ep->maxpacket;
deptsiz.b.pktcnt = 1;
}
else
{
deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
}
WRITE_REG32(&core_regs.outep_regs[ep->num]->dev_out_ep_txfer_siz, deptsiz.d32);
if (ep->type == EP_TYPE_ISOC)
{
if (ep->even_odd_frame)
{
depctl.b.setd1pid = 1;
}
else
{
depctl.b.setd0pid = 1;
}
}
/* EP enable */
depctl.b.cnak = 1;
depctl.b.epena = 1;
WRITE_REG32(&core_regs.outep_regs[ep->num]->dev_out_ep_ctl, depctl.d32);
}
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EP0StartXfer
* Description : Handle the setup for a data xfer for EP0 and starts the xfer
* Input : None
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EP0StartXfer(USB_OTG_EP *ep)
{
USB_OTG_Status status = USB_OTG_OK;
uint32_t fifoemptymsk = 0;
USB_OTG_dev_ep_ctl_data depctl;
USB_OTG_dev_ep_txfer_size0_data deptsiz;
USB_OTG_dev_in_ep_regs *in_regs ;
/* IN endpoint */
if (ep->is_in == 1)
{
in_regs = core_regs.inep_regs[0];
depctl.d32 = READ_REG32(&in_regs->dev_in_ep_ctl);
deptsiz.d32 = READ_REG32(&in_regs->dev_in_ep_txfer_siz);
/* Zero Length Packet? */
if (ep->xfer_len == 0)
{
deptsiz.b.xfersize = 0;
deptsiz.b.pktcnt = 1;
}
else
{
if (ep->xfer_len > ep->maxpacket)
{
ep->xfer_len = ep->maxpacket;
deptsiz.b.xfersize = ep->maxpacket;
}
else
{
deptsiz.b.xfersize = ep->xfer_len;
}
deptsiz.b.pktcnt = 1;
}
WRITE_REG32(&in_regs->dev_in_ep_txfer_siz, deptsiz.d32);
/* EP enable, IN data in FIFO */
depctl.b.cnak = 1;
depctl.b.epena = 1;
WRITE_REG32(&in_regs->dev_in_ep_ctl, depctl.d32);
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
fifoemptymsk |= 1 << ep->num;
MODIFY_REG32(&core_regs.dev_regs->dev_fifo_empty_msk, 0, fifoemptymsk);
}
}
else
{
/* OUT endpoint */
depctl.d32 = READ_REG32(&core_regs.outep_regs[ep->num]->dev_out_ep_ctl);
deptsiz.d32 = READ_REG32(&core_regs.outep_regs[ep->num]->dev_out_ep_txfer_siz);
/* Program the transfer size and packet count as follows:
* xfersize = N * (maxpacket + 4 - (maxpacket % 4))
* pktcnt = N */
if (ep->xfer_len == 0)
{
deptsiz.b.xfersize = ep->maxpacket;
deptsiz.b.pktcnt = 1;
}
else
{
deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
}
WRITE_REG32(&core_regs.outep_regs[ep->num]->dev_out_ep_txfer_siz, deptsiz.d32);
/* EP enable */
depctl.b.cnak = 1;
depctl.b.epena = 1;
WRITE_REG32 (&(core_regs.outep_regs[ep->num]->dev_out_ep_ctl), depctl.d32);
}
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EPSetStall
* Description : Set the EP STALL
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPSetStall(USB_OTG_EP *ep)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_ep_ctl_data depctl;
__IO uint32_t *depctl_addr;
if (ep->is_in == 1)
{
depctl_addr = &(core_regs.inep_regs[ep->num]->dev_in_ep_ctl);
depctl.d32 = READ_REG32(depctl_addr);
/* set the disable and stall bits */
if (depctl.b.epena)
{
depctl.b.epdis = 1;
}
depctl.b.stall = 1;
WRITE_REG32(depctl_addr, depctl.d32);
}
else
{
depctl_addr = &(core_regs.outep_regs[ep->num]->dev_out_ep_ctl);
depctl.d32 = READ_REG32(depctl_addr);
/* set the stall bit */
depctl.b.stall = 1;
WRITE_REG32(depctl_addr, depctl.d32);
}
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_EPClearStall
* Description : Clear the EP STALL
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPClearStall(USB_OTG_EP *ep)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_ep_ctl_data depctl;
__IO uint32_t *depctl_addr;
if (ep->is_in == 1)
{
depctl_addr = &(core_regs.inep_regs[ep->num]->dev_in_ep_ctl);
}
else
{
depctl_addr = &(core_regs.outep_regs[ep->num]->dev_out_ep_ctl);
}
depctl.d32 = READ_REG32(depctl_addr);
/* clear the stall bits */
depctl.b.stall = 0;
if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
{
depctl.b.setd0pid = 1; /* DATA0 */
}
WRITE_REG32(depctl_addr, depctl.d32);
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_ReadDevAllOutEp_itr
* Description : returns the OUT endpoint interrupt bits
* Input : None
* Output : None
* Return : None
*******************************************************************************/
uint32_t OTGD_FS_ReadDevAllOutEp_itr(void)
{
uint32_t v;
v = READ_REG32(&core_regs.dev_regs->dev_all_int);
v &= READ_REG32(&core_regs.dev_regs->dev_all_int_msk);
return ((v & 0xffff0000) >> 16);
}
/*******************************************************************************
* Function Name : OTGD_FS_ReadDevOutEP_itr
* Description : returns the Device OUT EP Interrupt register
* Input : None
* Output : None
* Return : None
*******************************************************************************/
uint32_t OTGD_FS_ReadDevOutEP_itr(USB_OTG_EP *ep)
{
uint32_t v;
v = READ_REG32(&core_regs.outep_regs[ep->num]->dev_out_ep_int);
v &= READ_REG32(&core_regs.dev_regs->dev_out_ep_msk);
return v;
}
/*******************************************************************************
* Function Name : OTGD_FS_ReadDevAllInEPItr
* Description : Get int status register
* Input : None
* Output : None
* Return : None
*******************************************************************************/
uint32_t OTGD_FS_ReadDevAllInEPItr(void)
{
uint32_t v;
v = READ_REG32(&core_regs.dev_regs->dev_all_int);
v &= READ_REG32(&core_regs.dev_regs->dev_all_int_msk);
return (v & 0xffff);
}
/*******************************************************************************
* Function Name : OTGD_FS_Dev_GetEPStatus
* Description : returns the EP Status
* Input : - ep: pointer to the EP structure
* Output : None
* Return : status: DEV_EP_TX_STALL, DEV_EP_TX_VALID, DEV_EP_TX_NAK,
* DEV_EP_RX_STALL, DEV_EP_RX_VALID or DEV_EP_RX_NAK,
*******************************************************************************/
uint32_t OTGD_FS_Dev_GetEPStatus(USB_OTG_EP *ep)
{
USB_OTG_dev_ep_ctl_data depctl;
__IO uint32_t *depctl_addr;
uint32_t Status = 0;
if (ep->is_in == 1)
{
depctl_addr = &(core_regs.inep_regs[ep->num]->dev_in_ep_ctl);
}
else
{
depctl_addr = &(core_regs.outep_regs[ep->num]->dev_out_ep_ctl);
}
depctl.d32 = READ_REG32(depctl_addr);
/* Process for IN endpoint */
if (ep->is_in == 1)
{
if (depctl.b.stall == 1)
Status = DEV_EP_TX_STALL;
else if (depctl.b.naksts == 1)
Status = DEV_EP_TX_NAK;
else
Status = DEV_EP_TX_VALID;
}
/* Process for OUT endpoint */
else
{
if (depctl.b.stall == 1)
Status = DEV_EP_RX_STALL;
else if (depctl.b.naksts == 1)
Status = DEV_EP_RX_NAK;
else
Status = DEV_EP_RX_VALID;
}
/* Return the current status */
return Status;
}
/*******************************************************************************
* Function Name : OTGD_FS_Dev_SetEPStatus
* Description : Sets the EP Status
* Input : - ep: pointer to the EP structure
* - Status: new status to be set
* Output : None
* Return : None
*******************************************************************************/
void OTGD_FS_Dev_SetEPStatus(USB_OTG_EP *ep, uint32_t Status)
{
USB_OTG_dev_ep_ctl_data depctl;
__IO uint32_t *depctl_addr;
if (ep->is_in == 1)
{
depctl_addr = &(core_regs.inep_regs[ep->num]->dev_in_ep_ctl);
}
else
{
depctl_addr = &(core_regs.outep_regs[ep->num]->dev_out_ep_ctl);
}
depctl.d32 = READ_REG32(depctl_addr);
/* Process for IN endpoint */
if (ep->is_in == 1)
{
if (Status == DEV_EP_TX_STALL)
{
OTGD_FS_EPSetStall(ep); return;
}
else if (Status == DEV_EP_TX_NAK)
depctl.b.snak = 1;
else if (Status == DEV_EP_TX_VALID)
{
if (depctl.b.stall == 1)
{
ep->even_odd_frame = 0;
OTGD_FS_EPClearStall(ep);
return;
}
depctl.b.cnak = 1;
depctl.b.usbactep = 1;
depctl.b.epena = 1;
}
else if (Status == DEV_EP_TX_DIS)
depctl.b.usbactep = 0;
}
else /* Process for OUT endpoint */
{
if (Status == DEV_EP_RX_STALL)
depctl.b.stall = 1;
else if (Status == DEV_EP_RX_NAK)
depctl.b.snak = 1;
else if (Status == DEV_EP_RX_VALID)
{
if (depctl.b.stall == 1)
{
ep->even_odd_frame = 0;
OTGD_FS_EPClearStall(ep);
return;
}
depctl.b.cnak = 1;
depctl.b.usbactep = 1;
depctl.b.epena = 1;
}
else if (Status == DEV_EP_RX_DIS)
{
depctl.b.usbactep = 0;
}
}
if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
{
depctl.b.setd0pid = 1; /* DATA0 */
}
WRITE_REG32(depctl_addr, depctl.d32);
}
/*******************************************************************************
* Function Name : OTGD_FS_Dev_SetRemoteWakeup
* Description : Enable Remote wakeup signaling
* Input : None
* Output : None
* Return : status
*******************************************************************************/
void OTGD_FS_Dev_SetRemoteWakeup()
{
USB_OTG_dev_ctl_data devctl;
__IO uint32_t *dctl_addr;
dctl_addr = &(core_regs.dev_regs->dev_ctl);
devctl.d32 = READ_REG32( dctl_addr);
/* Enable the Remote Wakeup signal */
devctl.b.rmtwkupsig = 1;
WRITE_REG32(dctl_addr, devctl.d32);
}
/*******************************************************************************
* Function Name : OTGD_FS_Dev_ResetRemoteWakeup
* Description : Disable Remote wakeup signaling
* Input : None
* Output : None
* Return : status
*******************************************************************************/
void OTGD_FS_Dev_ResetRemoteWakeup()
{
USB_OTG_dev_ctl_data devctl;
__IO uint32_t *dctl_addr;
dctl_addr = &(core_regs.dev_regs->dev_ctl);
devctl.d32 = READ_REG32( dctl_addr);
/* Disable the Remote Wakeup signal */
devctl.b.rmtwkupsig = 0;
WRITE_REG32(dctl_addr, devctl.d32);
}
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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flight/Libraries/STM32_USB-FS-Device_Driver/src/otgd_fs_dev.c
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@ -1,385 +0,0 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_dev.c
* Author : STMicroelectronics
* Version : V3.1.0
* Date : 10/30/2009
* Description : High Layer device mode interface and wrapping layer.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifdef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
#include "otgd_fs_dev.h"
#include "usb_regs.h"
#include "otgd_fs_cal.h"
#include "otgd_fs_pcd.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Extern variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : OTG_DEV_Init
* Description : Initialize the OTG Device IP and EP0.
* Input : None.
* Output : None.
* Return : None.
*******************************************************************************/
void OTG_DEV_Init(void)
{
EP_DESCRIPTOR ep_descriptor;
USB_OTG_EP *ep;
/* Set the OTG_USB base registers address */
OTGD_FS_SetAddress(USB_OTG_FS1_BASE_ADDR);
/* Disable all global interrupts */
OTGD_FS_DisableGlobalInt();
/*Init the Core (common init.) */
OTGD_FS_CoreInit();
/* Init Device */
OTGD_FS_CoreInitDev();
/* Init internal driver structure */
OTGD_FS_PCD_Init();
/* Configure and open the IN control EP0 */
ep_descriptor.bEndpointAddress = 0x80;
ep_descriptor.wMaxPacketSize = 64;
ep_descriptor.bmAttributes = USB_ENDPOINT_XFER_CONTROL;
OTGD_FS_PCD_EP_Open(&ep_descriptor);
/* Configure and open the OUT control EP0 */
ep_descriptor.bEndpointAddress = 0x00;
OTGD_FS_PCD_EP_Open(&ep_descriptor);
ep = OTGD_FS_PCD_GetOutEP(0);
OTGD_FS_EPStartXfer(ep);
/* Enable EP0 to start receiving setup packets */
OTGD_FS_PCD_EP0_OutStart();
/* Enable USB Global interrupt */
OTGD_FS_EnableGlobalInt();
}
/*******************************************************************************
* Function Name : OTG_DEV_EP_Init
* Description : Initialize the selected endpoint parameters
* Input : - bEpAdd: address of the endpoint (epnum|epdir)
* expample: EP1 OUT -> 0x01 and EP1 IN 0x81.
* - bEpType: OTG_DEV_EP_TYPE_CONTROL, OTG_DEV_EP_TYPE_ISOC,
* OTG_DEV_EP_TYPE_BULK, OTG_DEV_EP_TYPE_INT
* - wEpMaxPackSize: The EP max packet size.
* Output : None.
* Return : Status: New status to be set for the endpoint:
*******************************************************************************/
void OTG_DEV_EP_Init(uint8_t bEpAdd, uint8_t bEpType, uint16_t wEpMaxPackSize)
{
EP_DESCRIPTOR ep_descriptor;
USB_OTG_EP *ep;
/* Set the EP parameters in a structure */
ep_descriptor.bEndpointAddress = bEpAdd;
ep_descriptor.bmAttributes = bEpType;
ep_descriptor.wMaxPacketSize = wEpMaxPackSize;
OTGD_FS_PCD_EP_Flush(bEpAdd);
/* Open the EP with entered parameters */
OTGD_FS_PCD_EP_Open(&ep_descriptor);
/* Activate the EP if it is an OUT EP */
if ((bEpAdd & 0x80) == 0)
{
ep = OTGD_FS_PCD_GetOutEP(bEpAdd & 0x7F);
OTGD_FS_EPStartXfer(ep);
}
else
{
ep = OTGD_FS_PCD_GetInEP(bEpAdd & 0x7F);
ep->even_odd_frame = 0;
OTG_DEV_SetEPTxStatus(bEpAdd, DEV_EP_TX_NAK);
}
}
/*******************************************************************************
* Function Name : OTG_DEV_GetEPTxStatus
* Description : Set the related endpoint status.
* Input : Number of the endpoint.
* Output : None.
* Return : Status: New status to be set for the endpoint:
*******************************************************************************/
uint32_t OTG_DEV_GetEPTxStatus(uint8_t bEpnum)
{
USB_OTG_EP *ep;
uint32_t status = 0;
ep = OTGD_FS_PCD_GetInEP(bEpnum & 0x7F);
status = OTGD_FS_Dev_GetEPStatus(ep);
return status;
}
/*******************************************************************************
* Function Name : OTG_DEV_GetEPRxStatus
* Description : returns the related endpoint status.
* Input : Number of the endpoint.
* Output : None.
* Return : Status: New status to be set for the endpoint:
*******************************************************************************/
uint32_t OTG_DEV_GetEPRxStatus(uint8_t bEpnum)
{
USB_OTG_EP *ep;
uint32_t status = 0;
ep = OTGD_FS_PCD_GetOutEP(bEpnum & 0x7F);
status = OTGD_FS_Dev_GetEPStatus(ep);
return status;
}
/*******************************************************************************
* Function Name : OTG_DEV_SetEPTxStatus
* Description : Sets the related endpoint status.
* Input : - bEpnum: Number of the endpoint.
* - Status: New status to be set for the endpoint. It can be
* DEV_EP_TX_VALID, DEV_EP_TX_STALL, DEV_EP_TX_NAK or
* DEV_EP_TX_DISABLE.
* Output : None.
* Return : None.
*******************************************************************************/
void OTG_DEV_SetEPTxStatus(uint8_t bEpnum, uint32_t Status)
{
USB_OTG_EP *ep;
ep = OTGD_FS_PCD_GetInEP(bEpnum & 0x7F);
if ((bEpnum == 0x80) && (Status == DEV_EP_TX_STALL))
{
ep->is_in = 1;
}
OTGD_FS_Dev_SetEPStatus(ep, Status);
}
/*******************************************************************************
* Function Name : OTG_DEV_SetEPRxStatus
* Description : Sets the related endpoint status.
* Input : - bEpnum: Number of the endpoint.
* - Status: New status to be set for the endpoint. It can be
* DEV_EP_RX_VALID, DEV_EP_RX_STALL, DEV_EP_RX_NAK or
* DEV_EP_RX_DISABLE.
* Output : None.
* Return : None.
*******************************************************************************/
void OTG_DEV_SetEPRxStatus(uint8_t bEpnum, uint32_t Status)
{
USB_OTG_EP *ep;
ep = OTGD_FS_PCD_GetOutEP(bEpnum & 0x7F);
OTGD_FS_Dev_SetEPStatus(ep, Status);
}
/*******************************************************************************
* Function Name : USB_DevDisconnect
* Description : Disconnect the Pullup resist.
* Input : bEpNum: Endpoint Number.
* wState: new state.
* Output : None.
* Return : None.
*******************************************************************************/
void USB_DevDisconnect(void)
{
OTGD_FS_PCD_DevDisconnect();
}
/*******************************************************************************
* Function Name : USB_DevConnect
* Description : Disconnect the .
* Input : bEpNum: Endpoint Number.
* wState: new state.
* Output : None.
* Return : None.
*******************************************************************************/
void USB_DevConnect(void)
{
OTGD_FS_PCD_DevConnect();
}
/*-*-*-*-*-*-*-*-*-* Replace the usb_regs.h defines -*-*-*-*-*-*-*-*-*-*-*-*-*/
/*******************************************************************************
* Function Name : SetEPTxStatus
* Description : Set the status of Tx endpoint.
* Input : bEpNum: Endpoint Number.
* wState: new state.
* Output : None.
* Return : None.
*******************************************************************************/
void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
{
_SetEPTxStatus(bEpNum, wState);
}
/*******************************************************************************
* Function Name : SetEPRxStatus
* Description : Set the status of Rx endpoint.
* Input : bEpNum: Endpoint Number.
* wState: new state.
* Output : None.
* Return : None.
*******************************************************************************/
void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
{
_SetEPRxStatus(bEpNum, wState);
}
/*******************************************************************************
* Function Name : GetEPTxStatus
* Description : Returns the endpoint Tx status.
* Input : bEpNum: Endpoint Number.
* Output : None.
* Return : Endpoint TX Status
*******************************************************************************/
uint16_t GetEPTxStatus(uint8_t bEpNum)
{
return(_GetEPTxStatus(bEpNum));
}
/*******************************************************************************
* Function Name : GetEPRxStatus
* Description : Returns the endpoint Rx status.
* Input : bEpNum: Endpoint Number.
* Output : None.
* Return : Endpoint RX Status
*******************************************************************************/
uint16_t GetEPRxStatus(uint8_t bEpNum)
{
return(_GetEPRxStatus(bEpNum));
}
/*******************************************************************************
* Function Name : SetEPTxValid
* Description : Valid the endpoint Tx Status.
* Input : bEpNum: Endpoint Number.
* Output : None.
* Return : None.
*******************************************************************************/
void SetEPTxValid(uint8_t bEpNum)
{
_SetEPTxStatus(bEpNum, EP_TX_VALID);
}
/*******************************************************************************
* Function Name : SetEPRxValid
* Description : Valid the endpoint Rx Status.
* Input : bEpNum: Endpoint Number.
* Output : None.
* Return : None.
*******************************************************************************/
void SetEPRxValid(uint8_t bEpNum)
{
_SetEPRxStatus(bEpNum, EP_RX_VALID);
}
/*******************************************************************************
* Function Name : GetTxStallStatus
* Description : Returns the Stall status of the Tx endpoint.
* Input : bEpNum: Endpoint Number.
* Output : None.
* Return : Tx Stall status.
*******************************************************************************/
uint16_t GetTxStallStatus(uint8_t bEpNum)
{
return(_GetTxStallStatus(bEpNum));
}
/*******************************************************************************
* Function Name : GetRxStallStatus
* Description : Returns the Stall status of the Rx endpoint.
* Input : bEpNum: Endpoint Number.
* Output : None.
* Return : Rx Stall status.
*******************************************************************************/
uint16_t GetRxStallStatus(uint8_t bEpNum)
{
return(_GetRxStallStatus(bEpNum));
}
/*******************************************************************************
* Function Name : SetEPTxCount.
* Description : Set the Tx count.
* Input : bEpNum: Endpoint Number.
* wCount: new count value.
* Output : None.
* Return : None.
*******************************************************************************/
void SetEPTxCount(uint8_t bEpNum, uint16_t wCount)
{
}
/*******************************************************************************
* Function Name : SetEPRxCount
* Description : Set the Rx count.
* Input : bEpNum: Endpoint Number.
* wCount: the new count value.
* Output : None.
* Return : None.
*******************************************************************************/
void SetEPRxCount(uint8_t bEpNum, uint16_t wCount)
{
}
/*******************************************************************************
* Function Name : ToWord
* Description : merge two byte in a word.
* Input : bh: byte high, bl: bytes low.
* Output : None.
* Return : resulted word.
*******************************************************************************/
uint16_t ToWord(uint8_t bh, uint8_t bl)
{
uint16_t wRet;
wRet = (uint16_t)bl | ((uint16_t)bh << 8);
return(wRet);
}
/*******************************************************************************
* Function Name : ByteSwap
* Description : Swap two byte in a word.
* Input : wSwW: word to Swap.
* Output : None.
* Return : resulted word.
*******************************************************************************/
uint16_t ByteSwap(uint16_t wSwW)
{
uint8_t bTemp;
uint16_t wRet;
bTemp = (uint8_t)(wSwW & 0xff);
wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8);
return(wRet);
}
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

876
flight/Libraries/STM32_USB-FS-Device_Driver/src/otgd_fs_int.c
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@ -1,876 +0,0 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_int.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Description : Endpoint interrupt's service routines.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifdef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
#include "usb_type.h"
#include "otgd_fs_int.h"
#include "usb_lib.h"
#include "usb_istr.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Max size of the received OUT Non periodic packet */
#define MAX_OUT_PKT_SIZE 160
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
uint8_t USBD_Data_Buffer [MAX_OUT_PKT_SIZE];
__IO uint8_t IsocBuff [(ISOC_BUFFER_SZE * NUM_SUB_BUFFERS)];
__IO uint32_t IsocBufferIdx = 0;
extern USB_OTG_CORE_REGS core_regs;
__IO uint16_t SaveRState;
__IO uint16_t SaveTState;
/* Extern variables ----------------------------------------------------------*/
extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
/* Private function prototypes -----------------------------------------------*/
static uint32_t OTGD_FS_PCD_ReadDevInEP( USB_OTG_EP *ep);
static enum usb_device_speed OTGD_FS_PCD_GetDeviceSpeed(void);
static uint32_t OTGD_FS_PCD_WriteEmptyTxFifo(uint32_t epnum);
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : OTGD_FS_Handle_ModeMismatch_ISR
* Description : Handles the Mode Mismatch error interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_ModeMismatch_ISR(void)
{
USB_OTG_int_sts_data gintsts;
INTR_MODEMISMATCH_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.modemismatch = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_Sof_ISR
* Description : Handles the Start Of Frame detected interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_Sof_ISR(void)
{
USB_OTG_int_sts_data int_sts;
/* Call user function */
INTR_SOFINTR_Callback();
/* Clear interrupt */
int_sts.d32 = 0;
int_sts.b.sofintr = 1;
WRITE_REG32 (&core_regs.common_regs->int_sts, int_sts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_RxStatusQueueLevel_ISR
* Description : Handles the Rx Status Queue Level Interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_RxStatusQueueLevel_ISR(void)
{
USB_OTG_int_msk_data int_mask;
USB_OTG_dev_rx_sts_data status;
/* USB_OTG_int_sts_data int_sts; */
USB_OTG_EP *ep;
/* Disable the Rx Status Queue Level interrupt */
int_mask.b.rxstsqlvl = 1;
MODIFY_REG32( &core_regs.common_regs->int_msk, int_mask.d32, 0);
/* Get the Status from the top of the FIFO */
status.d32 = READ_REG32( &core_regs.common_regs->rx_stsp );
/* Get the related endpoint structure */
ep = OTGD_FS_PCD_GetOutEP(status.b.epnum);
switch (status.b.pktsts)
{
case STS_GOUT_NAK:
break;
case STS_DATA_UPDT:
if (status.b.bcnt)
{
if (ep->type == EP_TYPE_ISOC)
{
/* Call user function */
INTR_RXSTSQLVL_ISODU_Callback();
/* Copy the received buffer to the RAM */
OTGD_FS_ReadPacket((uint8_t*)(IsocBuff + (ISOC_BUFFER_SZE * IsocBufferIdx)), status.b.bcnt);
ep->xfer_buff = (uint8_t*)(IsocBuff + (ISOC_BUFFER_SZE * IsocBufferIdx));
/* Check if the end of the global buffer has been reached */
if (IsocBufferIdx == (NUM_SUB_BUFFERS - 1))
{
/* Reset the buffer index */
IsocBufferIdx = 0;
}
else
{
/* Increment the buffer index */
IsocBufferIdx ++;
}
}
else
{
/* Copy the received buffer to the RAM */
OTGD_FS_ReadPacket(USBD_Data_Buffer, status.b.bcnt);
ep->xfer_buff = USBD_Data_Buffer;
}
/* Update the endpoint structure */
ep->xfer_len = status.b.bcnt;
ep->xfer_count += status.b.bcnt;
}
break;
case STS_XFER_COMP:
break;
case STS_SETUP_COMP:
break;
case STS_SETUP_UPDT:
/* Copy the setup packet received in Fifo into the setup buffer in RAM */
OTGD_FS_ReadPacket(USBD_Data_Buffer, 8);
ep->xfer_buff = USBD_Data_Buffer;
ep->xfer_count += status.b.bcnt;
ep->xfer_len = status.b.bcnt;
break;
default:
break;
}
/* Call the user function */
INTR_RXSTSQLVL_Callback();
/* Enable the Rx Status Queue Level interrupt */
MODIFY_REG32( &core_regs.common_regs->int_msk, 0, int_mask.d32);
/* Clear interrupt: this is a read only bit, it cannot be cleared by register
access */
/* int_sts.d32 = 0;
int_sts.b.rxstsqlvl = 1;
WRITE_REG32 (&core_regs.common_regs->int_sts, int_sts.d32);
*/
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_NPTxFE_ISR
* Description : Handles the Non Periodic Tx FIFO Empty interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_NPTxFE_ISR(void )
{
/* USB_OTG_int_sts_data gintsts; */
USB_OTG_int_msk_data gintmsk;
gintmsk.d32 = 0;
/* Call the user function */
INTR_NPTXFEMPTY_Callback();
gintmsk.b.nptxfempty = 1;
MODIFY_REG32(&core_regs.common_regs->int_msk, gintmsk.d32, 0 );
/* Clear interrupt: This bit is a read only bit, cannot be cleared
by register access */
/* gintsts.d32 = 0;
gintsts.b.nptxfempty = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
*/
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_GInNakEff_ISR
* Description : Handles the Global IN Endpoints NAK Effective interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_GInNakEff_ISR(void)
{
/* USB_OTG_int_sts_data gintsts; */
/* Call user function */
INTR_GINNAKEFF_Callback();
/* Clear interrupt: This is a read only bit, it cannot be cleared by register
access */
/* gintsts.d32 = 0;
gintsts.b.ginnakeff = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
*/
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_GOutNakEff_ISR
* Description : Handles the Global OUT Endpoints NAK Effective interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_GOutNakEff_ISR(void)
{
/* USB_OTG_int_sts_data gintsts; */
/* Call user function */
INTR_GOUTNAKEFF_Callback();
/* Clear interrupt: This is a read only bit, it cannot be cleared by register
access */
/* gintsts.d32 = 0;
gintsts.b.goutnakeff = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
*/
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_EarlySuspend_ISR
* Description : Handles the Early Suspend detected interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_EarlySuspend_ISR(void )
{
USB_OTG_int_sts_data gintsts;
USB_OTG_int_msk_data gintmsk;
gintmsk.d32 = 0;
/* Call user function */
INTR_ERLYSUSPEND_Callback();
gintmsk.b.erlysuspend = 1;
MODIFY_REG32(&core_regs.common_regs->int_msk, gintmsk.d32, 0 );
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.erlysuspend = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_USBSuspend_ISR
* Description : Handles the Suspend condition detected interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_USBSuspend_ISR(void)
{
USB_OTG_int_sts_data gintsts;
/* Call user function */
INTR_USBSUSPEND_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.usbsuspend = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_UsbReset_ISR
* Description : This interrupt occurs when a USB Reset is detected.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_UsbReset_ISR(void)
{
USB_OTG_dev_all_int_data daintmsk;
USB_OTG_dev_out_ep_msk_data doepmsk;
USB_OTG_dev_in_ep_msk_data diepmsk;
USB_OTG_dev_cfg_data dcfg;
USB_OTG_dev_ctl_data dctl;
USB_OTG_int_sts_data gintsts;
daintmsk.d32 = 0;
doepmsk.d32 = 0;
diepmsk.d32 = 0;
dcfg.d32 = 0;
dctl.d32 = 0;
/* Clear the Remote Wakeup Signalling */
dctl.b.rmtwkupsig = 1;
MODIFY_REG32(&core_regs.dev_regs->dev_ctl, dctl.d32, 0 );
/* Flush the NP Tx FIFO */
OTGD_FS_FlushTxFifo( 0 );
daintmsk.b.inep0 = 1;
daintmsk.b.outep0 = 1;
WRITE_REG32( &core_regs.dev_regs->dev_all_int_msk, daintmsk.d32 );
doepmsk.b.setup = 1;
doepmsk.b.xfercompl = 1;
doepmsk.b.ahberr = 1;
doepmsk.b.epdisabled = 1;
WRITE_REG32( &core_regs.dev_regs->dev_out_ep_msk, doepmsk.d32 );
diepmsk.b.xfercompl = 1;
diepmsk.b.timeout = 1;
diepmsk.b.epdisabled = 1;
diepmsk.b.ahberr = 1;
diepmsk.b.intknepmis = 1;
WRITE_REG32( &core_regs.dev_regs->dev_in_ep_msk, diepmsk.d32 );
/* Reset Device Address */
dcfg.d32 = READ_REG32( &core_regs.dev_regs->dev_cfg);
dcfg.b.devaddr = 0;
WRITE_REG32( &core_regs.dev_regs->dev_cfg, dcfg.d32);
/* setup EP0 to receive SETUP packets */
OTGD_FS_PCD_EP0_OutStart();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.usbreset = 1;
WRITE_REG32 (&core_regs.common_regs->int_sts, gintsts.d32);
/* Call the user reset function */
OTGD_FS_DEVICE_RESET;
/* Call user function */
INTR_USBRESET_Callback();
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_EnumDone_ISR
* Description : Reads the device status register and set the device speed
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_EnumDone_ISR(void)
{
USB_OTG_int_sts_data gintsts;
USB_OTG_usb_cfg_data gusbcfg;
OTGD_FS_EP0Activate();
/* Set USB turnaround time based on device speed and PHY interface. */
gusbcfg.d32 = READ_REG32(&core_regs.common_regs->usb_cfg);
/* Full or low speed */
if ( OTGD_FS_PCD_GetDeviceSpeed() == USB_SPEED_FULL)
{
gusbcfg.b.usbtrdtim = 9;
}
WRITE_REG32(&core_regs.common_regs->usb_cfg, gusbcfg.d32);
/* Call user function */
INTR_ENUMDONE_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.enumdone = 1;
WRITE_REG32( &core_regs.common_regs->int_sts, gintsts.d32 );
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_IsoOutDrop_ISR
* Description : Handles the Isochrounous Out packet Dropped interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_IsoOutDrop_ISR(void)
{
USB_OTG_int_sts_data gintsts;
/* Call user function */
INTR_ISOOUTDROP_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.isooutdrop = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_EOPF_ISR
* Description : Handles the Expexted End Of Periodic Frame interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_EOPF_ISR(void )
{
USB_OTG_int_sts_data gintsts;
USB_OTG_int_msk_data gintmsk;
gintmsk.d32 = 0;
gintmsk.b.eopframe = 1;
MODIFY_REG32(&core_regs.common_regs->int_msk, gintmsk.d32, 0 );
/* Call user function */
INTR_EOPFRAME_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.eopframe = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_EPMismatch_ISR
* Description : Handles the Endpoint Mismatch error interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_EPMismatch_ISR(void)
{
USB_OTG_int_sts_data gintsts;
/* Call user function */
INTR_EPMISMATCH_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.epmismatch = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_InEP_ISR
* Description : Handles all IN endpoints interrupts.
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_InEP_ISR(void)
{
USB_OTG_dev_in_ep_int_data diepint;
uint32_t ep_intr;
uint32_t epnum = 0;
USB_OTG_EP *ep;
uint32_t fifoemptymsk;
diepint.d32 = 0;
ep_intr = OTGD_FS_ReadDevAllInEPItr();
while ( ep_intr )
{
if (ep_intr&0x1) /* In ITR */
{
ep = OTGD_FS_PCD_GetInEP(epnum);
diepint.d32 = OTGD_FS_PCD_ReadDevInEP(ep); /* Get In ITR status */
if ( diepint.b.xfercompl )
{
fifoemptymsk = 0x1 << ep->num;
MODIFY_REG32(&core_regs.dev_regs->dev_fifo_empty_msk, fifoemptymsk, 0);
/* Clear the Interrupt flag */
CLEAR_IN_EP_INTR(epnum, xfercompl);
if (epnum == 0)
{
/* Call the core IN process for EP0 */
In0_Process();
/* before terminate set Tx & Rx status */
OTG_DEV_SetEPRxStatus(epnum, SaveRState);
OTG_DEV_SetEPTxStatus(epnum, SaveTState);
}
else
{
OTG_DEV_SetEPTxStatus(EP1_IN, DEV_EP_TX_NAK);
(*pEpInt_IN[epnum -1])();
/* Toggle Endpoint frame ID */
if (ep->even_odd_frame == 0)
ep->even_odd_frame = 1;
else
ep->even_odd_frame = 0;
}
}
if ( diepint.b.ahberr )
{
CLEAR_IN_EP_INTR(epnum, ahberr);
}
if ( diepint.b.timeout )
{
CLEAR_IN_EP_INTR(epnum, timeout);
}
if (diepint.b.intktxfemp)
{
CLEAR_IN_EP_INTR(epnum, intktxfemp);
}
if (diepint.b.intknepmis)
{
CLEAR_IN_EP_INTR(epnum, intknepmis);
}
if (diepint.b.inepnakeff)
{
CLEAR_IN_EP_INTR(epnum, inepnakeff);
}
if (diepint.b.emptyintr)
{
if ((epnum == 0) || (OTG_DEV_GetEPTxStatus(epnum) == DEV_EP_TX_VALID))
{
OTGD_FS_PCD_WriteEmptyTxFifo(epnum);
}
CLEAR_IN_EP_INTR(epnum, emptyintr);
}
if ( diepint.b.epdisabled )
{
/* Reset Endpoint Frame ID to 0 */
ep->even_odd_frame = 0;
CLEAR_IN_EP_INTR(epnum, epdisabled);
}
}
epnum++;
ep_intr >>= 1;
}
/* Call user function */
INTR_INEPINTR_Callback();
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_OutEP_ISR
* Description : Handles all OUT endpoints interrupts.
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
uint32_t OTGD_FS_Handle_OutEP_ISR(void)
{
uint32_t ep_intr;
USB_OTG_dev_out_ep_int_data doepint;
uint32_t epnum = 0;
USB_OTG_EP *ep;
doepint.d32 = 0;
/* Read in the device interrupt bits */
ep_intr = OTGD_FS_ReadDevAllOutEp_itr();
while ( ep_intr )
{
if (ep_intr&0x1)
{
/* Get EP pointer */
ep = OTGD_FS_PCD_GetOutEP(epnum);
doepint.d32 = OTGD_FS_ReadDevOutEP_itr(ep);
/* Transfer complete */
if ( doepint.b.xfercompl )
{
/* Clear the bit in DOEPINTn for this interrupt */
CLEAR_OUT_EP_INTR(epnum, xfercompl);
if (epnum == 0)
{
/* Call the OUT process for the EP0 */
Out0_Process();
}
else
{
(*pEpInt_OUT[epnum-1])();
}
}
/* Endpoint disable */
if ( doepint.b.epdisabled )
{
/* Clear the bit in DOEPINTn for this interrupt */
CLEAR_OUT_EP_INTR(epnum, epdisabled);
}
/* AHB Error */
if ( doepint.b.ahberr )
{
CLEAR_OUT_EP_INTR(epnum, ahberr);
}
/* Setup Phase Done (control EPs) */
if ( doepint.b.setup )
{
if (epnum == 0)
{
/* Call the SETUP process for the EP0 */
Setup0_Process();
/* Before exit, update the Tx status */
OTG_DEV_SetEPTxStatus(0x80, SaveTState);
}
else
{
/* Other control endpoints */
}
/* Clear the EP Interrupt */
CLEAR_OUT_EP_INTR(epnum, setup);
}
}
epnum++;
ep_intr >>= 1;
}
/* Call user function */
INTR_OUTEPINTR_Callback();
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_IncomplIsoIn_ISR
* Description : Handles the Incomplete Isochrous IN tranfer error interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_IncomplIsoIn_ISR(void)
{
USB_OTG_int_sts_data gintsts;
/* Call user function */
INTR_INCOMPLISOIN_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.incomplisoin = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_IncomplIsoOut_ISR
* Description : Handles the Incomplete Isochrous OUT tranfer error interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_IncomplIsoOut_ISR(void)
{
USB_OTG_int_sts_data gintsts;
/* Call user function */
INTR_INCOMPLISOOUT_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.outepintr = 1;
WRITE_REG32(&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_Wakeup_ISR
* Description : Handles the Wakeup or Remote Wakeup detected interrupt.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_Wakeup_ISR(void)
{
USB_OTG_int_sts_data gintsts;
/* Call user function */
INTR_WKUPINTR_Callback();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.wkupintr = 1;
WRITE_REG32 (&core_regs.common_regs->int_sts, gintsts.d32);
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_GetDeviceSpeed
* Description : Get the device speed from the device status register
* Input : None
* Output : None
* Return : The Device speed value.
*******************************************************************************/
static enum usb_device_speed OTGD_FS_PCD_GetDeviceSpeed(void)
{
USB_OTG_dev_sts_data dsts;
enum usb_device_speed speed = USB_SPEED_UNKNOWN;
dsts.d32 = READ_REG32(&core_regs.dev_regs->dev_sts);
switch (dsts.b.enumspd)
{
case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
speed = USB_SPEED_HIGH;
break;
case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
case DSTS_ENUMSPD_FS_PHY_48MHZ:
speed = USB_SPEED_FULL;
break;
case DSTS_ENUMSPD_LS_PHY_6MHZ:
speed = USB_SPEED_LOW;
break;
}
return speed;
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_ReadDevInEP
* Description : Reads all the Endpoints flags.
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
static uint32_t OTGD_FS_PCD_ReadDevInEP( USB_OTG_EP *ep)
{
uint32_t v, msk, emp;
msk = READ_REG32(&core_regs.dev_regs->dev_in_ep_msk);
emp = READ_REG32(&core_regs.dev_regs->dev_fifo_empty_msk);
msk |= ((emp >> ep->num) & 0x1) << 7;
v = READ_REG32(&core_regs.inep_regs[ep->num]->dev_in_ep_int) & msk;
return v;
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_WriteEmptyTxFifo
* Description : Checks Fifo for the next packet to be loaded.
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
static uint32_t OTGD_FS_PCD_WriteEmptyTxFifo(uint32_t epnum)
{
USB_OTG_dev_tx_fifo_sts_data txstatus;
USB_OTG_EP *ep;
uint32_t len = 0;
uint32_t dwords;
USB_OTG_dev_ep_ctl_data depctl;
txstatus.d32 = 0;
ep = OTGD_FS_PCD_GetInEP(epnum);
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
dwords = (len + 3) / 4;
txstatus.d32 = READ_REG32( &core_regs.inep_regs[epnum]->dev_tx_fifo_sts);
/* Manage the case of 0-length data packets toggling data PID */
if ((ep->xfer_len == 0) && (ep->xfer_count == 0))
{
if (ep->num > 0)
{
depctl.d32 = READ_REG32( &core_regs.inep_regs[epnum]->dev_in_ep_ctl);
if (ep->even_odd_frame == 1)
{
depctl.b.setd0pid = 0;
depctl.b.setd1pid = 1;
}
else
{
depctl.b.setd0pid = 1;
depctl.b.setd1pid = 0;
}
WRITE_REG32( &core_regs.inep_regs[epnum]->dev_in_ep_ctl, depctl.d32);
}
}
while (txstatus.b.txfspcavail > dwords &&
ep->xfer_count < ep->xfer_len &&
ep->xfer_len != 0)
{
if (ep->num > 0)
{
depctl.d32 = READ_REG32( &core_regs.inep_regs[epnum]->dev_in_ep_ctl);
if (ep->even_odd_frame == 0)
{
depctl.b.setd0pid = 1;
depctl.b.setd1pid = 0;
}
else
{
depctl.b.setd0pid = 0;
depctl.b.setd1pid = 1;
}
WRITE_REG32( &core_regs.inep_regs[epnum]->dev_in_ep_ctl, depctl.d32);
}
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
dwords = (len + 3) / 4;
OTGD_FS_WritePacket(ep->xfer_buff, epnum, len);
ep->xfer_count += len;
txstatus.d32 = READ_REG32(&core_regs.inep_regs[epnum]->dev_tx_fifo_sts);
}
return 1;
}
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

445
flight/Libraries/STM32_USB-FS-Device_Driver/src/otgd_fs_pcd.c
View File

@ -1,445 +0,0 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : otgd_fs_pcd.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Description : Peripheral Device Interface low layer.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifdef STM32F10X_CL
#include "usb_lib.h"
#include "otgd_fs_cal.h"
#include "otgd_fs_pcd.h"
USB_OTG_PCD_DEV USB_OTG_PCD_dev;
extern USB_OTG_CORE_REGS core_regs;
/*******************************************************************************
* Function Name : OTGD_FS_PCD_Init
* Description : Initialize the USB Device portion of the driver.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void OTGD_FS_PCD_Init(void)
{
uint32_t i;
USB_OTG_EP *ep;
ep = &USB_OTG_PCD_dev.ep0;
USB_OTG_PCD_dev.ep0state = 0;
/* Init ep structure */
ep->num = 0;
ep->tx_fifo_num = 0;
/* Control until ep is actvated */
ep->type = EP_TYPE_CTRL;
ep->maxpacket = MAX_PACKET_SIZE;
ep->xfer_buff = 0;
ep->xfer_len = 0;
for (i = 1; i < MAX_TX_FIFOS ; i++)
{
ep = &USB_OTG_PCD_dev.in_ep[i-1];
/* Init ep structure */
ep->is_in = 1;
ep->num = i;
ep->tx_fifo_num = i;
/* Control until ep is actvated */
ep->type = EP_TYPE_CTRL;
ep->maxpacket = MAX_PACKET_SIZE;
ep->xfer_buff = 0;
ep->xfer_len = 0;
}
for (i = 1; i < MAX_TX_FIFOS; i++)
{
ep = &USB_OTG_PCD_dev.out_ep[i-1];
/* Init ep structure */
ep->is_in = 0;
ep->num = i;
ep->tx_fifo_num = i;
/* Control until ep is activated */
ep->type = EP_TYPE_CTRL;
ep->maxpacket = MAX_PACKET_SIZE;
ep->xfer_buff = 0;
ep->xfer_len = 0;
}
USB_OTG_PCD_dev.ep0.maxpacket = MAX_EP0_SIZE;
USB_OTG_PCD_dev.ep0.type = EP_TYPE_CTRL;
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_EP_Open
* Description : Configure an Endpoint
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_PCD_EP_Open(EP_DESCRIPTOR *epdesc)
{
USB_OTG_EP *ep;
if ((0x80 & epdesc->bEndpointAddress) != 0)
{
ep = OTGD_FS_PCD_GetInEP(epdesc->bEndpointAddress & 0x7F);
}
else
{
ep = OTGD_FS_PCD_GetOutEP(epdesc->bEndpointAddress & 0x7F);
}
ep->num = epdesc->bEndpointAddress & 0x7F;
ep->is_in = (0x80 & epdesc->bEndpointAddress) != 0;
ep->maxpacket = epdesc->wMaxPacketSize;
ep->type = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
if (ep->is_in)
{
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
}
/* Set initial data PID. */
if ((epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK )
{
ep->data_pid_start = 0;
}
OTGD_FS_EPActivate(ep );
return 0;
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_EP_Close
* Description : Called when an EP is disabled
* Input : Endpoint address.
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_PCD_EP_Close(uint8_t ep_addr)
{
USB_OTG_EP *ep;
if ((0x80 & ep_addr) != 0)
{
ep = OTGD_FS_PCD_GetInEP(ep_addr & 0x7F);
}
else
{
ep = OTGD_FS_PCD_GetOutEP(ep_addr & 0x7F);
}
ep->num = ep_addr & 0x7F;
ep->is_in = (0x80 & ep_addr) != 0;
OTGD_FS_EPDeactivate(ep );
return 0;
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_EP_Read
* Description : Read data from Fifo
* Input : Endpoint address.
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_PCD_EP_Read (uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
{
USB_OTG_EP *ep;
uint32_t i;
ep = OTGD_FS_PCD_GetOutEP(ep_addr & 0x7F);
/* copy received data into application buffer */
for (i = 0 ; i < buf_len ; i++)
{
pbuf[i] = ep->xfer_buff[i];
}
/*setup and start the Xfer */
ep->xfer_buff = pbuf;
ep->xfer_len = buf_len;
ep->xfer_count = 0;
ep->is_in = 0;
ep->num = ep_addr & 0x7F;
if ( ep->num == 0 )
{
OTGD_FS_EP0StartXfer(ep);
}
else if (USB_OTG_PCD_dev.ep0state == 0)
{
OTGD_FS_EPStartXfer( ep );
}
return 0;
}
/*******************************************************************************
* Function Name : USBF_EP_Write
* Description : Read data from Fifo
* Input : ep
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_PCD_EP_Write (uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
{
USB_OTG_EP *ep;
ep = OTGD_FS_PCD_GetInEP(ep_addr & 0x7f);
/* assign data to EP structure buffer */
ep->xfer_buff = pbuf;
/* Setup and start the Transfer */
ep->xfer_count = 0;
ep->xfer_len = buf_len;
ep->is_in = 1;
ep->num = ep_addr & 0x7F;
if ( ep->num == 0 )
{
OTGD_FS_EP0StartXfer(ep);
}
else if (USB_OTG_PCD_dev.ep0state == 0)
{
OTGD_FS_EPStartXfer( ep );
}
return 0;
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_EP_Stall
* Description : Stall an endpoint.
* Input : Endpoint Address.
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_PCD_EP_Stall (uint8_t ep_addr)
{
USB_OTG_EP *ep;
if ((0x80 & ep_addr) != 0)
{
ep = OTGD_FS_PCD_GetInEP(ep_addr & 0x7F);
}
else
{
ep = OTGD_FS_PCD_GetOutEP(ep_addr & 0x7F);
}
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80) ? 1 : 0;
OTGD_FS_EPSetStall(ep);
return (0);
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_EP_ClrStall
* Description : Clear stall condition on endpoints.
* Input : Endpoint Address.
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_PCD_EP_ClrStall (uint8_t ep_addr)
{
USB_OTG_EP *ep;
if ((0x80 & ep_addr) != 0)
{
ep = OTGD_FS_PCD_GetInEP(ep_addr & 0x7F);
}
else
{
ep = OTGD_FS_PCD_GetOutEP(ep_addr & 0x7F);
}
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80) ? 1 : 0;
OTGD_FS_EPClearStall(ep);
return (0);
}
/*******************************************************************************
* Function Name : USBF_FCD_EP_Flush()
* Description : This Function flushes the buffer.
* Input : Endpoint Address.
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_PCD_EP_Flush (uint8_t ep_addr)
{
uint8_t is_out;
uint8_t ep_nbr;
ep_nbr = ep_addr & 0x7F;
is_out = ((ep_addr & 0x80) == 0x80) ? 0 : 1;
if (is_out == 0)
{
OTGD_FS_FlushTxFifo(ep_nbr);
}
else
{
OTGD_FS_FlushRxFifo();
}
OTGD_FS_PCD_EP_ClrStall(ep_addr);
return (0);
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_EP_SetAddress
* Description : This Function set USB device address
* Input : The new device Address to be set.
* Output : None
* Return : status
*******************************************************************************/
void OTGD_FS_PCD_EP_SetAddress (uint8_t address)
{
USB_OTG_dev_cfg_data dcfg;
dcfg.d32 = 0;
dcfg.b.devaddr = address;
MODIFY_REG32( &core_regs.dev_regs->dev_cfg, 0, dcfg.d32);
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_GetInEP
* Description : This function returns pointer to IN EP struct with number ep_num
* Input : Endpoint Number.
* Output : None
* Return : status
*******************************************************************************/
USB_OTG_EP* OTGD_FS_PCD_GetInEP(uint32_t ep_num)
{
uint32_t i;
if (ep_num == 0)
{
return &USB_OTG_PCD_dev.ep0;
}
else
{
for (i = 0; i < MAX_TX_FIFOS; ++i)
{
if (USB_OTG_PCD_dev.in_ep[i].num == ep_num)
return &USB_OTG_PCD_dev.in_ep[i];
}
return 0;
}
}
/*******************************************************************************
* Function Name : USBF_GetOutEP
* Description : returns pointer to OUT EP struct with number ep_num
* Input : Endpoint Number.
* Output : None
* Return : USBF_EP
*******************************************************************************/
USB_OTG_EP* OTGD_FS_PCD_GetOutEP(uint32_t ep_num)
{
uint32_t i;
if (ep_num == 0)
{
return &USB_OTG_PCD_dev.ep0;
}
else
{
for (i = 0; i < MAX_TX_FIFOS; ++i)
{
if (USB_OTG_PCD_dev.out_ep[i].num == ep_num)
return &USB_OTG_PCD_dev.out_ep[i];
}
return 0;
}
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_DevConnect
* Description : Connect device
* Input : None
* Output : None
* Return : status
*******************************************************************************/
void OTGD_FS_PCD_DevConnect(void)
{
USB_OTG_dev_ctl_data dctl;
dctl.d32 = READ_REG32(&core_regs.dev_regs->dev_ctl);
/* Connect device */
dctl.b.sftdiscon = 0;
WRITE_REG32(&core_regs.dev_regs->dev_ctl, dctl.d32);
mDELAY(25);
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_DevDisconnect
* Description : Disconnect device
* Input : None
* Output : None
* Return : status
*******************************************************************************/
void OTGD_FS_PCD_DevDisconnect (void)
{
USB_OTG_dev_ctl_data dctl;
dctl.d32 = READ_REG32(&core_regs.dev_regs->dev_ctl);
/* Disconnect device for 20ms */
dctl.b.sftdiscon = 1;
WRITE_REG32(&core_regs.dev_regs->dev_ctl, dctl.d32);
mDELAY(25);
}
/*******************************************************************************
* Function Name : OTGD_FS_PCD_EP0_OutStart
* Description : Configures EPO to receive SETUP packets.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void OTGD_FS_PCD_EP0_OutStart(void)
{
USB_OTG_dev_ep_txfer_size0_data doeptsize0;
doeptsize0.d32 = 0;
doeptsize0.b.supcnt = 3;
doeptsize0.b.pktcnt = 1;
doeptsize0.b.xfersize = 8 * 3;
WRITE_REG32( &core_regs.outep_regs[0]->dev_out_ep_txfer_siz, doeptsize0.d32 );
}
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

119
flight/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_core.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Standard protocol processing (USB v2.0)
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -15,19 +15,19 @@
/* Includes ------------------------------------------------------------------*/
#include "usb_lib.h"
//DEVICE_INFO *pInformation;
//DEVICE Device_Table;
//DEVICE_PROP *pProperty;
//USER_STANDARD_REQUESTS *pUser_Standard_Requests;
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define ValBit(VAR,Place) (VAR & (1 << Place))
#define SetBit(VAR,Place) (VAR |= (1 << Place))
#define ClrBit(VAR,Place) (VAR &= ((1 << Place) ^ 255))
#ifdef STM32F10X_CL
#define Send0LengthData() {OTGD_FS_PCD_EP_Write (0, 0, 0) ; vSetEPTxStatus(EP_TX_VALID);}
#else
#define Send0LengthData() { _SetEPTxCount(ENDP0, 0); \
vSetEPTxStatus(EP_TX_VALID); \
}
#endif /* STM32F10X_CL */
#define vSetEPRxStatus(st) (SaveRState = st)
#define vSetEPTxStatus(st) (SaveTState = st)
@ -41,7 +41,6 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
uint16_t_uint8_t StatusInfo;
bool Data_Mul_MaxPacketSize = FALSE;
/* Private function prototypes -----------------------------------------------*/
static void DataStageOut(void);
@ -168,8 +167,8 @@ uint8_t *Standard_GetStatus(uint16_t Length)
return 0;
}
/* Reset Status Information */
StatusInfo.w = 0;
/* Reset Status Information */
if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
{
@ -181,19 +180,15 @@ uint8_t *Standard_GetStatus(uint16_t Length)
{
SetBit(StatusInfo0, 1);
}
else
{
ClrBit(StatusInfo0, 1);
}
/* Bus-powered */
if (ValBit(Feature, 6))
{
SetBit(StatusInfo0, 0);
ClrBit(StatusInfo0, 0);
}
else /* Self-powered */
{
ClrBit(StatusInfo0, 0);
SetBit(StatusInfo0, 0);
}
}
/*Interface Status*/
@ -294,9 +289,7 @@ RESULT Standard_ClearFeature(void)
/* IN endpoint */
if (_GetTxStallStatus(Related_Endpoint ))
{
#ifndef STM32F10X_CL
ClearDTOG_TX(Related_Endpoint);
#endif /* STM32F10X_CL */
SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
}
}
@ -308,14 +301,14 @@ RESULT Standard_ClearFeature(void)
if (Related_Endpoint == ENDP0)
{
/* After clear the STALL, enable the default endpoint receiver */
SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize);
// SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize);
// TK: we should reference MaxPacketSize() via pointer!
SetEPRxCount(Related_Endpoint, pProperty->MaxPacketSize);
_SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
}
else
{
#ifndef STM32F10X_CL
ClearDTOG_RX(Related_Endpoint);
#endif /* STM32F10X_CL */
_SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
}
}
@ -340,7 +333,7 @@ RESULT Standard_SetEndPointFeature(void)
uint32_t wIndex0;
uint32_t Related_Endpoint;
uint32_t rEP;
uint32_t Status;
uint32_t Status;
wIndex0 = pInformation->USBwIndex0;
rEP = wIndex0 & ~0x80;
@ -458,11 +451,7 @@ void DataStageOut(void)
pEPinfo->Usb_rLength -= Length;
pEPinfo->Usb_rOffset += Length;
#ifdef STM32F10X_CL
OTGD_FS_PCD_EP_Read(ENDP0, Buffer, Length);
#else
PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length);
#endif /* STM32F10X_CL */
}
if (pEPinfo->Usb_rLength != 0)
@ -519,14 +508,7 @@ void DataStageIn(void)
{
/* No more data to send so STALL the TX Status*/
ControlState = WAIT_STATUS_OUT;
#ifdef STM32F10X_CL
OTGD_FS_PCD_EP_Read (ENDP0, 0, 0);
#endif /* STM32F10X_CL */
#ifndef STM32F10X_CL
vSetEPTxStatus(EP_TX_STALL);
#endif /* STM32F10X_CL */
}
goto Expect_Status_Out;
@ -542,11 +524,7 @@ void DataStageIn(void)
DataBuffer = (*pEPinfo->CopyData)(Length);
#ifdef STM32F10X_CL
OTGD_FS_PCD_EP_Write (ENDP0, DataBuffer, Length);
#else
UserToPMABufferCopy(DataBuffer, GetEPTxAddr(ENDP0), Length);
#endif /* STM32F10X_CL */
SetEPTxCount(ENDP0, Length);
@ -596,10 +574,6 @@ void NoData_Setup0(void)
else
{
Result = USB_SUCCESS;
#ifdef STM32F10X_CL
SetDeviceAddress(pInformation->USBwValue0);
#endif /* STM32F10X_CL */
}
}
/*SET FEATURE for Device*/
@ -709,7 +683,6 @@ void Data_Setup0(void)
CopyRoutine = NULL;
wOffset = 0;
/*GET DESCRIPTOR*/
if (Request_No == GET_DESCRIPTOR)
{
if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
@ -837,7 +810,7 @@ void Data_Setup0(void)
/* Device ==> Host */
__IO uint32_t wLength = pInformation->USBwLength;
/* Restrict the data length to be the one host asks for */
/* Restrict the data length to be the one host asks */
if (pInformation->Ctrl_Info.Usb_wLength > wLength)
{
pInformation->Ctrl_Info.Usb_wLength = wLength;
@ -883,29 +856,17 @@ uint8_t Setup0_Process(void)
uint16_t* w;
} pBuf;
#ifdef STM32F10X_CL
USB_OTG_EP *ep;
uint16_t offset = 0;
ep = OTGD_FS_PCD_GetOutEP(ENDP0);
pBuf.b = ep->xfer_buff;
OTGD_FS_EP0StartXfer(ep);
#else
uint16_t offset = 1;
pBuf.b = PMAAddr + (uint8_t *)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
#endif /* STM32F10X_CL */
if (pInformation->ControlState != PAUSE)
{
pInformation->USBbmRequestType = *pBuf.b++; /* bmRequestType */
pInformation->USBbRequest = *pBuf.b++; /* bRequest */
pBuf.w += offset; /* word not accessed because of 32 bits addressing */
pBuf.w++; /* word not accessed because of 32 bits addressing */
pInformation->USBwValue = ByteSwap(*pBuf.w++); /* wValue */
pBuf.w += offset; /* word not accessed because of 32 bits addressing */
pBuf.w++; /* word not accessed because of 32 bits addressing */
pInformation->USBwIndex = ByteSwap(*pBuf.w++); /* wIndex */
pBuf.w += offset; /* word not accessed because of 32 bits addressing */
pBuf.w++; /* word not accessed because of 32 bits addressing */
pInformation->USBwLength = *pBuf.w; /* wLength */
}
@ -974,12 +935,7 @@ uint8_t Out0_Process(void)
{
uint32_t ControlState = pInformation->ControlState;
if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
{
/* host aborts the transfer before finish */
ControlState = STALLED;
}
else if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA))
if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA))
{
DataStageOut();
ControlState = pInformation->ControlState; /* may be changed outside the function */
@ -988,11 +944,14 @@ uint8_t Out0_Process(void)
else if (ControlState == WAIT_STATUS_OUT)
{
(*pProperty->Process_Status_OUT)();
#ifndef STM32F10X_CL
ControlState = STALLED;
#endif /* STM32F10X_CL */
}
else if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
{
/* host aborts the transfer before finish */
ControlState = STALLED;
}
/* Unexpect state, STALL the endpoint */
else
@ -1015,11 +974,9 @@ uint8_t Out0_Process(void)
*******************************************************************************/
uint8_t Post0_Process(void)
{
#ifdef STM32F10X_CL
USB_OTG_EP *ep;
#endif /* STM32F10X_CL */
SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
// SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
// TK: we should reference to MaxPacketSize() via pointer!
SetEPRxCount(ENDP0, pProperty->MaxPacketSize);
if (pInformation->ControlState == STALLED)
{
@ -1027,26 +984,6 @@ uint8_t Post0_Process(void)
vSetEPTxStatus(EP_TX_STALL);
}
#ifdef STM32F10X_CL
else if ((pInformation->ControlState == OUT_DATA) ||
(pInformation->ControlState == WAIT_STATUS_OUT))
{
ep = OTGD_FS_PCD_GetInEP(0);
ep->is_in = 0;
OTGD_FS_EP0StartXfer(ep);
vSetEPTxStatus(EP_TX_VALID);
}
else if ((pInformation->ControlState == IN_DATA) ||
(pInformation->ControlState == WAIT_STATUS_IN))
{
ep = OTGD_FS_PCD_GetInEP(0);
ep->is_in = 1;
OTGD_FS_EP0StartXfer(ep);
}
#endif /* STM32F10X_CL */
return (pInformation->ControlState == PAUSE);
}
@ -1059,9 +996,6 @@ uint8_t Post0_Process(void)
*******************************************************************************/
void SetDeviceAddress(uint8_t Val)
{
#ifdef STM32F10X_CL
OTGD_FS_PCD_EP_SetAddress ((uint8_t)Val);
#else
uint32_t i;
uint32_t nEP = Device_Table.Total_Endpoint;
@ -1071,7 +1005,6 @@ void SetDeviceAddress(uint8_t Val)
_SetEPAddress((uint8_t)i, (uint8_t)i);
} /* for */
_SetDADDR(Val | DADDR_EF); /* set device address and enable function */
#endif /* STM32F10X_CL */
}
/*******************************************************************************

4
flight/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_init.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Initialization routines & global variables
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

64
flight/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_int.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Endpoint CTR (Low and High) interrupt's service routines
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -12,7 +12,6 @@
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
#include "usb_lib.h"
@ -21,8 +20,8 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
__IO uint16_t SaveRState;
__IO uint16_t SaveTState;
uint16_t SaveRState;
uint16_t SaveTState;
/* Extern variables ----------------------------------------------------------*/
extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
@ -41,10 +40,20 @@ extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
*******************************************************************************/
void CTR_LP(void)
{
__IO uint16_t wEPVal = 0;
uint32_t wEPVal = 0;
// TK: inserted, was a global variable before which could lead to unintended overwrites
// if CTR_LP() was called from a different task
uint16_t wIstr;
// TK: same for this global variable, we have a conflict if CTR_LP() and CTR_HP()
// are called with different priorities
uint8_t EPindex;
/* stay in loop while pending ints */
while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
{
_SetISTR((uint16_t)CLR_CTR); /* clear CTR flag */
/* extract highest priority endpoint number */
EPindex = (uint8_t)(wIstr & ISTR_EP_ID);
if (EPindex == 0)
@ -55,14 +64,12 @@ void CTR_LP(void)
/* save RX & TX status */
/* and set both to NAK */
SaveRState = _GetEPRxStatus(ENDP0);
SaveTState = _GetEPTxStatus(ENDP0);
_SetEPRxStatus(ENDP0, EP_RX_NAK);
_SetEPTxStatus(ENDP0, EP_TX_NAK);
SaveRState = _GetENDPOINT(ENDP0);
SaveTState = SaveRState & EPTX_STAT;
SaveRState &= EPRX_STAT;
_SetEPRxTxStatus(ENDP0,EP_RX_NAK,EP_TX_NAK);
/* DIR bit = origin of the interrupt */
if ((wIstr & ISTR_DIR) == 0)
@ -77,9 +84,9 @@ void CTR_LP(void)
In0_Process();
/* before terminate set Tx & Rx status */
_SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
return;
_SetEPRxStatus(ENDP0, SaveRState);
_SetEPTxStatus(ENDP0, SaveTState);
return;
}
else
{
@ -89,14 +96,22 @@ void CTR_LP(void)
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
wEPVal = _GetENDPOINT(ENDP0);
if ((wEPVal &EP_SETUP) != 0)
if ((wEPVal & EP_CTR_TX) != 0)
{
_ClearEP_CTR_TX(ENDP0);
In0_Process();
/* before terminate set Tx & Rx status */
_SetEPRxStatus(ENDP0, SaveRState);
_SetEPTxStatus(ENDP0, SaveTState);
return;
}
else if ((wEPVal &EP_SETUP) != 0)
{
_ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
Setup0_Process();
/* before terminate set Tx & Rx status */
_SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
_SetEPRxStatus(ENDP0, SaveRState);
_SetEPTxStatus(ENDP0, SaveTState);
return;
}
@ -105,8 +120,8 @@ void CTR_LP(void)
_ClearEP_CTR_RX(ENDP0);
Out0_Process();
/* before terminate set Tx & Rx status */
_SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
_SetEPRxStatus(ENDP0, SaveRState);
_SetEPTxStatus(ENDP0, SaveTState);
return;
}
}
@ -153,6 +168,11 @@ void CTR_HP(void)
{
uint32_t wEPVal = 0;
// TK: made local - we have a conflict if CTR_LP() and CTR_HP()
// are called with different priorities
uint8_t EPindex;
uint16_t wIstr;
while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
{
_SetISTR((uint16_t)CLR_CTR); /* clear CTR flag */
@ -183,6 +203,4 @@ void CTR_HP(void)
}/* while(...) */
}
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

6
flight/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_mem.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Utility functions for memory transfers to/from PMA
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -12,7 +12,6 @@
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
#include "usb_lib.h"
@ -71,5 +70,4 @@ void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNByt
}
}
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

6
flight/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c
View File

@ -1,8 +1,8 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_regs.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Version : V3.0.1
* Date : 04/27/2009
* Description : Interface functions to USB cell registers
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -12,7 +12,6 @@
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef STM32F10X_CL
/* Includes ------------------------------------------------------------------*/
#include "usb_lib.h"
@ -746,5 +745,4 @@ uint16_t ByteSwap(uint16_t wSwW)
return(wRet);
}
#endif /* STM32F10X_CL */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

126
flight/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c
View File

@ -1,126 +0,0 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : usb_sil.c
* Author : MCD Application Team
* Version : V3.1.0
* Date : 10/30/2009
* Description : Simplified Interface Layer for Global Initialization and
* Endpoint Rea/Write operations.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "usb_lib.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Extern variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : USB_SIL_Init
* Description : Initialize the USB Device IP and the Endpoint 0.
* Input : None.
* Output : None.
* Return : Status.
*******************************************************************************/
uint32_t USB_SIL_Init(void)
{
#ifndef STM32F10X_CL
/* USB interrupts initialization */
/* clear pending interrupts */
_SetISTR(0);
wInterrupt_Mask = IMR_MSK;
/* set interrupts mask */
_SetCNTR(wInterrupt_Mask);
#else
/* Perform OTG Device initialization procedure (including EP0 init) */
OTG_DEV_Init();
#endif /* STM32F10X_CL */
return 0;
}
/*******************************************************************************
* Function Name : USB_SIL_Write
* Description : Write a buffer of data to a selected endpoint.
* Input : - bEpAddr: The address of the non control endpoint.
* - pBufferPointer: The pointer to the buffer of data to be written
* to the endpoint.
* - wBufferSize: Number of data to be written (in bytes).
* Output : None.
* Return : Status.
*******************************************************************************/
uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
{
#ifndef STM32F10X_CL
/* Use the memory interface function to write to the selected endpoint */
UserToPMABufferCopy(pBufferPointer, GetEPTxAddr(bEpAddr & 0x7F), wBufferSize);
/* Update the data length in the control register */
SetEPTxCount((bEpAddr & 0x7F), wBufferSize);
#else
/* Use the PCD interface layer function to write to the selected endpoint */
OTGD_FS_PCD_EP_Write (bEpAddr, pBufferPointer, wBufferSize);
#endif /* STM32F10X_CL */
return 0;
}
/*******************************************************************************
* Function Name : USB_SIL_Read
* Description : Write a buffer of data to a selected endpoint.
* Input : - bEpAddr: The address of the non control endpoint.
* - pBufferPointer: The pointer to which will be saved the
* received data buffer.
* Output : None.
* Return : Number of received data (in Bytes).
*******************************************************************************/
uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer)
{
uint32_t DataLength = 0;
#ifndef STM32F10X_CL
/* Get the number of received data on the selected Endpoint */
DataLength = GetEPRxCount(bEpAddr & 0x7F);
/* Use the memory interface function to write to the selected endpoint */
PMAToUserBufferCopy(pBufferPointer, GetEPRxAddr(bEpAddr & 0x7F), DataLength);
#else
USB_OTG_EP *ep;
/* Get the structure pointer of the selected Endpoint */
ep = OTGD_FS_PCD_GetOutEP(bEpAddr);
/* Get the number of received data */
DataLength = ep->xfer_len;
/* Use the PCD interface layer function to read the selected endpoint */
OTGD_FS_PCD_EP_Read (bEpAddr, pBufferPointer, DataLength);
#endif /* STM32F10X_CL */
/* Return the number of received data */
return DataLength;
}
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/