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New pios_overo driver that handles the SPI communications to the overo
This commit is contained in:
James Cotton
parent
bc075c5d2c
commit
92a0311b32
456
flight/PiOS/STM32F4xx/pios_overo.c
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456
flight/PiOS/STM32F4xx/pios_overo.c
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@ -0,0 +1,456 @@
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/**
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @addtogroup PIOS_OVERO OVERO Functions
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* @brief PIOS interface to read and write to overo
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* @{
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*
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* @file pios_overo.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
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* @brief Hardware Abstraction Layer for Overo communications
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* @see The GNU Public License (GPL) Version 3
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* @notes
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <pios.h>
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/**
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* Configures the SPI device to use a double buffered DMA for transferring
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* data. At the end of each transfer (NSS goes high) it makes sure to reset
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* the DMA counter to the beginning of each packet and swap to the next
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* buffer
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*/
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#if defined(PIOS_INCLUDE_SPI)
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#include <pios_overo.h>
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static bool PIOS_OVERO_validate(struct pios_overo_dev * com_dev)
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{
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/* Should check device magic here */
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return(true);
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}
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#if defined(PIOS_INCLUDE_FREERTOS)
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static struct pios_overo_dev * PIOS_OVERO_alloc(void)
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{
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return (malloc(sizeof(struct pios_overo_dev)));
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}
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#else
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#error Unsupported
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#endif
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/**
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* Initialises Overo pins
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* \param[in] mode currently only mode 0 supported
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* \return < 0 if initialisation failed
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*/
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int32_t PIOS_Overo_Init(uint32_t * overo_id, const struct pios_overo_cfg * cfg)
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{
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uint32_t init_ssel = 0;
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PIOS_Assert(overo_id);
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PIOS_Assert(cfg);
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struct pios_overo_dev * overo_dev;
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overo_dev = (struct pios_overo_dev *) PIOS_OVERO_alloc();
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if (!overo_dev) goto out_fail;
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/* Bind the configuration to the device instance */
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overo_dev->cfg = cfg;
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#if defined(PIOS_INCLUDE_FREERTOS)
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vSemaphoreCreateBinary(overo_dev->busy);
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xSemaphoreGive(overo_dev->busy);
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#endif
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/* Disable callback function */
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overo_dev->callback = NULL;
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/* Set rx/tx dummy bytes to a known value */
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overo_dev->rx_dummy_byte = 0xFF;
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overo_dev->tx_dummy_byte = 0xFF;
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/* only legal for single-slave config */
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PIOS_Assert(overo_dev->cfg->slave_count == 1);
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init_ssel = 1;
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SPI_SSOutputCmd(overo_dev->cfg->regs, (overo_dev->cfg->init.SPI_Mode == SPI_Mode_Master) ? ENABLE : DISABLE);
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/* Initialize the GPIO pins */
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/* note __builtin_ctz() due to the difference between GPIO_PinX and GPIO_PinSourceX */
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if (overo_dev->cfg->remap) {
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GPIO_PinAFConfig(overo_dev->cfg->sclk.gpio,
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__builtin_ctz(overo_dev->cfg->sclk.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->mosi.gpio,
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__builtin_ctz(overo_dev->cfg->mosi.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->miso.gpio,
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__builtin_ctz(overo_dev->cfg->miso.init.GPIO_Pin),
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overo_dev->cfg->remap);
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for (uint32_t i = 0; i < init_ssel; i++) {
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GPIO_PinAFConfig(overo_dev->cfg->ssel[i].gpio,
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__builtin_ctz(overo_dev->cfg->ssel[i].init.GPIO_Pin),
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overo_dev->cfg->remap);
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}
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}
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GPIO_Init(overo_dev->cfg->sclk.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->sclk.init));
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GPIO_Init(overo_dev->cfg->mosi.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->mosi.init));
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GPIO_Init(overo_dev->cfg->miso.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->miso.init));
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/* Configure DMA for SPI Rx */
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DMA_DeInit(overo_dev->cfg->dma.rx.channel);
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DMA_Cmd(overo_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Init(overo_dev->cfg->dma.rx.channel, (DMA_InitTypeDef*)&(overo_dev->cfg->dma.rx.init));
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/* Configure DMA for SPI Tx */
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DMA_DeInit(overo_dev->cfg->dma.tx.channel);
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DMA_Cmd(overo_dev->cfg->dma.tx.channel, DISABLE);
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DMA_Init(overo_dev->cfg->dma.tx.channel, (DMA_InitTypeDef*)&(overo_dev->cfg->dma.tx.init));
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/* Initialize the SPI block */
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SPI_DeInit(overo_dev->cfg->regs);
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SPI_Init(overo_dev->cfg->regs, (SPI_InitTypeDef*)&(overo_dev->cfg->init));
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/* Configure CRC calculation */
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if (overo_dev->cfg->use_crc) {
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SPI_CalculateCRC(overo_dev->cfg->regs, ENABLE);
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} else {
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SPI_CalculateCRC(overo_dev->cfg->regs, DISABLE);
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}
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/* Enable SPI */
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SPI_Cmd(overo_dev->cfg->regs, ENABLE);
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(overo_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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/* Must store this before enabling interrupt */
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*spi_id = (uint32_t)overo_dev;
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/* Configure DMA interrupt */
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NVIC_Init((NVIC_InitTypeDef*)&(overo_dev->cfg->dma.irq.init));
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return(0);
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out_fail:
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return(-1);
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}
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/**
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* Claim the SPI bus semaphore. Calling the SPI functions does not require this
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* \param[in] spi SPI number (0 or 1)
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* \return 0 if no error
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* \return -1 if timeout before claiming semaphore
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*/
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int32_t PIOS_OVERO_ClaimBus(uint32_t spi_id)
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{
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#if defined(PIOS_INCLUDE_FREERTOS)
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid)
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if (xSemaphoreTake(overo_dev->busy, 0xffff) != pdTRUE)
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return -1;
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#endif
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return 0;
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}
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/**
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* Claim the SPI bus semaphore from an ISR. Has no timeout.
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* \param[in] spi SPI number (0 or 1)
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* \return 0 if no error
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* \return -1 if timeout before claiming semaphore
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*/
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int32_t PIOS_OVERO_ClaimBusISR(uint32_t overo_io)
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{
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#if defined(PIOS_INCLUDE_FREERTOS)
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struct pios_overo_dev * overo_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid)
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if (xQueueGenericReceive(( xQueueHandle ) overo_dev->busy, NULL, 0x0000 , pdFALSE ) != pdTRUE)
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return -1;
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#endif
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return 0;
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}
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/**
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* Release the SPI bus semaphore. Calling the SPI functions does not require this
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* \param[in] spi SPI number (0 or 1)
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* \return 0 if no error
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*/
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int32_t PIOS_OVERO_ReleaseBus(uint32_t overo_id)
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{
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#if defined(PIOS_INCLUDE_FREERTOS)
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid)
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xSemaphoreGive(overo_dev->busy);
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#endif
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return 0;
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}
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/**
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* Transfers a block of bytes via DMA.
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* \param[in] spi SPI number (0 or 1)
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* \param[in] send_buffer pointer to buffer which should be sent.<BR>
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* If NULL, 0xff (all-one) will be sent.
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* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
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* If NULL, received bytes will be discarded.
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* \param[in] len number of bytes which should be transfered
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* \param[in] callback pointer to callback function which will be executed
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* from DMA channel interrupt once the transfer is finished.
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* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
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* block until the transfer is finished.
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* \return >= 0 if no error during transfer
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* \return -1 if disabled SPI port selected
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* \return -3 if function has been called during an ongoing DMA transfer
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*/
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static int32_t SPI_DMA_TransferBlock(uint32_t spi_id, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
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{
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struct pios_overo_dev * overo_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(overo_dev);
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PIOS_Assert(valid)
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DMA_InitTypeDef dma_init;
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/* Exit if ongoing transfer */
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if (DMA_GetCurrDataCounter(overo_dev->cfg->dma.rx.channel)) {
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return -3;
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}
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/* Disable the DMA channels */
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DMA_Cmd(overo_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Cmd(overo_dev->cfg->dma.tx.channel, DISABLE);
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while(DMA_GetCmdStatus(overo_dev->cfg->dma.rx.channel) == ENABLE);
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while(DMA_GetCmdStatus(overo_dev->cfg->dma.tx.channel) == ENABLE);
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/* Disable the SPI peripheral */
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/* Initialize the SPI block */
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SPI_DeInit(overo_dev->cfg->regs);
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SPI_Init(overo_dev->cfg->regs, (SPI_InitTypeDef*)&(overo_dev->cfg->init));
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SPI_Cmd(overo_dev->cfg->regs, DISABLE);
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/* Configure CRC calculation */
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if (overo_dev->cfg->use_crc) {
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SPI_CalculateCRC(overo_dev->cfg->regs, ENABLE);
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} else {
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SPI_CalculateCRC(overo_dev->cfg->regs, DISABLE);
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}
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(overo_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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/* Set callback function */
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overo_dev->callback = callback;
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/*
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* Configure Rx channel
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*/
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/* Start with the default configuration for this peripheral */
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dma_init = overo_dev->cfg->dma.rx.init;
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DMA_DeInit(overo_dev->cfg->dma.rx.channel);
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if (receive_buffer != NULL) {
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/* Enable memory addr. increment - bytes written into receive buffer */
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dma_init.DMA_Memory0BaseAddr = (uint32_t) receive_buffer;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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/* Disable memory addr. increment - bytes written into dummy buffer */
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overo_dev->rx_dummy_byte = 0xFF;
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dma_init.DMA_Memory0BaseAddr = (uint32_t) &overo_dev->rx_dummy_byte;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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if (overo_dev->cfg->use_crc) {
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/* Make sure the CRC error flag is cleared before we start */
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SPI_I2S_ClearFlag(overo_dev->cfg->regs, SPI_FLAG_CRCERR);
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}
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dma_init.DMA_BufferSize = len;
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DMA_Init(overo_dev->cfg->dma.rx.channel, &(dma_init));
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/*
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* Configure Tx channel
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*/
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/* Start with the default configuration for this peripheral */
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dma_init = overo_dev->cfg->dma.tx.init;
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DMA_DeInit(overo_dev->cfg->dma.tx.channel);
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if (send_buffer != NULL) {
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/* Enable memory addr. increment - bytes written into receive buffer */
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dma_init.DMA_Memory0BaseAddr = (uint32_t) send_buffer;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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/* Disable memory addr. increment - bytes written into dummy buffer */
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overo_dev->tx_dummy_byte = 0xFF;
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dma_init.DMA_Memory0BaseAddr = (uint32_t) &overo_dev->tx_dummy_byte;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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if (overo_dev->cfg->use_crc) {
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/* The last byte of the payload will be replaced with the CRC8 */
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dma_init.DMA_BufferSize = len - 1;
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} else {
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dma_init.DMA_BufferSize = len;
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}
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DMA_Init(overo_dev->cfg->dma.tx.channel, &(dma_init));
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/* Enable DMA interrupt if callback function active */
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DMA_ITConfig(overo_dev->cfg->dma.rx.channel, DMA_IT_TC, (callback != NULL) ? ENABLE : DISABLE);
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/* Flush out the CRC registers */
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SPI_CalculateCRC(overo_dev->cfg->regs, DISABLE);
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(void)SPI_GetCRC(overo_dev->cfg->regs, SPI_CRC_Rx);
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SPI_I2S_ClearFlag(overo_dev->cfg->regs, SPI_FLAG_CRCERR);
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/* Make sure to flush out the receive buffer */
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(void)SPI_I2S_ReceiveData(overo_dev->cfg->regs);
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if (overo_dev->cfg->use_crc) {
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/* Need a 0->1 transition to reset the CRC logic */
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SPI_CalculateCRC(overo_dev->cfg->regs, ENABLE);
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}
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/* Start DMA transfers */
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DMA_Cmd(overo_dev->cfg->dma.rx.channel, ENABLE);
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DMA_Cmd(overo_dev->cfg->dma.tx.channel, ENABLE);
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/* Reenable the SPI device */
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SPI_Cmd(overo_dev->cfg->regs, ENABLE);
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if (callback) {
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/* User has requested a callback, don't wait for the transfer to complete. */
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return 0;
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}
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/* Wait until all bytes have been transmitted/received */
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while (DMA_GetCurrDataCounter(overo_dev->cfg->dma.rx.channel));
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/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
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while (!(SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_I2S_FLAG_TXE)));
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/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
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while (SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_I2S_FLAG_BSY));
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/* Check the CRC on the transfer if enabled. */
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if (overo_dev->cfg->use_crc) {
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/* Check the SPI CRC error flag */
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if (SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_FLAG_CRCERR)) {
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return -4;
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}
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}
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/* No error */
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return 0;
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}
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/**
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* Transfers a block of bytes via PIO or DMA.
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* \param[in] spi_id SPI device handle
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* \param[in] send_buffer pointer to buffer which should be sent.<BR>
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* If NULL, 0xff (all-one) will be sent.
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* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
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* If NULL, received bytes will be discarded.
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* \param[in] len number of bytes which should be transfered
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* \param[in] callback pointer to callback function which will be executed
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* from DMA channel interrupt once the transfer is finished.
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* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
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* block until the transfer is finished.
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* \return >= 0 if no error during transfer
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* \return -1 if disabled SPI port selected
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* \return -3 if function has been called during an ongoing DMA transfer
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*/
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int32_t PIOS_SPI_TransferBlock(uint32_t spi_id, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
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{
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return SPI_PIO_TransferBlock(spi_id, send_buffer, receive_buffer, len);
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}
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/**
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* Check if a transfer is in progress
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* \param[in] spi SPI number (0 or 1)
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* \return >= 0 if no transfer is in progress
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* \return -1 if disabled SPI port selected
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* \return -2 if unsupported SPI port selected
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* \return -3 if function has been called during an ongoing DMA transfer
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*/
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int32_t PIOS_OVERO_Busy(uint32_t overo_id)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid)
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/* DMA buffer has data or SPI transmit register not empty or SPI is busy*/
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if (DMA_GetCurrDataCounter(overo_dev->cfg->dma.rx.channel) ||
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!SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_I2S_FLAG_TXE) ||
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SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_I2S_FLAG_BSY))
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{
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return -3;
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}
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return(0);
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}
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void PIOS_OVERO_IRQ_Handler(uint32_t spi_id)
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{
|
||||
struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
|
||||
|
||||
bool valid = PIOS_OVERO_validate(overo_dev);
|
||||
PIOS_Assert(valid)
|
||||
|
||||
// FIXME XXX Only RX channel or better clear flags for both channels?
|
||||
DMA_ClearFlag(overo_dev->cfg->dma.rx.channel, overo_dev->cfg->dma.irq.flags);
|
||||
|
||||
if(overo_dev->cfg->init.SPI_Mode == SPI_Mode_Master) {
|
||||
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
||||
while (!(SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
|
||||
|
||||
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
||||
while (SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
|
||||
}
|
||||
|
||||
if (overo_dev->callback != NULL) {
|
||||
bool crc_ok = true;
|
||||
uint8_t crc_val;
|
||||
|
||||
if (SPI_I2S_GetFlagStatus(overo_dev->cfg->regs, SPI_FLAG_CRCERR)) {
|
||||
crc_ok = false;
|
||||
SPI_I2S_ClearFlag(overo_dev->cfg->regs, SPI_FLAG_CRCERR);
|
||||
}
|
||||
crc_val = SPI_GetCRC(overo_dev->cfg->regs, SPI_CRC_Rx);
|
||||
overo_dev->callback(crc_ok, crc_val);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
* @}
|
||||
*/
|
||||
69
flight/PiOS/inc/pios_overo.h
Normal file
69
flight/PiOS/inc/pios_overo.h
Normal file
@ -0,0 +1,69 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @addtogroup PIOS PIOS Core hardware abstraction layer
|
||||
* @{
|
||||
* @addtogroup PIOS_OVERO Overo Functions
|
||||
* @{
|
||||
*
|
||||
* @file pios_overo.h
|
||||
* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
|
||||
* @brief Overo functions header.
|
||||
* @see The GNU Public License (GPL) Version 3
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef PIOS_OVERO_H
|
||||
#define PIOS_OVERO_H
|
||||
|
||||
#include <pios.h>
|
||||
#include <pios_stm32.h>
|
||||
|
||||
struct pios_overo_cfg {
|
||||
SPI_TypeDef *regs;
|
||||
uint32_t remap; /* GPIO_Remap_* or GPIO_AF_* */
|
||||
SPI_InitTypeDef init;
|
||||
bool use_crc;
|
||||
struct stm32_dma dma;
|
||||
struct stm32_gpio sclk;
|
||||
struct stm32_gpio miso;
|
||||
struct stm32_gpio mosi;
|
||||
uint32_t slave_count;
|
||||
struct stm32_gpio ssel[];
|
||||
};
|
||||
|
||||
struct pios_overo_dev {
|
||||
const struct pios_overo_cfg * cfg;
|
||||
void (*callback) (uint8_t, uint8_t);
|
||||
uint8_t tx_dummy_byte;
|
||||
uint8_t rx_dummy_byte;
|
||||
#if defined(PIOS_INCLUDE_FREERTOS)
|
||||
xSemaphoreHandle busy;
|
||||
#else
|
||||
uint8_t busy;
|
||||
#endif
|
||||
};
|
||||
|
||||
extern int32_t PIOS_OVERO_Init(uint32_t * overo_id, const struct pios_overo_cfg * cfg);
|
||||
extern int32_t PIOS_OVERO_SwapBuffer(uint32_t overo_id, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback);
|
||||
|
||||
#endif /* PIOS_OVERO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
* @}
|
||||
*/
|
||||
Loading…
x
Reference in New Issue
Block a user