From a0a92d5a59061487594a4363904c89eaafa2b677 Mon Sep 17 00:00:00 2001 From: gussy Date: Sat, 13 Mar 2010 20:01:31 +0000 Subject: [PATCH] OP-21: Made changes to OpenPilot makefile too allow building for bootloader and non-bootloader targets. Use "USE_BOOTLOADER = YES" to build for the OpenPilot Bootloader. git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@300 ebee16cc-31ac-478f-84a7-5cbb03baadba --- flight/OpenPilot/Makefile | 14 +- flight/OpenPilot/System/inc/pios_board.h | 8 +- flight/PiOS/STM32F10x/link_stm32f10x_HD_BL.ld | 2 +- flight/PiOS/STM32F10x/link_stm32f10x_HD_NB.ld | 411 +++++++++++++++ flight/PiOS/STM32F10x/pios_sys.c | 2 +- flight/PiOS/STM32F10x/startup_stm32f10x_HD.S | 6 +- .../PiOS/STM32F10x/startup_stm32f10x_HD_BL.S | 6 +- .../PiOS/STM32F10x/startup_stm32f10x_HD_NB.S | 483 ++++++++++++++++++ 8 files changed, 920 insertions(+), 12 deletions(-) create mode 100644 flight/PiOS/STM32F10x/link_stm32f10x_HD_NB.ld create mode 100644 flight/PiOS/STM32F10x/startup_stm32f10x_HD_NB.S diff --git a/flight/OpenPilot/Makefile b/flight/OpenPilot/Makefile index 8c18a2ad1..4aa41656d 100644 --- a/flight/OpenPilot/Makefile +++ b/flight/OpenPilot/Makefile @@ -27,6 +27,7 @@ # Set to YES for debugging DEBUG = YES ENABLE_DEBUG_PINS = NO +USE_BOOTLOADER = NO # Set to YES when using Code Sourcery toolchain CODE_SOURCERY = YES @@ -52,8 +53,13 @@ USE_THUMB_MODE = YES # - BOARD just passed as define (optional) MCU = cortex-m3 CHIP = STM32F103RET -MODEL = HD BOARD = STM3210E_OP +ifeq ($(USE_BOOTLOADER), YES) +MODEL = HD_BL + +else +MODEL = HD_NB +endif # Directory for output files (lst, obj, dep, elf, sym, map, hex, bin etc.) OUTDIR = Build @@ -283,10 +289,12 @@ DEBUGF = dwarf-2 CDEFS = -DSTM32F10X_$(MODEL) CDEFS += -DUSE_STDPERIPH_DRIVER CDEFS += -DUSE_$(BOARD) - -ifeq ($(ENABLE_DEBUG_PINS),YES) +ifeq ($(ENABLE_DEBUG_PINS), YES) CDEFS += -DPIOS_ENABLE_DEBUG_PINS endif +ifeq ($(USE_BOOTLOADER), YES) +CDEFS += -DUSE_BOOTLOADER +endif # Place project-specific -D and/or -U options for diff --git a/flight/OpenPilot/System/inc/pios_board.h b/flight/OpenPilot/System/inc/pios_board.h index 48d5b0afb..115586bfb 100644 --- a/flight/OpenPilot/System/inc/pios_board.h +++ b/flight/OpenPilot/System/inc/pios_board.h @@ -28,6 +28,7 @@ #define PIOS_BOARD_H + //------------------------ // Timers and Channels Used //------------------------ @@ -200,10 +201,15 @@ TIM8 | Servo 5 | Servo 6 | Servo 7 | Servo 8 #define PIOS_DELAY_TIMER_RCC_FUNC RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) //------------------------- -// Master Clock +// System Settings //------------------------- #define PIOS_MASTER_CLOCK 72000000 #define PIOS_PERIPHERAL_CLOCK (PIOS_MASTER_CLOCK / 2) +#if defined(USE_BOOTLOADER) +#define PIOS_NVIC_VECTTAB_FLASH ((uint32_t)0x08008000) +#else +#define PIOS_NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) +#endif //------------------------- // Interrupt Priorities diff --git a/flight/PiOS/STM32F10x/link_stm32f10x_HD_BL.ld b/flight/PiOS/STM32F10x/link_stm32f10x_HD_BL.ld index 6b6ba6ef0..1dd023228 100644 --- a/flight/PiOS/STM32F10x/link_stm32f10x_HD_BL.ld +++ b/flight/PiOS/STM32F10x/link_stm32f10x_HD_BL.ld @@ -28,7 +28,7 @@ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 480K FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 diff --git a/flight/PiOS/STM32F10x/link_stm32f10x_HD_NB.ld b/flight/PiOS/STM32F10x/link_stm32f10x_HD_NB.ld new file mode 100644 index 000000000..6b6ba6ef0 --- /dev/null +++ b/flight/PiOS/STM32F10x/link_stm32f10x_HD_NB.ld @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * + * @file link_stm32f10x_HD.ld + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2009. + * @brief PiOS linker for the OpenPilot board + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* Memory Spaces Definitions */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 +} + +/* higher address of the user mode stack */ +_estack = 0x20010000; + +/* default stack sizes. + +These are used by the startup in order to allocate stacks for the different modes. + +Note: FreeRTOS gives each task an own stack +*/ + +__Stack_Size = 128 ; + +PROVIDE ( _Stack_Size = __Stack_Size ) ; + +__Stack_Init = _estack - __Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ +PROVIDE ( _Stack_Init = __Stack_Init ) ; + +/* +There will be a link error if there is not this amount of RAM free at the end. +*/ +_Minimum_Stack_Size = 0x100 ; + +/* Check valid alignment for VTOR */ +ASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), "Start of memory region flash not aligned for startup vector table"); + + +/* +this sends all unreferenced IRQHandlers to reset +*/ + + +PROVIDE ( Undefined_Handler = 0 ) ; +PROVIDE ( SWI_Handler = 0 ) ; +PROVIDE ( IRQ_Handler = 0 ) ; +PROVIDE ( Prefetch_Handler = 0 ) ; +PROVIDE ( Abort_Handler = 0 ) ; +PROVIDE ( FIQ_Handler = 0 ) ; + +PROVIDE ( NMI_Handler = 0 ) ; +PROVIDE ( HardFault_Handler = 0 ) ; +PROVIDE ( MemManage_Handler = 0 ) ; +PROVIDE ( BusFault_Handler = 0 ) ; +PROVIDE ( UsageFault_Handler = 0 ) ; +PROVIDE ( SVC_Handler = 0 ) ; +PROVIDE ( DebugMon_Handler = 0 ) ; +PROVIDE ( PendSV_Handler = 0 ) ; +PROVIDE ( SysTick_Handler = 0 ) ; + +PROVIDE ( WWDG_IRQHandler = 0 ) ; +PROVIDE ( PVD_IRQHandler = 0 ) ; +PROVIDE ( TAMPER_IRQHandler = 0 ) ; +PROVIDE ( RTC_IRQHandler = 0 ) ; +PROVIDE ( FLASH_IRQHandler = 0 ) ; +PROVIDE ( RCC_IRQHandler = 0 ) ; +PROVIDE ( EXTI0_IRQHandler = 0 ) ; +PROVIDE ( EXTI1_IRQHandler = 0 ) ; +PROVIDE ( EXTI2_IRQHandler = 0 ) ; +PROVIDE ( EXTI3_IRQHandler = 0 ) ; +PROVIDE ( EXTI4_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel1_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel2_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel3_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel4_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel5_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel6_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel7_IRQHandler = 0 ) ; +PROVIDE ( ADC_IRQHandler = 0 ) ; +PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ; +PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ; +PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ; +PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ; +PROVIDE ( EXTI9_5_IRQHandler = 0 ) ; +PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ; +PROVIDE ( TIM1_UP_IRQHandler = 0 ) ; +PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ; +PROVIDE ( TIM1_CC_IRQHandler = 0 ) ; +PROVIDE ( TIM2_IRQHandler = 0 ) ; +PROVIDE ( TIM3_IRQHandler = 0 ) ; +PROVIDE ( TIM4_IRQHandler = 0 ) ; +PROVIDE ( I2C1_EV_IRQHandler = 0 ) ; +PROVIDE ( I2C1_ER_IRQHandler = 0 ) ; +PROVIDE ( I2C2_EV_IRQHandler = 0 ) ; +PROVIDE ( I2C2_ER_IRQHandler = 0 ) ; +PROVIDE ( SPI1_IRQHandler = 0 ) ; +PROVIDE ( SPI2_IRQHandler = 0 ) ; +PROVIDE ( USART1_IRQHandler = 0 ) ; +PROVIDE ( USART2_IRQHandler = 0 ) ; +PROVIDE ( USART3_IRQHandler = 0 ) ; +PROVIDE ( EXTI15_10_IRQHandler = 0 ) ; +PROVIDE ( RTCAlarm_IRQHandler = 0 ) ; +PROVIDE ( USBWakeUp_IRQHandler = 0 ) ; +PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ; +PROVIDE ( TIM8_UP_IRQHandler = 0 ) ; +PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ; +PROVIDE ( TIM8_CC_IRQHandler = 0 ) ; +PROVIDE ( ADC3_IRQHandler = 0 ) ; +PROVIDE ( FSMC_IRQHandler = 0 ) ; +PROVIDE ( SDIO_IRQHandler = 0 ) ; +PROVIDE ( TIM5_IRQHandler = 0 ) ; +PROVIDE ( SPI3_IRQHandler = 0 ) ; +PROVIDE ( UART4_IRQHandler = 0 ) ; +PROVIDE ( UART5_IRQHandler = 0 ) ; +PROVIDE ( TIM6_IRQHandler = 0 ) ; +PROVIDE ( TIM7_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ; + + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/*this allows to compile the ST lib in "non-debug" mode*/ + + +/* Peripheral and SRAM base address in the alias region */ +PERIPH_BB_BASE = 0x42000000; +SRAM_BB_BASE = 0x22000000; + +/* Peripheral and SRAM base address in the bit-band region */ +SRAM_BASE = 0x20000000; +PERIPH_BASE = 0x40000000; + +/* Flash registers base address */ +PROVIDE ( FLASH_BASE = 0x40022000); +/* Flash Option Bytes base address */ +PROVIDE ( OB_BASE = 0x1FFFF800); + +/* Peripheral memory map */ +APB1PERIPH_BASE = PERIPH_BASE ; +APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ; +AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ; + +PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ; +PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ; +PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ; +PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ; +PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ; +PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ; +PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ; +PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ; +PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ; +PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ; +PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ; +PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ; +PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ; +PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ; + +PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ; +PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ; +PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ; +PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ; +PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ; +PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ; +PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ; +PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ; +PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ; +PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ; +PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ; +PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ; + +PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ; +PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ; +PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ; +PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ; +PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ; +PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ; +PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ; +PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ; +PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ; + +/* System Control Space memory map */ +SCS_BASE = 0xE000E000; + +PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ; +PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ; +PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ; + + +/* Sections Definitions */ + +SECTIONS +{ + + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ + .flashtext : + { + . = ALIGN(4); + *(.flashtext) /* Startup code */ + . = ALIGN(4); + } >FLASH + + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >FLASH + + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM + + + + /* this is the FLASH Bank1 */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + .b1text : + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata*) + } >FLASHB1 + + /* this is the EXTMEM */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + + /* EXTMEM Bank0 */ + .eb0text : + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata*) + } >EXTMEMB3 + + __exidx_start = .; + __exidx_end = .; + + /* after that it's only debugging information. */ + + /* remove the debugging information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + + diff --git a/flight/PiOS/STM32F10x/pios_sys.c b/flight/PiOS/STM32F10x/pios_sys.c index e59441b14..9567a8a65 100644 --- a/flight/PiOS/STM32F10x/pios_sys.c +++ b/flight/PiOS/STM32F10x/pios_sys.c @@ -110,7 +110,7 @@ int32_t PIOS_SYS_SerialNumberGet(char *str) void NVIC_Configuration(void) { /* Set the Vector Table base address as specified in .ld file */ - NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); + NVIC_SetVectorTable(PIOS_NVIC_VECTTAB_FLASH, 0x0); /* 4 bits for Interrupt priorities so no sub priorities */ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); diff --git a/flight/PiOS/STM32F10x/startup_stm32f10x_HD.S b/flight/PiOS/STM32F10x/startup_stm32f10x_HD.S index 34caf921b..a512f98a7 100644 --- a/flight/PiOS/STM32F10x/startup_stm32f10x_HD.S +++ b/flight/PiOS/STM32F10x/startup_stm32f10x_HD.S @@ -151,11 +151,11 @@ g_pfnVectors: .word 0 .word 0 .word 0 - .word vPortSVCHandler + .word SVC_Handler .word DebugMon_Handler .word 0 - .word xPortPendSVHandler - .word xPortSysTickHandler + .word PendSV_Handler + .word SysTick_Handler .word WWDG_IRQHandler .word PVD_IRQHandler .word TAMPER_IRQHandler diff --git a/flight/PiOS/STM32F10x/startup_stm32f10x_HD_BL.S b/flight/PiOS/STM32F10x/startup_stm32f10x_HD_BL.S index a512f98a7..34caf921b 100644 --- a/flight/PiOS/STM32F10x/startup_stm32f10x_HD_BL.S +++ b/flight/PiOS/STM32F10x/startup_stm32f10x_HD_BL.S @@ -151,11 +151,11 @@ g_pfnVectors: .word 0 .word 0 .word 0 - .word SVC_Handler + .word vPortSVCHandler .word DebugMon_Handler .word 0 - .word PendSV_Handler - .word SysTick_Handler + .word xPortPendSVHandler + .word xPortSysTickHandler .word WWDG_IRQHandler .word PVD_IRQHandler .word TAMPER_IRQHandler diff --git a/flight/PiOS/STM32F10x/startup_stm32f10x_HD_NB.S b/flight/PiOS/STM32F10x/startup_stm32f10x_HD_NB.S new file mode 100644 index 000000000..34caf921b --- /dev/null +++ b/flight/PiOS/STM32F10x/startup_stm32f10x_HD_NB.S @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team / David Ankers: Vector table for FreeRTOS + * @version V3.1.2 + * @date 09/28/2009 + * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure external SRAM mounted on STM3210E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global SystemInit_ExtMemCtl_Dummy +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +.equ Initial_spTop, 0x20000400 +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + bl SystemInit_ExtMemCtl +/* restore original stack pointer */ + LDR r0, =_estack + MSR msp, r0 +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief Dummy SystemInit_ExtMemCtl function + * @param None + * @retval : None +*/ + .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits +SystemInit_ExtMemCtl_Dummy: + bx lr + .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word Initial_spTop + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word vPortSVCHandler + .word DebugMon_Handler + .word 0 + .word xPortPendSVHandler + .word xPortSysTickHandler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak SystemInit_ExtMemCtl + .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy +