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https://bitbucket.org/librepilot/librepilot.git
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OP-378 Update the INS Makefile for the new file formats
This commit is contained in:
James Cotton
parent
b7f25ea5d8
commit
ab3127a0ea
@ -29,7 +29,6 @@ include $(TOP)/make/firmware-defs.mk
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# Set developer code and compile options
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# Set to YES for debugging
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DEBUG ?= YES
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USE_BOOTLOADER ?= NO
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# Set to YES when using Code Sourcery toolchain
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CODE_SOURCERY ?= YES
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@ -50,11 +49,6 @@ MCU = cortex-m3
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CHIP = STM32F103RET
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BOARD = STM3210E_INS
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MODEL = HD
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ifeq ($(USE_BOOTLOADER), YES)
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BOOT_MODEL = $(MODEL)_BL
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else
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BOOT_MODEL = $(MODEL)_NB
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endif
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# Directory for output files (lst, obj, dep, elf, sym, map, hex, bin etc.)
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OUTDIR = $(TOP)/build/ins
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@ -124,6 +118,7 @@ SRC += $(PIOSCOMMON)/pios_bma180.c
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SRC += $(PIOSCOMMON)/pios_hmc5883.c
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SRC += $(PIOSCOMMON)/pios_bmp085.c
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SRC += $(PIOSCOMMON)/pios_imu3000.c
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SRC += $(PIOSCOMMON)/pios_bl_helper.c
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## CMSIS for STM32
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SRC += $(CMSISDIR)/core_cm3.c
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@ -231,9 +226,8 @@ CDEFS = -DSTM32F10X_$(MODEL)
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CDEFS += -DUSE_STDPERIPH_DRIVER
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CDEFS += -DUSE_$(BOARD)
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CDEFS += -DIN_AHRS
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ifeq ($(USE_BOOTLOADER), YES)
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CDEFS += -DUSE_BOOTLOADER
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endif
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# Place project-specific -D and/or -U options for
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# Assembler with preprocessor here.
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#ADEFS = -DUSE_IRQ_ASM_WRAPPER
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@ -260,12 +254,7 @@ CSTANDARD = -std=gnu99
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# Flags for C and C++ (arm-elf-gcc/arm-elf-g++)
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ifeq ($(DEBUG),YES)
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CFLAGS += -g$(DEBUGF) #-DDEBUG
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else
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CFLAGS += -g$(DEBUGF)
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endif
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CFLAGS += -ffast-math
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@ -311,13 +300,14 @@ LDFLAGS += $(MATH_LIB)
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LDFLAGS += -lc -lgcc
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# Set linker-script name depending on selected submodel name
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LDFLAGS +=-T$(LINKERSCRIPTPATH)/link_$(BOARD)_$(BOOT_MODEL).ld
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LDFLAGS += -T$(LINKERSCRIPTPATH)/link_$(BOARD)_memory.ld
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LDFLAGS += -T$(LINKERSCRIPTPATH)/link_$(BOARD)_sections.ld
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OOCD_LOADFILE+=$(OUTDIR)/$(TARGET).elf
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OOCD_LOADFILE+=$(OUTDIR)/$(TARGET).bin
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# Program
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OOCD_CL+=-c "flash write_image $(OOCD_LOADFILE)"
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OOCD_CL+=-c "flash write_image erase $(OOCD_LOADFILE) 0x08002000 bin"
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# Verify
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OOCD_CL+=-c "verify_image $(OOCD_LOADFILE)"
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OOCD_CL+=-c "verify_image $(OOCD_LOADFILE) 0x08002000 bin"
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# reset target
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OOCD_CL+=-c "reset run"
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# # terminate OOCD after programming
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@ -359,19 +349,12 @@ endif
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endif
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# Program the device.
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ifeq ($(USE_BOOTLOADER), YES)
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# Program the device with OP Upload Tool".
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program: $(OUTDIR)/$(TARGET).bin
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@echo ${quote}Programming with OP Upload Tool${quote}
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../../ground/src/experimental/upload-build-desktop/debug/OPUploadTool -d 1 -p $(OUTDIR)/$(TARGET).bin
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else
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ifeq ($(FLASH_TOOL),OPENOCD)
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# Program the device with Dominic Rath's OPENOCD in "batch-mode", needs cfg and "reset-script".
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program: $(OUTDIR)/$(TARGET).elf
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program: $(OUTDIR)/$(TARGET).bin
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@echo ${quote}Programming with OPENOCD${quote}
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$(OOCD_EXE) $(OOCD_CL)
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endif
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endif
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# Link: create ELF output file from object files.
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$(eval $(call LINK_TEMPLATE, $(OUTDIR)/$(TARGET).elf, $(ALLOBJ)))
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@ -400,7 +383,9 @@ $(eval $(call PARTIAL_COMPILE_TEMPLATE, SRC))
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# Compile: create assembler files from C source files. ARM only
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$(eval $(call PARTIAL_COMPILE_ARM_TEMPLATE, SRCARM))
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.PHONY: elf lss sym hex bin
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$(OUTDIR)/$(TARGET).bin.o: $(OUTDIR)/$(TARGET).bin
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.PHONY: elf lss sym hex bin bino
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elf: $(OUTDIR)/$(TARGET).elf
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lss: $(OUTDIR)/$(TARGET).lss
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sym: $(OUTDIR)/$(TARGET).sym
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@ -437,6 +422,7 @@ clean_list :
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$(V1) $(REMOVE) $(OUTDIR)/$(TARGET).bin
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$(V1) $(REMOVE) $(OUTDIR)/$(TARGET).sym
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$(V1) $(REMOVE) $(OUTDIR)/$(TARGET).lss
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$(V1) $(REMOVE) $(OUTDIR)/$(TARGET).bin.o
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$(V1) $(REMOVE) $(ALLOBJ)
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$(V1) $(REMOVE) $(LSTFILES)
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$(V1) $(REMOVE) $(DEPFILES)
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@ -70,17 +70,13 @@ TIM8 | | | |
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// BOOTLOADER_SETTINGS
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//------------------------
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//#define FUNC_ID 1
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//#define HW_VERSION 01
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#define BOOTLOADER_VERSION 0
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#define BOARD_TYPE 0x05 // INS board
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#define BOARD_REVISION 0x01 // Beta version
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#define BOOTLOADER_VERSION 0
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#define BOARD_TYPE 0x05 // INS board
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#define BOARD_REVISION 0x01 // Beta version
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//#define HW_VERSION (BOARD_TYPE << 8) | BOARD_REVISION
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#define MEM_SIZE 524288 //512K
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#define MEM_SIZE 524288 //512K
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#define SIZE_OF_DESCRIPTION (uint8_t) 100
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#define START_OF_USER_CODE (uint32_t)0x08005000//REMEMBER SET ALSO IN link_stm32f10x_HD_BL.ld
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#define START_OF_USER_CODE (uint32_t)0x08002000//REMEMBER SET ALSO IN link_STM3210E_INS_memory.ld
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#define SIZE_OF_CODE (uint32_t) (MEM_SIZE-(START_OF_USER_CODE-0x08000000)-SIZE_OF_DESCRIPTION)
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#ifdef STM32F10X_HD
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361
flight/PiOS/STM32F10x/link_STM3210E_INS_BL_sections.ld
Normal file
361
flight/PiOS/STM32F10x/link_STM3210E_INS_BL_sections.ld
Normal file
@ -0,0 +1,361 @@
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/* This is the size of the stack for early init and for all FreeRTOS IRQs */
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_irq_stack_size = 0x400;
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/* Check valid alignment for VTOR */
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ASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
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/*
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this sends all unreferenced IRQHandlers to reset
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*/
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PROVIDE ( Undefined_Handler = 0 ) ;
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PROVIDE ( SWI_Handler = 0 ) ;
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PROVIDE ( IRQ_Handler = 0 ) ;
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PROVIDE ( Prefetch_Handler = 0 ) ;
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PROVIDE ( Abort_Handler = 0 ) ;
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PROVIDE ( FIQ_Handler = 0 ) ;
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PROVIDE ( NMI_Handler = 0 ) ;
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PROVIDE ( HardFault_Handler = 0 ) ;
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PROVIDE ( MemManage_Handler = 0 ) ;
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PROVIDE ( BusFault_Handler = 0 ) ;
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PROVIDE ( UsageFault_Handler = 0 ) ;
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PROVIDE ( vPortSVCHandler = 0 ) ;
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PROVIDE ( DebugMon_Handler = 0 ) ;
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PROVIDE ( xPortPendSVHandler = 0 ) ;
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PROVIDE ( xPortSysTickHandler = 0 ) ;
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PROVIDE ( WWDG_IRQHandler = 0 ) ;
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PROVIDE ( PVD_IRQHandler = 0 ) ;
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PROVIDE ( TAMPER_IRQHandler = 0 ) ;
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PROVIDE ( RTC_IRQHandler = 0 ) ;
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PROVIDE ( FLASH_IRQHandler = 0 ) ;
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PROVIDE ( RCC_IRQHandler = 0 ) ;
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PROVIDE ( EXTI0_IRQHandler = 0 ) ;
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PROVIDE ( EXTI1_IRQHandler = 0 ) ;
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PROVIDE ( EXTI2_IRQHandler = 0 ) ;
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PROVIDE ( EXTI3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
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PROVIDE ( ADC_IRQHandler = 0 ) ;
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PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
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PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
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PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
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PROVIDE ( TIM2_IRQHandler = 0 ) ;
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PROVIDE ( TIM3_IRQHandler = 0 ) ;
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PROVIDE ( TIM4_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
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PROVIDE ( SPI1_IRQHandler = 0 ) ;
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PROVIDE ( SPI2_IRQHandler = 0 ) ;
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PROVIDE ( USART1_IRQHandler = 0 ) ;
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PROVIDE ( USART2_IRQHandler = 0 ) ;
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PROVIDE ( USART3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
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PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
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PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
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PROVIDE ( ADC3_IRQHandler = 0 ) ;
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PROVIDE ( FSMC_IRQHandler = 0 ) ;
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PROVIDE ( SDIO_IRQHandler = 0 ) ;
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PROVIDE ( TIM5_IRQHandler = 0 ) ;
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PROVIDE ( SPI3_IRQHandler = 0 ) ;
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PROVIDE ( UART4_IRQHandler = 0 ) ;
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PROVIDE ( UART5_IRQHandler = 0 ) ;
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PROVIDE ( TIM6_IRQHandler = 0 ) ;
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PROVIDE ( TIM7_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/*this allows to compile the ST lib in "non-debug" mode*/
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/* Peripheral and SRAM base address in the alias region */
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PERIPH_BB_BASE = 0x42000000;
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SRAM_BB_BASE = 0x22000000;
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/* Peripheral and SRAM base address in the bit-band region */
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SRAM_BASE = 0x20000000;
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PERIPH_BASE = 0x40000000;
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/* Flash registers base address */
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PROVIDE ( FLASH_BASE = 0x40022000);
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/* Flash Option Bytes base address */
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PROVIDE ( OB_BASE = 0x1FFFF800);
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/* Peripheral memory map */
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APB1PERIPH_BASE = PERIPH_BASE ;
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APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
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AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
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PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
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PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
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PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
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PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
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PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
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PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
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PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
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PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
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PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
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PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
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PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
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PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
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PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
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PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
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PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
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PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
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PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
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PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
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PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
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PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
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PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
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/* System Control Space memory map */
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SCS_BASE = 0xE000E000;
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PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
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PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
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PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
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/* Sections Definitions */
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SECTIONS
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{
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/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
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.isr_vector :
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{
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
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.flashtext :
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{
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. = ALIGN(4);
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*(.flashtext) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* init sections */
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.initcalluavobj.init :
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{
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. = ALIGN(4);
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__uavobj_initcall_start = .;
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KEEP(*(.initcalluavobj.init))
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. = ALIGN(4);
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__uavobj_initcall_end = .;
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} > BL_FLASH
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/* the program code is stored in the .text section, which goes to Flash */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* remaining code */
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*(.text.*) /* remaining code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(4);
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_etext = .;
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/* This is used by the startup in order to initialize the .data secion */
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_sidata = _etext;
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} > BL_FLASH
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/*
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* This stack is used both as the initial sp during early init as well as ultimately
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* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
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* is used for _all_ interrupt handlers. The end of this stack should be placed
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* against the lowest address in RAM so that a stack overrun results in a hard fault
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* at the first access beyond the end of the stack.
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*/
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.irq_stack :
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{
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. = ALIGN(4);
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_irq_stack_end = . ;
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. = . + _irq_stack_size ;
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. = ALIGN(4);
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_irq_stack_top = . - 4 ;
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. = ALIGN(4);
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} >RAM
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/* This is the initialized data section
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The program executes knowing that the data is in the RAM
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but the loader puts the initial values in the FLASH (inidata).
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It is one task of the startup to copy the initial values from FLASH to RAM. */
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.data : AT ( _sidata )
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_sdata = . ;
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*(.data)
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*(.data.*)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM
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/* This is the uninitialized data section */
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.bss :
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .;
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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} >RAM
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PROVIDE ( end = _ebss );
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PROVIDE ( _end = _ebss );
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/* this is the FLASH Bank1 */
|
||||
/* the C or assembly source must explicitly place the code or data there
|
||||
using the "section" attribute */
|
||||
.b1text :
|
||||
{
|
||||
*(.b1text) /* remaining code */
|
||||
*(.b1rodata) /* read-only data (constants) */
|
||||
*(.b1rodata*)
|
||||
} >FLASHB1
|
||||
|
||||
/* this is the EXTMEM */
|
||||
/* the C or assembly source must explicitly place the code or data there
|
||||
using the "section" attribute */
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb0text :
|
||||
{
|
||||
*(.eb0text) /* remaining code */
|
||||
*(.eb0rodata) /* read-only data (constants) */
|
||||
*(.eb0rodata*)
|
||||
} >EXTMEMB0
|
||||
|
||||
/* EXTMEM Bank1 */
|
||||
.eb1text :
|
||||
{
|
||||
*(.eb1text) /* remaining code */
|
||||
*(.eb1rodata) /* read-only data (constants) */
|
||||
*(.eb1rodata*)
|
||||
} >EXTMEMB1
|
||||
|
||||
/* EXTMEM Bank2 */
|
||||
.eb2text :
|
||||
{
|
||||
*(.eb2text) /* remaining code */
|
||||
*(.eb2rodata) /* read-only data (constants) */
|
||||
*(.eb2rodata*)
|
||||
} >EXTMEMB2
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb3text :
|
||||
{
|
||||
*(.eb3text) /* remaining code */
|
||||
*(.eb3rodata) /* read-only data (constants) */
|
||||
*(.eb3rodata*)
|
||||
} >EXTMEMB3
|
||||
|
||||
__exidx_start = .;
|
||||
__exidx_end = .;
|
||||
|
||||
/* after that it's only debugging information. */
|
||||
|
||||
/* remove the debugging information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
||||
|
||||
11
flight/PiOS/STM32F10x/link_STM3210E_INS_memory.ld
Normal file
11
flight/PiOS/STM32F10x/link_STM3210E_INS_memory.ld
Normal file
@ -0,0 +1,11 @@
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 8K
|
||||
FLASH (rx) : ORIGIN = 0x08000000 + 8K, LENGTH = 512K - 8k
|
||||
FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
}
|
||||
361
flight/PiOS/STM32F10x/link_STM3210E_INS_sections.ld
Normal file
361
flight/PiOS/STM32F10x/link_STM3210E_INS_sections.ld
Normal file
@ -0,0 +1,361 @@
|
||||
/* This is the size of the stack for early init and for all FreeRTOS IRQs */
|
||||
_irq_stack_size = 0x400;
|
||||
|
||||
/* Check valid alignment for VTOR */
|
||||
ASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
|
||||
|
||||
/*
|
||||
this sends all unreferenced IRQHandlers to reset
|
||||
*/
|
||||
|
||||
|
||||
PROVIDE ( Undefined_Handler = 0 ) ;
|
||||
PROVIDE ( SWI_Handler = 0 ) ;
|
||||
PROVIDE ( IRQ_Handler = 0 ) ;
|
||||
PROVIDE ( Prefetch_Handler = 0 ) ;
|
||||
PROVIDE ( Abort_Handler = 0 ) ;
|
||||
PROVIDE ( FIQ_Handler = 0 ) ;
|
||||
|
||||
PROVIDE ( NMI_Handler = 0 ) ;
|
||||
PROVIDE ( HardFault_Handler = 0 ) ;
|
||||
PROVIDE ( MemManage_Handler = 0 ) ;
|
||||
PROVIDE ( BusFault_Handler = 0 ) ;
|
||||
PROVIDE ( UsageFault_Handler = 0 ) ;
|
||||
PROVIDE ( vPortSVCHandler = 0 ) ;
|
||||
PROVIDE ( DebugMon_Handler = 0 ) ;
|
||||
PROVIDE ( xPortPendSVHandler = 0 ) ;
|
||||
PROVIDE ( xPortSysTickHandler = 0 ) ;
|
||||
|
||||
PROVIDE ( WWDG_IRQHandler = 0 ) ;
|
||||
PROVIDE ( PVD_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TAMPER_IRQHandler = 0 ) ;
|
||||
PROVIDE ( RTC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( FLASH_IRQHandler = 0 ) ;
|
||||
PROVIDE ( RCC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI0_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI4_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
|
||||
PROVIDE ( ADC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
|
||||
PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM4_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
|
||||
PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SPI1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SPI2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USART1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USART2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USART3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
|
||||
PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
|
||||
PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( ADC3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( FSMC_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SDIO_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( SPI3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( UART4_IRQHandler = 0 ) ;
|
||||
PROVIDE ( UART5_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM6_IRQHandler = 0 ) ;
|
||||
PROVIDE ( TIM7_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
|
||||
PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
/*this allows to compile the ST lib in "non-debug" mode*/
|
||||
|
||||
|
||||
/* Peripheral and SRAM base address in the alias region */
|
||||
PERIPH_BB_BASE = 0x42000000;
|
||||
SRAM_BB_BASE = 0x22000000;
|
||||
|
||||
/* Peripheral and SRAM base address in the bit-band region */
|
||||
SRAM_BASE = 0x20000000;
|
||||
PERIPH_BASE = 0x40000000;
|
||||
|
||||
/* Flash registers base address */
|
||||
PROVIDE ( FLASH_BASE = 0x40022000);
|
||||
/* Flash Option Bytes base address */
|
||||
PROVIDE ( OB_BASE = 0x1FFFF800);
|
||||
|
||||
/* Peripheral memory map */
|
||||
APB1PERIPH_BASE = PERIPH_BASE ;
|
||||
APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
|
||||
AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
|
||||
|
||||
PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
|
||||
PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
|
||||
PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
|
||||
PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
|
||||
PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
|
||||
PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
|
||||
PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
|
||||
PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
|
||||
PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
|
||||
PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
|
||||
PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
|
||||
PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
|
||||
PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
|
||||
PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
|
||||
|
||||
PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
|
||||
PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
|
||||
PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
|
||||
PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
|
||||
PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
|
||||
PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
|
||||
PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
|
||||
PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
|
||||
PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
|
||||
PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
|
||||
PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
|
||||
PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
|
||||
|
||||
PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
|
||||
PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
|
||||
PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
|
||||
PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
|
||||
PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
|
||||
PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
|
||||
PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
|
||||
PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
|
||||
PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
|
||||
|
||||
/* System Control Space memory map */
|
||||
SCS_BASE = 0xE000E000;
|
||||
|
||||
PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
|
||||
PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
|
||||
PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
|
||||
|
||||
|
||||
/* Sections Definitions */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
|
||||
.flashtext :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.flashtext) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
|
||||
/* init sections */
|
||||
.initcalluavobj.init :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__uavobj_initcall_start = .;
|
||||
KEEP(*(.initcalluavobj.init))
|
||||
. = ALIGN(4);
|
||||
__uavobj_initcall_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* the program code is stored in the .text section, which goes to Flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = _etext;
|
||||
} >FLASH
|
||||
|
||||
|
||||
/*
|
||||
* This stack is used both as the initial sp during early init as well as ultimately
|
||||
* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
|
||||
* is used for _all_ interrupt handlers. The end of this stack should be placed
|
||||
* against the lowest address in RAM so that a stack overrun results in a hard fault
|
||||
* at the first access beyond the end of the stack.
|
||||
*/
|
||||
.irq_stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_irq_stack_end = . ;
|
||||
. = . + _irq_stack_size ;
|
||||
. = ALIGN(4);
|
||||
_irq_stack_top = . - 4 ;
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
|
||||
|
||||
/* This is the initialized data section
|
||||
The program executes knowing that the data is in the RAM
|
||||
but the loader puts the initial values in the FLASH (inidata).
|
||||
It is one task of the startup to copy the initial values from FLASH to RAM. */
|
||||
.data : AT ( _sidata )
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >RAM
|
||||
|
||||
|
||||
|
||||
/* This is the uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
} >RAM
|
||||
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
|
||||
/* this is the FLASH Bank1 */
|
||||
/* the C or assembly source must explicitly place the code or data there
|
||||
using the "section" attribute */
|
||||
.b1text :
|
||||
{
|
||||
*(.b1text) /* remaining code */
|
||||
*(.b1rodata) /* read-only data (constants) */
|
||||
*(.b1rodata*)
|
||||
} >FLASHB1
|
||||
|
||||
/* this is the EXTMEM */
|
||||
/* the C or assembly source must explicitly place the code or data there
|
||||
using the "section" attribute */
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb0text :
|
||||
{
|
||||
*(.eb0text) /* remaining code */
|
||||
*(.eb0rodata) /* read-only data (constants) */
|
||||
*(.eb0rodata*)
|
||||
} >EXTMEMB0
|
||||
|
||||
/* EXTMEM Bank1 */
|
||||
.eb1text :
|
||||
{
|
||||
*(.eb1text) /* remaining code */
|
||||
*(.eb1rodata) /* read-only data (constants) */
|
||||
*(.eb1rodata*)
|
||||
} >EXTMEMB1
|
||||
|
||||
/* EXTMEM Bank2 */
|
||||
.eb2text :
|
||||
{
|
||||
*(.eb2text) /* remaining code */
|
||||
*(.eb2rodata) /* read-only data (constants) */
|
||||
*(.eb2rodata*)
|
||||
} >EXTMEMB2
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb3text :
|
||||
{
|
||||
*(.eb3text) /* remaining code */
|
||||
*(.eb3rodata) /* read-only data (constants) */
|
||||
*(.eb3rodata*)
|
||||
} >EXTMEMB3
|
||||
|
||||
__exidx_start = .;
|
||||
__exidx_end = .;
|
||||
|
||||
/* after that it's only debugging information. */
|
||||
|
||||
/* remove the debugging information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
||||
|
||||
@ -139,6 +139,10 @@
|
||||
65988573138440CB006777AA /* link_STM3210E_OP_memory.ld */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = link_STM3210E_OP_memory.ld; sourceTree = "<group>"; };
|
||||
6598857F138442D0006777AA /* startup_stm32f10x_MD_CC.S */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.asm; path = startup_stm32f10x_MD_CC.S; sourceTree = "<group>"; };
|
||||
65988580138442D0006777AA /* startup_stm32f10x_HD_OP.S */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.asm; path = startup_stm32f10x_HD_OP.S; sourceTree = "<group>"; };
|
||||
659885A313845038006777AA /* STM3210E_INS.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = STM3210E_INS.h; sourceTree = "<group>"; };
|
||||
659885AD138450D2006777AA /* link_STM3210E_INS_sections.ld */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = link_STM3210E_INS_sections.ld; sourceTree = "<group>"; };
|
||||
659885AE138450D2006777AA /* link_STM3210E_INS_BL_sections.ld */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = link_STM3210E_INS_BL_sections.ld; sourceTree = "<group>"; };
|
||||
659885AF138450D2006777AA /* link_STM3210E_INS_memory.ld */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = link_STM3210E_INS_memory.ld; sourceTree = "<group>"; };
|
||||
659ED317122226B60011010E /* ahrssettings.xml */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.xml; path = ahrssettings.xml; sourceTree = "<group>"; };
|
||||
65B35D7F121C261E003EAD18 /* bin.pro */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = bin.pro; sourceTree = "<group>"; };
|
||||
65B35D80121C261E003EAD18 /* openpilotgcs */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.script.sh; path = openpilotgcs; sourceTree = "<group>"; };
|
||||
@ -3582,6 +3586,7 @@
|
||||
children = (
|
||||
65632DF51251650300469B77 /* pios_board.h */,
|
||||
65632DF71251650300469B77 /* STM3210E_OP.h */,
|
||||
659885A313845038006777AA /* STM3210E_INS.h */,
|
||||
65632DF61251650300469B77 /* STM32103CB_AHRS.h */,
|
||||
65E6E06112E031E300058553 /* STM32103CB_CC_Rev1.h */,
|
||||
65E6E06212E031E300058553 /* STM32103CB_PIPXTREME_Rev1.h */,
|
||||
@ -7818,14 +7823,17 @@
|
||||
65988568138440CB006777AA /* link_STM32103CB_PIPXTREME_sections.ld */,
|
||||
65988569138440CB006777AA /* link_STM32103CB_PIPXTREME_BL_sections.ld */,
|
||||
6598856A138440CB006777AA /* link_STM32103CB_AHRS_sections.ld */,
|
||||
65988572138440CB006777AA /* link_STM32103CB_AHRS_memory.ld */,
|
||||
6598856B138440CB006777AA /* link_STM32103CB_AHRS_BL_sections.ld */,
|
||||
659885AD138450D2006777AA /* link_STM3210E_INS_sections.ld */,
|
||||
659885AE138450D2006777AA /* link_STM3210E_INS_BL_sections.ld */,
|
||||
659885AF138450D2006777AA /* link_STM3210E_INS_memory.ld */,
|
||||
6598856C138440CB006777AA /* link_STM3210E_OP_sections.ld */,
|
||||
6598856D138440CB006777AA /* link_STM3210E_OP_BL_sections.ld */,
|
||||
6598856E138440CB006777AA /* link_STM32103CB_PIPXTREME_memory.ld */,
|
||||
6598856F138440CB006777AA /* link_STM32103CB_CC_Rev1_sections.ld */,
|
||||
65988570138440CB006777AA /* link_STM32103CB_CC_Rev1_memory.ld */,
|
||||
65988571138440CB006777AA /* link_STM32103CB_CC_Rev1_BL_sections.ld */,
|
||||
65988572138440CB006777AA /* link_STM32103CB_AHRS_memory.ld */,
|
||||
65988573138440CB006777AA /* link_STM3210E_OP_memory.ld */,
|
||||
65E8F0D811EFF25C00BBF654 /* link_stm32f10x_HD.ld */,
|
||||
65E8F0DB11EFF25C00BBF654 /* link_stm32f10x_MD.ld */,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user