From b59408863ac7989a334272edd90f196f341b2824 Mon Sep 17 00:00:00 2001 From: Alessio Morale Date: Thu, 4 Sep 2014 15:13:16 +0200 Subject: [PATCH] REVONANO - Allows per board linker scripts --- flight/pios/stm32f4xx/library.mk | 16 +- ...mory.ld => link_STM32F4xx_DI_bl_memory.ld} | 0 ...mory.ld => link_STM32F4xx_DI_fw_memory.ld} | 0 ...tions.ld => link_STM32F4xx_DI_sections.ld} | 0 ...d => link_STM32F4xx_DI_sections_compat.ld} | 0 .../stm32f4xx/link_STM32F4xx_OSD_bl_memory.ld | 7 + .../stm32f4xx/link_STM32F4xx_OSD_fw_memory.ld | 8 + .../stm32f4xx/link_STM32F4xx_OSD_sections.ld | 193 ++++++++++++++++++ .../link_STM32F4xx_OSD_sections_compat.ld | 176 ++++++++++++++++ .../stm32f4xx/link_STM32F4xx_RM_bl_memory.ld | 7 + .../stm32f4xx/link_STM32F4xx_RM_fw_memory.ld | 8 + .../stm32f4xx/link_STM32F4xx_RM_sections.ld | 193 ++++++++++++++++++ .../link_STM32F4xx_RM_sections_compat.ld | 176 ++++++++++++++++ .../stm32f4xx/link_STM32F4xx_RP_bl_memory.ld | 7 + .../stm32f4xx/link_STM32F4xx_RP_fw_memory.ld | 8 + .../stm32f4xx/link_STM32F4xx_RP_sections.ld | 193 ++++++++++++++++++ .../link_STM32F4xx_RP_sections_compat.ld | 176 ++++++++++++++++ flight/targets/boards/revoproto/board-info.mk | 2 +- 18 files changed, 1163 insertions(+), 7 deletions(-) rename flight/pios/stm32f4xx/{link_stm32f4xx_bl_memory.ld => link_STM32F4xx_DI_bl_memory.ld} (100%) rename flight/pios/stm32f4xx/{link_stm32f4xx_fw_memory.ld => link_STM32F4xx_DI_fw_memory.ld} (100%) rename flight/pios/stm32f4xx/{link_stm32f4xx_sections.ld => link_STM32F4xx_DI_sections.ld} (100%) rename flight/pios/stm32f4xx/{link_stm32f4xx_sections_compat.ld => link_STM32F4xx_DI_sections_compat.ld} (100%) create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_OSD_bl_memory.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_OSD_fw_memory.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections_compat.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RM_bl_memory.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RM_fw_memory.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RM_sections.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RM_sections_compat.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RP_bl_memory.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RP_fw_memory.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RP_sections.ld create mode 100644 flight/pios/stm32f4xx/link_STM32F4xx_RP_sections_compat.ld diff --git a/flight/pios/stm32f4xx/library.mk b/flight/pios/stm32f4xx/library.mk index b7e766911..eeaf88577 100644 --- a/flight/pios/stm32f4xx/library.mk +++ b/flight/pios/stm32f4xx/library.mk @@ -6,13 +6,13 @@ PIOS_DEVLIB := $(dir $(lastword $(MAKEFILE_LIST))) # Hardcoded linker script names for now -LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)link_stm32f4xx_fw_memory.ld \ - $(PIOS_DEVLIB)link_stm32f4xx_sections.ld -LINKER_SCRIPTS_BL = $(PIOS_DEVLIB)link_stm32f4xx_bl_memory.ld \ - $(PIOS_DEVLIB)link_stm32f4xx_sections.ld +LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)link_$(BOARD)_fw_memory.ld \ + $(PIOS_DEVLIB)link_$(BOARD)_sections.ld +LINKER_SCRIPTS_BL = $(PIOS_DEVLIB)link_$(BOARD)_bl_memory.ld \ + $(PIOS_DEVLIB)link_$(BOARD)_sections.ld # _compat linker script are aimed at bootloader updater to guarantee to be compatible with earlier bootloaders. -LINKER_SCRIPTS_COMPAT = $(PIOS_DEVLIB)link_stm32f4xx_fw_memory.ld \ - $(PIOS_DEVLIB)link_stm32f4xx_sections_compat.ld +LINKER_SCRIPTS_COMPAT = $(PIOS_DEVLIB)link_$(BOARD)_fw_memory.ld \ + $(PIOS_DEVLIB)link_$(BOARD)_sections_compat.ld # Compiler options implied by the F4xx CDEFS += -DSTM32F4XX @@ -20,7 +20,11 @@ CDEFS += -DSYSCLK_FREQ=$(SYSCLK_FREQ) CDEFS += -DHSE_VALUE=$(OSCILLATOR_FREQ) CDEFS += -DUSE_STDPERIPH_DRIVER CDEFS += -DARM_MATH_CM4 -D__FPU_PRESENT=1 +ifneq ($(NOCCSRAM),YES) CDEFS += -DPIOS_TARGET_PROVIDES_FAST_HEAP +else +$(error NOCCSRAM) +endif ARCHFLAGS += -mcpu=cortex-m4 -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard # PIOS device library source and includes diff --git a/flight/pios/stm32f4xx/link_stm32f4xx_bl_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_DI_bl_memory.ld similarity index 100% rename from flight/pios/stm32f4xx/link_stm32f4xx_bl_memory.ld rename to flight/pios/stm32f4xx/link_STM32F4xx_DI_bl_memory.ld diff --git a/flight/pios/stm32f4xx/link_stm32f4xx_fw_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_DI_fw_memory.ld similarity index 100% rename from flight/pios/stm32f4xx/link_stm32f4xx_fw_memory.ld rename to flight/pios/stm32f4xx/link_STM32F4xx_DI_fw_memory.ld diff --git a/flight/pios/stm32f4xx/link_stm32f4xx_sections.ld b/flight/pios/stm32f4xx/link_STM32F4xx_DI_sections.ld similarity index 100% rename from flight/pios/stm32f4xx/link_stm32f4xx_sections.ld rename to flight/pios/stm32f4xx/link_STM32F4xx_DI_sections.ld diff --git a/flight/pios/stm32f4xx/link_stm32f4xx_sections_compat.ld b/flight/pios/stm32f4xx/link_STM32F4xx_DI_sections_compat.ld similarity index 100% rename from flight/pios/stm32f4xx/link_stm32f4xx_sections_compat.ld rename to flight/pios/stm32f4xx/link_STM32F4xx_DI_sections_compat.ld diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_OSD_bl_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_bl_memory.ld new file mode 100644 index 000000000..3c0a67711 --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_bl_memory.ld @@ -0,0 +1,7 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x008000 - 0x000080 + BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x020000 + CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000 +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_OSD_fw_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_fw_memory.ld new file mode 100644 index 000000000..9f279355d --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_fw_memory.ld @@ -0,0 +1,8 @@ +MEMORY +{ + BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080 + RSVD (rx) : ORIGIN = 0x08008000, LENGTH = 0x020000 - 0x008000 + FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 0x0e0000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x020000 + CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000 +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections.ld b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections.ld new file mode 100644 index 000000000..99a3f509f --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections.ld @@ -0,0 +1,193 @@ + +/* Section Definitions */ +SECTIONS +{ + /* + * Vectors, code and constant data. + */ + .text : + { + PROVIDE (pios_isr_vector_table_base = .); + KEEP(*(.cpu_vectors)) /* CPU exception vectors */ + KEEP(*(.io_vectors)) /* I/O interrupt vectors */ + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + } > FLASH + + /* + * Init section for UAVObjects. + */ + .initcalluavobj.init : + { + . = ALIGN(4); + __uavobj_initcall_start = .; + KEEP(*(.initcalluavobj.init)) + . = ALIGN(4); + __uavobj_initcall_end = .; + } >FLASH + + /* + * Module init section section + */ + .initcallmodule.init : + { + . = ALIGN(4); + __module_initcall_start = .; + KEEP(*(.initcallmodule.init)) + . = ALIGN(4); + __module_initcall_end = .; + } >FLASH + + /* + * C++ exception handling. + */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* + * Markers for the end of the 'text' section and the in-flash start of + * non-constant data + */ + . = ALIGN(4); + _etext = .; + _sidata = .; + + /* + * Board info structure, normally only generated by the bootloader but can + * be read by the application. + */ + PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO)); + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO)); + } > BD_INFO + + /* + * Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow + * results in a hard fault. + */ + .istack (NOLOAD) : + { + . = ALIGN(4); + _irq_stack_end = . ; + *(.irqstack) + _irq_stack_top = . ; + } > CCSRAM + + + /* + * Non-const initialised data. + */ + .data : AT (_sidata) + { + . = ALIGN(4); + _sdata = .; + *(.data .data.*) + . = ALIGN(4); + _edata = . ; + } > SRAM + + /* + * Uninitialised data (BSS + commons). + */ + .bss (NOLOAD) : + { + _sbss = . ; + *(.bss .bss.*) + *(COMMON) + _ebss = . ; + PROVIDE ( _end = _ebss ) ; + } > SRAM + + /* + * The heap consumes the remainder of the SRAM. + */ + .heap (NOLOAD) : + { + . = ALIGN(4); + _sheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.heap) + + /* extend the heap up to the top of SRAM */ + . = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap); + _eheap = .; + } > SRAM + + /* + * 'Fast' memory goes in the CCM SRAM + */ + .fast (NOLOAD) : + { + _sfast = . ; + *(.fast) + _efast = . ; + } > CCSRAM + + .fastheap (NOLOAD) : + { + . = ALIGN(4); + _sfastheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.fastheap) + + /* extend the fastheap up to the top of CCSRAM */ + . = ORIGIN(CCSRAM) + LENGTH(CCSRAM) - ABSOLUTE(_sfastheap); + _efastheap = .; + } > CCSRAM + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections_compat.ld b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections_compat.ld new file mode 100644 index 000000000..c6701fb19 --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_OSD_sections_compat.ld @@ -0,0 +1,176 @@ + +/* Section Definitions */ +SECTIONS +{ + /* + * Vectors, code and constant data. + */ + .text : + { + PROVIDE (pios_isr_vector_table_base = .); + KEEP(*(.cpu_vectors)) /* CPU exception vectors */ + KEEP(*(.io_vectors)) /* I/O interrupt vectors */ + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + } > FLASH + + /* + * Init section for UAVObjects. + */ + .initcalluavobj.init : + { + . = ALIGN(4); + __uavobj_initcall_start = .; + KEEP(*(.initcalluavobj.init)) + . = ALIGN(4); + __uavobj_initcall_end = .; + } >FLASH + + /* + * Module init section section + */ + .initcallmodule.init : + { + . = ALIGN(4); + __module_initcall_start = .; + KEEP(*(.initcallmodule.init)) + . = ALIGN(4); + __module_initcall_end = .; + } >FLASH + + /* + * C++ exception handling. + */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* + * Markers for the end of the 'text' section and the in-flash start of + * non-constant data + */ + . = ALIGN(4); + _etext = .; + _sidata = .; + + /* + * Board info structure, normally only generated by the bootloader but can + * be read by the application. + */ + PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO)); + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO)); + } > BD_INFO + + /* + * Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow + * results in a hard fault. + */ + .istack (NOLOAD) : + { + . = ALIGN(4); + _irq_stack_end = . ; + *(.irqstack) + _irq_stack_top = . ; + } > SRAM + + + /* + * Non-const initialised data. + */ + .data : AT (_sidata) + { + . = ALIGN(4); + _sdata = .; + *(.data .data.*) + . = ALIGN(4); + _edata = . ; + } > SRAM + + /* + * Uninitialised data (BSS + commons). + */ + .bss (NOLOAD) : + { + _sbss = . ; + *(.bss .bss.*) + *(COMMON) + _ebss = . ; + PROVIDE ( _end = _ebss ) ; + } > SRAM + + /* + * The heap consumes the remainder of the SRAM. + */ + .heap (NOLOAD) : + { + . = ALIGN(4); + _sheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.heap) + + /* extend the heap up to the top of SRAM */ + . = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap); + _eheap = .; + } > SRAM + + /* + * 'Fast' memory goes in the CCM SRAM + */ + .fast (NOLOAD) : + { + _sfast = . ; + *(.fast) + _efast = . ; + } > CCSRAM + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RM_bl_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RM_bl_memory.ld new file mode 100644 index 000000000..3c0a67711 --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RM_bl_memory.ld @@ -0,0 +1,7 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x008000 - 0x000080 + BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x020000 + CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000 +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RM_fw_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RM_fw_memory.ld new file mode 100644 index 000000000..9f279355d --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RM_fw_memory.ld @@ -0,0 +1,8 @@ +MEMORY +{ + BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080 + RSVD (rx) : ORIGIN = 0x08008000, LENGTH = 0x020000 - 0x008000 + FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 0x0e0000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x020000 + CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000 +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RM_sections.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RM_sections.ld new file mode 100644 index 000000000..99a3f509f --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RM_sections.ld @@ -0,0 +1,193 @@ + +/* Section Definitions */ +SECTIONS +{ + /* + * Vectors, code and constant data. + */ + .text : + { + PROVIDE (pios_isr_vector_table_base = .); + KEEP(*(.cpu_vectors)) /* CPU exception vectors */ + KEEP(*(.io_vectors)) /* I/O interrupt vectors */ + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + } > FLASH + + /* + * Init section for UAVObjects. + */ + .initcalluavobj.init : + { + . = ALIGN(4); + __uavobj_initcall_start = .; + KEEP(*(.initcalluavobj.init)) + . = ALIGN(4); + __uavobj_initcall_end = .; + } >FLASH + + /* + * Module init section section + */ + .initcallmodule.init : + { + . = ALIGN(4); + __module_initcall_start = .; + KEEP(*(.initcallmodule.init)) + . = ALIGN(4); + __module_initcall_end = .; + } >FLASH + + /* + * C++ exception handling. + */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* + * Markers for the end of the 'text' section and the in-flash start of + * non-constant data + */ + . = ALIGN(4); + _etext = .; + _sidata = .; + + /* + * Board info structure, normally only generated by the bootloader but can + * be read by the application. + */ + PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO)); + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO)); + } > BD_INFO + + /* + * Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow + * results in a hard fault. + */ + .istack (NOLOAD) : + { + . = ALIGN(4); + _irq_stack_end = . ; + *(.irqstack) + _irq_stack_top = . ; + } > CCSRAM + + + /* + * Non-const initialised data. + */ + .data : AT (_sidata) + { + . = ALIGN(4); + _sdata = .; + *(.data .data.*) + . = ALIGN(4); + _edata = . ; + } > SRAM + + /* + * Uninitialised data (BSS + commons). + */ + .bss (NOLOAD) : + { + _sbss = . ; + *(.bss .bss.*) + *(COMMON) + _ebss = . ; + PROVIDE ( _end = _ebss ) ; + } > SRAM + + /* + * The heap consumes the remainder of the SRAM. + */ + .heap (NOLOAD) : + { + . = ALIGN(4); + _sheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.heap) + + /* extend the heap up to the top of SRAM */ + . = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap); + _eheap = .; + } > SRAM + + /* + * 'Fast' memory goes in the CCM SRAM + */ + .fast (NOLOAD) : + { + _sfast = . ; + *(.fast) + _efast = . ; + } > CCSRAM + + .fastheap (NOLOAD) : + { + . = ALIGN(4); + _sfastheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.fastheap) + + /* extend the fastheap up to the top of CCSRAM */ + . = ORIGIN(CCSRAM) + LENGTH(CCSRAM) - ABSOLUTE(_sfastheap); + _efastheap = .; + } > CCSRAM + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RM_sections_compat.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RM_sections_compat.ld new file mode 100644 index 000000000..c6701fb19 --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RM_sections_compat.ld @@ -0,0 +1,176 @@ + +/* Section Definitions */ +SECTIONS +{ + /* + * Vectors, code and constant data. + */ + .text : + { + PROVIDE (pios_isr_vector_table_base = .); + KEEP(*(.cpu_vectors)) /* CPU exception vectors */ + KEEP(*(.io_vectors)) /* I/O interrupt vectors */ + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + } > FLASH + + /* + * Init section for UAVObjects. + */ + .initcalluavobj.init : + { + . = ALIGN(4); + __uavobj_initcall_start = .; + KEEP(*(.initcalluavobj.init)) + . = ALIGN(4); + __uavobj_initcall_end = .; + } >FLASH + + /* + * Module init section section + */ + .initcallmodule.init : + { + . = ALIGN(4); + __module_initcall_start = .; + KEEP(*(.initcallmodule.init)) + . = ALIGN(4); + __module_initcall_end = .; + } >FLASH + + /* + * C++ exception handling. + */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* + * Markers for the end of the 'text' section and the in-flash start of + * non-constant data + */ + . = ALIGN(4); + _etext = .; + _sidata = .; + + /* + * Board info structure, normally only generated by the bootloader but can + * be read by the application. + */ + PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO)); + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO)); + } > BD_INFO + + /* + * Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow + * results in a hard fault. + */ + .istack (NOLOAD) : + { + . = ALIGN(4); + _irq_stack_end = . ; + *(.irqstack) + _irq_stack_top = . ; + } > SRAM + + + /* + * Non-const initialised data. + */ + .data : AT (_sidata) + { + . = ALIGN(4); + _sdata = .; + *(.data .data.*) + . = ALIGN(4); + _edata = . ; + } > SRAM + + /* + * Uninitialised data (BSS + commons). + */ + .bss (NOLOAD) : + { + _sbss = . ; + *(.bss .bss.*) + *(COMMON) + _ebss = . ; + PROVIDE ( _end = _ebss ) ; + } > SRAM + + /* + * The heap consumes the remainder of the SRAM. + */ + .heap (NOLOAD) : + { + . = ALIGN(4); + _sheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.heap) + + /* extend the heap up to the top of SRAM */ + . = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap); + _eheap = .; + } > SRAM + + /* + * 'Fast' memory goes in the CCM SRAM + */ + .fast (NOLOAD) : + { + _sfast = . ; + *(.fast) + _efast = . ; + } > CCSRAM + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RP_bl_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RP_bl_memory.ld new file mode 100644 index 000000000..3c0a67711 --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RP_bl_memory.ld @@ -0,0 +1,7 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x008000 - 0x000080 + BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x020000 + CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000 +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RP_fw_memory.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RP_fw_memory.ld new file mode 100644 index 000000000..9f279355d --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RP_fw_memory.ld @@ -0,0 +1,8 @@ +MEMORY +{ + BD_INFO (r) : ORIGIN = 0x08008000 - 0x80, LENGTH = 0x000080 + RSVD (rx) : ORIGIN = 0x08008000, LENGTH = 0x020000 - 0x008000 + FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 0x0e0000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x020000 + CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x010000 +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RP_sections.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RP_sections.ld new file mode 100644 index 000000000..99a3f509f --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RP_sections.ld @@ -0,0 +1,193 @@ + +/* Section Definitions */ +SECTIONS +{ + /* + * Vectors, code and constant data. + */ + .text : + { + PROVIDE (pios_isr_vector_table_base = .); + KEEP(*(.cpu_vectors)) /* CPU exception vectors */ + KEEP(*(.io_vectors)) /* I/O interrupt vectors */ + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + } > FLASH + + /* + * Init section for UAVObjects. + */ + .initcalluavobj.init : + { + . = ALIGN(4); + __uavobj_initcall_start = .; + KEEP(*(.initcalluavobj.init)) + . = ALIGN(4); + __uavobj_initcall_end = .; + } >FLASH + + /* + * Module init section section + */ + .initcallmodule.init : + { + . = ALIGN(4); + __module_initcall_start = .; + KEEP(*(.initcallmodule.init)) + . = ALIGN(4); + __module_initcall_end = .; + } >FLASH + + /* + * C++ exception handling. + */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* + * Markers for the end of the 'text' section and the in-flash start of + * non-constant data + */ + . = ALIGN(4); + _etext = .; + _sidata = .; + + /* + * Board info structure, normally only generated by the bootloader but can + * be read by the application. + */ + PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO)); + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO)); + } > BD_INFO + + /* + * Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow + * results in a hard fault. + */ + .istack (NOLOAD) : + { + . = ALIGN(4); + _irq_stack_end = . ; + *(.irqstack) + _irq_stack_top = . ; + } > CCSRAM + + + /* + * Non-const initialised data. + */ + .data : AT (_sidata) + { + . = ALIGN(4); + _sdata = .; + *(.data .data.*) + . = ALIGN(4); + _edata = . ; + } > SRAM + + /* + * Uninitialised data (BSS + commons). + */ + .bss (NOLOAD) : + { + _sbss = . ; + *(.bss .bss.*) + *(COMMON) + _ebss = . ; + PROVIDE ( _end = _ebss ) ; + } > SRAM + + /* + * The heap consumes the remainder of the SRAM. + */ + .heap (NOLOAD) : + { + . = ALIGN(4); + _sheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.heap) + + /* extend the heap up to the top of SRAM */ + . = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap); + _eheap = .; + } > SRAM + + /* + * 'Fast' memory goes in the CCM SRAM + */ + .fast (NOLOAD) : + { + _sfast = . ; + *(.fast) + _efast = . ; + } > CCSRAM + + .fastheap (NOLOAD) : + { + . = ALIGN(4); + _sfastheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.fastheap) + + /* extend the fastheap up to the top of CCSRAM */ + . = ORIGIN(CCSRAM) + LENGTH(CCSRAM) - ABSOLUTE(_sfastheap); + _efastheap = .; + } > CCSRAM + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/flight/pios/stm32f4xx/link_STM32F4xx_RP_sections_compat.ld b/flight/pios/stm32f4xx/link_STM32F4xx_RP_sections_compat.ld new file mode 100644 index 000000000..c6701fb19 --- /dev/null +++ b/flight/pios/stm32f4xx/link_STM32F4xx_RP_sections_compat.ld @@ -0,0 +1,176 @@ + +/* Section Definitions */ +SECTIONS +{ + /* + * Vectors, code and constant data. + */ + .text : + { + PROVIDE (pios_isr_vector_table_base = .); + KEEP(*(.cpu_vectors)) /* CPU exception vectors */ + KEEP(*(.io_vectors)) /* I/O interrupt vectors */ + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + } > FLASH + + /* + * Init section for UAVObjects. + */ + .initcalluavobj.init : + { + . = ALIGN(4); + __uavobj_initcall_start = .; + KEEP(*(.initcalluavobj.init)) + . = ALIGN(4); + __uavobj_initcall_end = .; + } >FLASH + + /* + * Module init section section + */ + .initcallmodule.init : + { + . = ALIGN(4); + __module_initcall_start = .; + KEEP(*(.initcallmodule.init)) + . = ALIGN(4); + __module_initcall_end = .; + } >FLASH + + /* + * C++ exception handling. + */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* + * Markers for the end of the 'text' section and the in-flash start of + * non-constant data + */ + . = ALIGN(4); + _etext = .; + _sidata = .; + + /* + * Board info structure, normally only generated by the bootloader but can + * be read by the application. + */ + PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO)); + .boardinfo : + { + . = ALIGN(4); + KEEP(*(.boardinfo)) + . = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO)); + } > BD_INFO + + /* + * Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow + * results in a hard fault. + */ + .istack (NOLOAD) : + { + . = ALIGN(4); + _irq_stack_end = . ; + *(.irqstack) + _irq_stack_top = . ; + } > SRAM + + + /* + * Non-const initialised data. + */ + .data : AT (_sidata) + { + . = ALIGN(4); + _sdata = .; + *(.data .data.*) + . = ALIGN(4); + _edata = . ; + } > SRAM + + /* + * Uninitialised data (BSS + commons). + */ + .bss (NOLOAD) : + { + _sbss = . ; + *(.bss .bss.*) + *(COMMON) + _ebss = . ; + PROVIDE ( _end = _ebss ) ; + } > SRAM + + /* + * The heap consumes the remainder of the SRAM. + */ + .heap (NOLOAD) : + { + . = ALIGN(4); + _sheap = . ; + + /* + * This allows us to declare an object or objects up to the minimum acceptable + * heap size and receive a linker error if the space available for the heap is + * not sufficient. + */ + *(.heap) + + /* extend the heap up to the top of SRAM */ + . = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap); + _eheap = .; + } > SRAM + + /* + * 'Fast' memory goes in the CCM SRAM + */ + .fast (NOLOAD) : + { + _sfast = . ; + *(.fast) + _efast = . ; + } > CCSRAM + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/flight/targets/boards/revoproto/board-info.mk b/flight/targets/boards/revoproto/board-info.mk index 1337952eb..fb3fdd67c 100644 --- a/flight/targets/boards/revoproto/board-info.mk +++ b/flight/targets/boards/revoproto/board-info.mk @@ -5,7 +5,7 @@ HW_TYPE := 0x00 MCU := cortex-m4 CHIP := STM32F405RGT -BOARD := STM32F4xx_OP +BOARD := STM32F4xx_RP MODEL := HD MODEL_SUFFIX :=