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Code Issues Releases Activity

OP-1275 uncrustification

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This commit is contained in:
Alessio Morale 2014-06-29 12:10:17 +02:00
parent 55d52ceab0
commit baad216810
8 changed files with 69 additions and 72 deletions
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10
flight/pios/inc/stm32f0xx_conf.h
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@ -32,12 +32,12 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */ /* Comment the line below to disable peripheral header file inclusion */
#include "stm32f0xx_adc.h" #include "stm32f0xx_adc.h"
//#include "stm32f0xx_can.h" // #include "stm32f0xx_can.h"
//#include "stm32f0xx_cec.h" // #include "stm32f0xx_cec.h"
#include "stm32f0xx_crc.h" #include "stm32f0xx_crc.h"
#include "stm32f0xx_crs.h" #include "stm32f0xx_crs.h"
//#include "stm32f0xx_comp.h" // #include "stm32f0xx_comp.h"
//#include "stm32f0xx_dac.h" // #include "stm32f0xx_dac.h"
#include "stm32f0xx_dbgmcu.h" #include "stm32f0xx_dbgmcu.h"
#include "stm32f0xx_dma.h" #include "stm32f0xx_dma.h"
#include "stm32f0xx_exti.h" #include "stm32f0xx_exti.h"
@ -73,7 +73,7 @@
*/ */
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */ /* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line); void assert_failed(uint8_t *file, uint32_t line);
#else #else
#define assert_param(expr) ((void)0) #define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */ #endif /* USE_FULL_ASSERT */

4
flight/pios/stm32f0x/pios_delay.c
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@ -60,7 +60,7 @@ int32_t PIOS_DELAY_Init(void)
// Stop timer // Stop timer
TIM_Cmd(TIM2, DISABLE); TIM_Cmd(TIM2, DISABLE);
// Configure timebase and internal clock // Configure timebase and internal clock
TIM_TimeBaseInit(TIM2, (TIM_TimeBaseInitTypeDef*)&timerInit); TIM_TimeBaseInit(TIM2, (TIM_TimeBaseInitTypeDef *)&timerInit);
TIM_InternalClockConfig(TIM2); TIM_InternalClockConfig(TIM2);
TIM_SetCounter(TIM2, 0); TIM_SetCounter(TIM2, 0);
TIM_Cmd(TIM2, ENABLE); TIM_Cmd(TIM2, ENABLE);
@ -164,7 +164,7 @@ uint32_t PIOS_DELAY_GetRaw()
*/ */
uint32_t PIOS_DELAY_DiffuS(uint32_t raw) uint32_t PIOS_DELAY_DiffuS(uint32_t raw)
{ {
uint32_t diff = - raw; uint32_t diff = -raw;
return diff; return diff;
} }

7
flight/pios/stm32f0x/pios_exti.c
View File

@ -98,7 +98,6 @@ uint8_t PIOS_EXTI_gpio_port_to_exti_source_port(GPIO_TypeDef *gpio_port)
case (uint32_t)GPIOE: return EXTI_PortSourceGPIOE; case (uint32_t)GPIOE: return EXTI_PortSourceGPIOE;
case (uint32_t)GPIOF: return EXTI_PortSourceGPIOF; case (uint32_t)GPIOF: return EXTI_PortSourceGPIOF;
} }
PIOS_Assert(0); PIOS_Assert(0);
@ -166,16 +165,16 @@ int32_t PIOS_EXTI_Init(const struct pios_exti_cfg *cfg)
pios_exti_line_to_cfg_map[line_index] = cfg_index; pios_exti_line_to_cfg_map[line_index] = cfg_index;
/* Initialize the GPIO pin */ /* Initialize the GPIO pin */
GPIO_Init(cfg->pin.gpio,(GPIO_InitTypeDef*) &cfg->pin.init); GPIO_Init(cfg->pin.gpio, (GPIO_InitTypeDef *)&cfg->pin.init);
/* Set up the EXTI interrupt source */ /* Set up the EXTI interrupt source */
uint8_t exti_source_port = PIOS_EXTI_gpio_port_to_exti_source_port(cfg->pin.gpio); uint8_t exti_source_port = PIOS_EXTI_gpio_port_to_exti_source_port(cfg->pin.gpio);
uint8_t exti_source_pin = PIOS_EXTI_gpio_pin_to_exti_source_pin(cfg->pin.init.GPIO_Pin); uint8_t exti_source_pin = PIOS_EXTI_gpio_pin_to_exti_source_pin(cfg->pin.init.GPIO_Pin);
SYSCFG_EXTILineConfig(exti_source_port, exti_source_pin); SYSCFG_EXTILineConfig(exti_source_port, exti_source_pin);
EXTI_Init((EXTI_InitTypeDef*)&cfg->exti.init); EXTI_Init((EXTI_InitTypeDef *)&cfg->exti.init);
/* Enable the interrupt channel */ /* Enable the interrupt channel */
NVIC_Init((NVIC_InitTypeDef*)&cfg->irq.init); NVIC_Init((NVIC_InitTypeDef *)&cfg->irq.init);
return 0; return 0;

5
flight/pios/stm32f0x/pios_gpio.c
View File

@ -65,7 +65,7 @@ int32_t PIOS_GPIO_Init(uint32_t *gpios_dev_id, const struct pios_gpio_cfg *cfg)
GPIO_PinAFConfig(gpio->pin.gpio, gpio->pin.init.GPIO_Pin, gpio->remap); GPIO_PinAFConfig(gpio->pin.gpio, gpio->pin.init.GPIO_Pin, gpio->remap);
} }
GPIO_Init(gpio->pin.gpio, (GPIO_InitTypeDef*)&gpio->pin.init); GPIO_Init(gpio->pin.gpio, (GPIO_InitTypeDef *)&gpio->pin.init);
PIOS_GPIO_Off(*gpios_dev_id, i); PIOS_GPIO_Off(*gpios_dev_id, i);
} }
@ -138,12 +138,11 @@ void PIOS_GPIO_Toggle(uint32_t gpios_dev_id, uint8_t gpio_id)
const struct pios_gpio *gpio = &(gpio_cfg->gpios[gpio_id]); const struct pios_gpio *gpio = &(gpio_cfg->gpios[gpio_id]);
if (((gpio->pin.gpio->ODR & gpio->pin.init.GPIO_Pin) != 0) ^ gpio->active_low ) { if (((gpio->pin.gpio->ODR & gpio->pin.init.GPIO_Pin) != 0) ^ gpio->active_low) {
PIOS_GPIO_Off(gpios_dev_id, gpio_id); PIOS_GPIO_Off(gpios_dev_id, gpio_id);
} else { } else {
PIOS_GPIO_On(gpios_dev_id, gpio_id); PIOS_GPIO_On(gpios_dev_id, gpio_id);
} }
} }
#endif /* PIOS_INCLUDE_GPIO */ #endif /* PIOS_INCLUDE_GPIO */

2
flight/pios/stm32f0x/pios_spi.c
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@ -571,7 +571,7 @@ static int32_t SPI_DMA_TransferBlock(uint32_t spi_id, const uint8_t *send_buffer
SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE); SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
} }
//TODO: Verify the LDMA_TX and LDMA_RX handling then len is not a multiple of two!! // TODO: Verify the LDMA_TX and LDMA_RX handling then len is not a multiple of two!!
/* Start DMA transfers */ /* Start DMA transfers */
DMA_Cmd(spi_dev->cfg->dma.rx.channel, ENABLE); DMA_Cmd(spi_dev->cfg->dma.rx.channel, ENABLE);

13
flight/pios/stm32f0x/pios_sys.c
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@ -92,7 +92,7 @@ void PIOS_SYS_Init(void)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_13 | GPIO_Pin_14 ); // leave SWD pins alone GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_13 | GPIO_Pin_14); // leave SWD pins alone
GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
@ -100,7 +100,6 @@ void PIOS_SYS_Init(void)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
GPIO_Init(GPIOC, &GPIO_InitStructure); GPIO_Init(GPIOC, &GPIO_InitStructure);
} }
/** /**
@ -210,8 +209,7 @@ void NVIC_Configuration(void)
/* Copy the vector table from the Flash (mapped at the base of the application /* Copy the vector table from the Flash (mapped at the base of the application
load address 0x0800X000) to the base address of the SRAM at 0x20000000. */ load address 0x0800X000) to the base address of the SRAM at 0x20000000. */
for(uint32_t i = 0; i < 48; i++) for (uint32_t i = 0; i < 48; i++) {
{
VectorTable[i] = romTable[i]; VectorTable[i] = romTable[i];
} }
@ -285,10 +283,9 @@ void UsageFault_Handler(void)
stopHandler(); stopHandler();
} }
void stopHandler(){ void stopHandler()
while (1) {
{ while (1) {}
}
} }
#endif /* PIOS_INCLUDE_SYS */ #endif /* PIOS_INCLUDE_SYS */

8
flight/pios/stm32f0x/pios_usart.c
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@ -162,8 +162,8 @@ int32_t PIOS_USART_Init(uint32_t *usart_id, const struct pios_usart_cfg *cfg)
} }
/* Initialize the USART Rx and Tx pins */ /* Initialize the USART Rx and Tx pins */
GPIO_Init(usart_dev->cfg->rx.gpio, (GPIO_InitTypeDef*)&usart_dev->cfg->rx.init); GPIO_Init(usart_dev->cfg->rx.gpio, (GPIO_InitTypeDef *)&usart_dev->cfg->rx.init);
GPIO_Init(usart_dev->cfg->tx.gpio, (GPIO_InitTypeDef*)&usart_dev->cfg->tx.init); GPIO_Init(usart_dev->cfg->tx.gpio, (GPIO_InitTypeDef *)&usart_dev->cfg->tx.init);
/* Enable USART clock */ /* Enable USART clock */
switch ((uint32_t)usart_dev->cfg->regs) { switch ((uint32_t)usart_dev->cfg->regs) {
@ -179,7 +179,7 @@ int32_t PIOS_USART_Init(uint32_t *usart_id, const struct pios_usart_cfg *cfg)
} }
/* Configure the USART */ /* Configure the USART */
USART_Init(usart_dev->cfg->regs, (USART_InitTypeDef*)&usart_dev->cfg->init); USART_Init(usart_dev->cfg->regs, (USART_InitTypeDef *)&usart_dev->cfg->init);
*usart_id = (uint32_t)usart_dev; *usart_id = (uint32_t)usart_dev;
@ -195,7 +195,7 @@ int32_t PIOS_USART_Init(uint32_t *usart_id, const struct pios_usart_cfg *cfg)
PIOS_USART_3_id = (uint32_t)usart_dev; PIOS_USART_3_id = (uint32_t)usart_dev;
break; break;
} }
NVIC_Init((NVIC_InitTypeDef*)&usart_dev->cfg->irq.init); NVIC_Init((NVIC_InitTypeDef *)&usart_dev->cfg->irq.init);
USART_ITConfig(usart_dev->cfg->regs, USART_IT_RXNE, ENABLE); USART_ITConfig(usart_dev->cfg->regs, USART_IT_RXNE, ENABLE);
USART_ITConfig(usart_dev->cfg->regs, USART_IT_TXE, ENABLE); USART_ITConfig(usart_dev->cfg->regs, USART_IT_TXE, ENABLE);

6
flight/uavobjects/uavobjectmanager.c
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@ -893,11 +893,13 @@ int32_t UAVObjDelete(UAVObjHandle obj_handle, uint16_t instId)
} }
#else // PIOS_INCLUDE_FLASH #else // PIOS_INCLUDE_FLASH
int32_t UAVObjSave(__attribute__((unused)) UAVObjHandle obj_handle, __attribute__((unused)) uint16_t instId){ int32_t UAVObjSave(__attribute__((unused)) UAVObjHandle obj_handle, __attribute__((unused)) uint16_t instId)
{
return 0; return 0;
} }
int32_t UAVObjLoad(__attribute__((unused)) UAVObjHandle obj_handle, __attribute__((unused)) uint16_t instId){ int32_t UAVObjLoad(__attribute__((unused)) UAVObjHandle obj_handle, __attribute__((unused)) uint16_t instId)
{
return 0; return 0;
} }