mirror of
https://bitbucket.org/librepilot/librepilot.git
synced 2025-01-30 15:52:12 +01:00
LP-512 Build system changed; ld scripts cleanup
This commit is contained in:
Vladimir Zidar
parent
565014d560
commit
bd7641e857
@ -152,6 +152,14 @@ ifdef USER_EE_BANK_BASE
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BOARD_CDEFS += -DUSER_EE_BANK_BASE=$(USER_EE_BANK_BASE)
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BOARD_CDEFS += -DUSER_EE_BANK_SIZE=$(USER_EE_BANK_SIZE)
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endif
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ifdef SRAM_BANK_BASE
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BOARD_CDEFS += -DSRAM_BANK_BASE=$(SRAM_BANK_BASE)
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BOARD_CDEFS += -DSRAM_BANK_SIZE=$(SRAM_BANK_SIZE)
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endif
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ifdef CCSRAM_BANK_BASE
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BOARD_CDEFS += -DCCSRAM_BANK_BASE=$(CCSRAM_BANK_BASE)
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BOARD_CDEFS += -DCCSRAM_BANK_SIZE=$(CCSRAM_BANK_SIZE)
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endif
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CDEFS += $(BOARD_CDEFS)
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ifeq ($(DEBUG), YES)
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@ -214,6 +222,8 @@ ALLSRCBASE = $(notdir $(basename $(ALLSRC)))
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# Define all object files.
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ALLOBJ = $(addprefix $(OUTDIR)/, $(addsuffix .o, $(ALLSRCBASE))) $(EXTRAOBJ)
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ALLLD = $(addprefix $(OUTDIR)/, $(addsuffix .ld, $(notdir $(basename $(LDSRC)))))
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# Define all listing files (used for make clean).
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LSTFILES = $(addprefix $(OUTDIR)/, $(addsuffix .lst, $(ALLSRCBASE)))
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# Define all depedency-files (used for make clean).
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@ -241,9 +251,9 @@ endif
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# Link: create ELF output file from object files.
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ifeq ($(USE_CXX), YES)
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$(eval $(call LINK_CXX_TEMPLATE,$(OUTDIR)/$(TARGET).elf,$(ALLOBJ),$(ALLLIB)))
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$(eval $(call LINK_CXX_TEMPLATE,$(OUTDIR)/$(TARGET).elf,$(ALLOBJ),$(ALLLIB),$(ALLLD)))
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else
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$(eval $(call LINK_TEMPLATE,$(OUTDIR)/$(TARGET).elf,$(ALLOBJ),$(ALLLIB)))
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$(eval $(call LINK_TEMPLATE,$(OUTDIR)/$(TARGET).elf,$(ALLOBJ),$(ALLLIB),$(ALLLD)))
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endif
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# Assemble: create object files from assembler source files.
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@ -272,6 +282,9 @@ $(eval $(call PARTIAL_COMPILE_TEMPLATE,SRC))
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# Compile: create assembler files from C source files. ARM only
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$(eval $(call PARTIAL_COMPILE_ARM_TEMPLATE,SRCARM))
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# Preprocess: create linker scripts from .lds files.
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$(foreach src, $(LDSRC), $(eval $(call PREPROCESS_LDS_TEMPLATE,$(src))))
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# Add opfw target
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$(eval $(call OPFW_TEMPLATE,$(OUTDIR)/$(TARGET).bin,$(BOARD_TYPE),$(BOARD_REVISION)))
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@ -41,32 +41,33 @@ else
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endif
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# Define Messages
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MSG_FORMATERROR = $(QUOTE) Can not handle output-format$(QUOTE)
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MSG_MODINIT = $(QUOTE) MODINIT $(MSG_EXTRA) $(QUOTE)
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MSG_SIZE = $(QUOTE) SIZE $(MSG_EXTRA) $(QUOTE)
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MSG_LOAD_FILE = $(QUOTE) BIN/HEX $(MSG_EXTRA) $(QUOTE)
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MSG_BIN_OBJ = $(QUOTE) BINO $(MSG_EXTRA) $(QUOTE)
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MSG_STRIP_FILE = $(QUOTE) STRIP $(MSG_EXTRA) $(QUOTE)
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MSG_EXTENDED_LISTING = $(QUOTE) LIS $(MSG_EXTRA) $(QUOTE)
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MSG_SYMBOL_TABLE = $(QUOTE) NM $(MSG_EXTRA) $(QUOTE)
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MSG_ARCHIVING = $(QUOTE) AR $(MSG_EXTRA) $(QUOTE)
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MSG_LINKING = $(QUOTE) LD $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILING = $(QUOTE) CC $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILING_ARM = $(QUOTE) CC-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILINGCXX = $(QUOTE) CXX $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILINGCXX_ARM = $(QUOTE) CXX-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_ASSEMBLING = $(QUOTE) AS $(MSG_EXTRA) $(QUOTE)
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MSG_ASSEMBLING_ARM = $(QUOTE) AS-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_CLEANING = $(QUOTE) CLEAN $(MSG_EXTRA) $(QUOTE)
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MSG_ASMFROMC = $(QUOTE) AS(C) $(MSG_EXTRA) $(QUOTE)
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MSG_ASMFROMC_ARM = $(QUOTE) AS(C)-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_PYMITEINIT = $(QUOTE) PY $(MSG_EXTRA) $(QUOTE)
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MSG_OPFIRMWARE = $(QUOTE) OPFW $(MSG_EXTRA) $(QUOTE)
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MSG_FWINFO = $(QUOTE) FWINFO $(MSG_EXTRA) $(QUOTE)
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MSG_JTAG_PROGRAM = $(QUOTE) JTAG-PGM $(MSG_EXTRA) $(QUOTE)
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MSG_JTAG_WIPE = $(QUOTE) JTAG-WIPE $(MSG_EXTRA) $(QUOTE)
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MSG_PADDING = $(QUOTE) PADDING $(MSG_EXTRA) $(QUOTE)
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MSG_FLASH_IMG = $(QUOTE) FLASH_IMG $(MSG_EXTRA) $(QUOTE)
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MSG_FORMATERROR = $(QUOTE) Can not handle output-format$(QUOTE)
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MSG_MODINIT = $(QUOTE) MODINIT $(MSG_EXTRA) $(QUOTE)
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MSG_SIZE = $(QUOTE) SIZE $(MSG_EXTRA) $(QUOTE)
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MSG_LOAD_FILE = $(QUOTE) BIN/HEX $(MSG_EXTRA) $(QUOTE)
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MSG_BIN_OBJ = $(QUOTE) BINO $(MSG_EXTRA) $(QUOTE)
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MSG_STRIP_FILE = $(QUOTE) STRIP $(MSG_EXTRA) $(QUOTE)
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MSG_EXTENDED_LISTING = $(QUOTE) LIS $(MSG_EXTRA) $(QUOTE)
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MSG_SYMBOL_TABLE = $(QUOTE) NM $(MSG_EXTRA) $(QUOTE)
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MSG_ARCHIVING = $(QUOTE) AR $(MSG_EXTRA) $(QUOTE)
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MSG_LINKING = $(QUOTE) LD $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILING = $(QUOTE) CC $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILING_ARM = $(QUOTE) CC-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILINGCXX = $(QUOTE) CXX $(MSG_EXTRA) $(QUOTE)
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MSG_COMPILINGCXX_ARM = $(QUOTE) CXX-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_ASSEMBLING = $(QUOTE) AS $(MSG_EXTRA) $(QUOTE)
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MSG_ASSEMBLING_ARM = $(QUOTE) AS-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_CLEANING = $(QUOTE) CLEAN $(MSG_EXTRA) $(QUOTE)
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MSG_ASMFROMC = $(QUOTE) AS(C) $(MSG_EXTRA) $(QUOTE)
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MSG_ASMFROMC_ARM = $(QUOTE) AS(C)-ARM $(MSG_EXTRA) $(QUOTE)
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MSG_PYMITEINIT = $(QUOTE) PY $(MSG_EXTRA) $(QUOTE)
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MSG_OPFIRMWARE = $(QUOTE) OPFW $(MSG_EXTRA) $(QUOTE)
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MSG_FWINFO = $(QUOTE) FWINFO $(MSG_EXTRA) $(QUOTE)
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MSG_JTAG_PROGRAM = $(QUOTE) JTAG-PGM $(MSG_EXTRA) $(QUOTE)
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MSG_JTAG_WIPE = $(QUOTE) JTAG-WIPE $(MSG_EXTRA) $(QUOTE)
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MSG_PADDING = $(QUOTE) PADDING $(MSG_EXTRA) $(QUOTE)
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MSG_FLASH_IMG = $(QUOTE) FLASH_IMG $(MSG_EXTRA) $(QUOTE)
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MSG_PREPROCESSING_LDS = $(QUOTE) PP $(MSG_EXTRA) $(QUOTE)
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# Function for converting an absolute path to one relative
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# to the top of the source tree.
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@ -175,6 +176,13 @@ $(OUTDIR)/$(notdir $(basename $(1))).o : $(1)
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$(V1) $(CC) -c $(THUMB) $$(CFLAGS) $$(CONLYFLAGS) $$(CPPFLAGS) $$< -o $$@
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endef
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# Preprocess: create linker scripts from .lds files.
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define PREPROCESS_LDS_TEMPLATE
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$(OUTDIR)/$(notdir $(basename $(1))).ld : $(1)
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@echo $(MSG_PREPROCESSING_LDS) $$(call toprel, $$<)
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$(V1) $(CXX) -E -P -x c $(THUMB) $$(CFLAGS) $$(CPPFLAGS) $$< -o $$@
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endef
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# Compile: create object files from C source files. ARM-only
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define COMPILE_C_ARM_TEMPLATE
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$(OUTDIR)/$(notdir $(basename $(1))).o : $(1)
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@ -224,13 +232,16 @@ endef
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# $1 = elf file to produce
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# $2 = list of object files that make up the elf file
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# $3 = optional list of libraries to build and link
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# $4 = optional list of linker scripts to build and link
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define LINK_TEMPLATE
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.SECONDARY : $(1)
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.PRECIOUS : $(2) $(3)
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$(1).input_files: $(2) $(3)
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.PRECIOUS : $(2) $(3) $(4)
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$(1).input_files: $(2) $(3) $(4)
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$(V1) rm -rf $(1).input_files
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$(foreach file,$(2) $(3),
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$(V1) echo $(file) >> $$@)
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$(foreach file,$(4),
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$(V1) echo -T$(file) >> $$@)
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$(1): $(1).input_files
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@echo $(MSG_LINKING) $$(call toprel, $$@)
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@ -240,13 +251,17 @@ endef
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# Link: create ELF output file from object files.
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# $1 = elf file to produce
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# $2 = list of object files that make up the elf file
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# $3 = optional list of libraries to build and link
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# $4 = optional list of linker scripts to build and link
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define LINK_CXX_TEMPLATE
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.SECONDARY : $(1)
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.PRECIOUS : $(2) $(3)
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$(1).input_files: $(2) $(3)
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.PRECIOUS : $(2) $(3) $(4)
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$(1).input_files: $(2) $(3) $(4)
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$(V1) rm -rf $(1).input_files
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$(foreach file,$(2) $(3),
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$(V1) echo $(file) >> $$@)
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$(foreach file,$(4),
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$(V1) echo -T$(file) >> $$@)
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$(1): $(1).input_files
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@echo $(MSG_LINKING) $$(call toprel, $$@)
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@ -7,14 +7,7 @@ PIOS_DEVLIB := $(dir $(lastword $(MAKEFILE_LIST)))
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USE_USB ?= YES
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# Hardcoded linker script names for now
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LINKER_SCRIPTS_APP = $(OPSYSTEM)/memory.ld \
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$(OPSYSTEM)/../common/sections.ld
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LINKER_SCRIPTS_BL = $(OPSYSTEM)/memory.ld \
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$(OPSYSTEM)/../common/sections.ld
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# _compat linker script are aimed at bootloader updater to guarantee to be compatible with earlier bootloaders.
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LINKER_SCRIPTS_COMPAT = $(PIOS_DEVLIB)link_$(BOARD)_fw_memory.ld \
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$(PIOS_DEVLIB)link_$(BOARD)_sections_compat.ld
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LDSRC = $(PIOS_DEVLIB)link_memory.lds $(PIOS_DEVLIB)link_sections.lds
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CDEFS += -D$(CHIP) -DSTM32F3
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CDEFS += -DHSE_VALUE=$(OSCILLATOR_FREQ)
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@ -38,7 +31,6 @@ EXTRAINCDIRS += $(PIOS_DEVLIB)inc
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# CMSIS for the F3
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include $(PIOSCOMMON)/libraries/CMSIS/library.mk
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CMSIS_DEVICEDIR := $(PIOS_DEVLIB)libraries/CMSIS3/Device/ST/STM32F30x
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SRC += $(OPSYSTEM)/../common/system.c
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EXTRAINCDIRS += $(CMSIS_DEVICEDIR)/Include
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# ST Peripheral library
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@ -1,7 +0,0 @@
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x004000 - 0x000080
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BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
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SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x009000
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CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
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}
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@ -1,8 +0,0 @@
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MEMORY
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{
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BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
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RSVD (rx) : ORIGIN = 0x08004000, LENGTH = 0x00C000 - 0x004000
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FLASH (rx) : ORIGIN = 0x0800C000, LENGTH = 0x034000
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SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00A000
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CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
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}
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@ -1,197 +0,0 @@
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/* Section Definitions */
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SECTIONS
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{
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/*
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* Vectors, code and constant data.
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*/
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.text :
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{
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PROVIDE (pios_isr_vector_table_base = .);
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KEEP(*(.cpu_vectors)) /* CPU exception vectors */
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KEEP(*(.io_vectors)) /* I/O interrupt vectors */
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*(.text .text.* .gnu.linkonce.t.*)
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*(.glue_7t) *(.glue_7)
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*(.rodata .rodata* .gnu.linkonce.r.*)
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} > FLASH
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/*
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* Init section for UAVObjects.
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*/
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.initcalluavobj.init :
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{
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. = ALIGN(4);
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__uavobj_initcall_start = .;
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KEEP(*(.initcalluavobj.init))
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. = ALIGN(4);
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__uavobj_initcall_end = .;
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} >FLASH
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/*
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* Module init section section
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*/
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.initcallmodule.init :
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{
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. = ALIGN(4);
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__module_initcall_start = .;
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KEEP(*(.initcallmodule.init))
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. = ALIGN(4);
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__module_initcall_end = .;
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} >FLASH
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/*
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* C++ exception handling.
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*/
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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.ARM.exidx :
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{
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} > FLASH
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|
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/*
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* Markers for the end of the 'text' section and the in-flash start of
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* non-constant data
|
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*/
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. = ALIGN(4);
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_etext = .;
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_sidata = .;
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|
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/*
|
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* Board info structure, normally only generated by the bootloader but can
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* be read by the application.
|
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*/
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PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
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.boardinfo :
|
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{
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. = ALIGN(4);
|
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KEEP(*(.boardinfo))
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. = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO));
|
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} > BD_INFO
|
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|
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/*
|
||||
* Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow
|
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* results in a hard fault.
|
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*/
|
||||
.istack (NOLOAD) :
|
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{
|
||||
. = ALIGN(4);
|
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_irq_stack_end = . ;
|
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*(.irqstack)
|
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_irq_stack_top = . ;
|
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} > CCSRAM
|
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|
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|
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/*
|
||||
* Non-const initialised data.
|
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*/
|
||||
.data : AT (_sidata)
|
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{
|
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. = ALIGN(4);
|
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_sdata = .;
|
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*(.data .data.*)
|
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. = ALIGN(4);
|
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_edata = . ;
|
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} > SRAM
|
||||
|
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/*
|
||||
* Uninitialised data (BSS + commons).
|
||||
*/
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_sbss = . ;
|
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*(SORT_BY_ALIGNMENT(.bss*))
|
||||
*(COMMON)
|
||||
_ebss = . ;
|
||||
PROVIDE ( _end = _ebss ) ;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* The heap consumes the remainder of the SRAM.
|
||||
*/
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sheap = . ;
|
||||
|
||||
/*
|
||||
* This allows us to declare an object or objects up to the minimum acceptable
|
||||
* heap size and receive a linker error if the space available for the heap is
|
||||
* not sufficient.
|
||||
*/
|
||||
*(.heap)
|
||||
|
||||
/* extend the heap up to the top of SRAM */
|
||||
. = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap);
|
||||
_eheap = .;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* 'Fast' memory goes in the CCM SRAM
|
||||
*/
|
||||
.fast (NOLOAD) :
|
||||
{
|
||||
_sfast = . ;
|
||||
*(.fast)
|
||||
_efast = . ;
|
||||
} > CCSRAM
|
||||
|
||||
/*
|
||||
* The fastheap consumes the remainder of the CCSRAM.
|
||||
*/
|
||||
.fastheap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfastheap = . ;
|
||||
|
||||
/*
|
||||
* This allows us to declare an object or objects up to the minimum acceptable
|
||||
* heap size and receive a linker error if the space available for the heap is
|
||||
* not sufficient.
|
||||
*/
|
||||
*(.fastheap)
|
||||
|
||||
/* extend the heap up to the top of SRAM */
|
||||
. = ORIGIN(CCSRAM) + LENGTH(CCSRAM) - ABSOLUTE(_sfastheap);
|
||||
_efastheap = .;
|
||||
} > CCSRAM
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
26
flight/pios/stm32f30x/link_memory.lds
Normal file
26
flight/pios/stm32f30x/link_memory.lds
Normal file
@ -0,0 +1,26 @@
|
||||
#define SRAM_BANK_BASE 0x20000000
|
||||
#define CCSRAM_BANK_BASE 0x10000000
|
||||
|
||||
#ifdef STM32F303xC
|
||||
# define SRAM_BANK_SIZE 0x009000
|
||||
# define CCSRAM_BANK_SIZE 0x002000
|
||||
#endif
|
||||
#ifdef STM32F303xE
|
||||
# define SRAM_BANK_SIZE 0x00A000
|
||||
# define CCSRAM_BANK_SIZE 0x002000
|
||||
#endif
|
||||
|
||||
MEMORY
|
||||
{
|
||||
BD_INFO (r) : ORIGIN = (BL_BANK_BASE + BL_BANK_SIZE) - 0x80, LENGTH = 0x000080
|
||||
#ifdef EE_BANK_BASE
|
||||
EE_BANK (rx) : ORIGIN = EE_BANK_BASE, LENGTH = EE_BANK_SIZE
|
||||
#endif /* EE_BANK_BASE */
|
||||
#ifdef BOOTLOADER
|
||||
FLASH (rx) : ORIGIN = BL_BANK_BASE, LENGTH = BL_BANK_SIZE
|
||||
#else
|
||||
FLASH (rx) : ORIGIN = FW_BANK_BASE, LENGTH = FW_BANK_SIZE
|
||||
#endif
|
||||
SRAM (rwx) : ORIGIN = SRAM_BANK_BASE, LENGTH = SRAM_BANK_SIZE
|
||||
CCSRAM (rw) : ORIGIN = CCSRAM_BANK_BASE, LENGTH = CCSRAM_BANK_SIZE
|
||||
}
|
||||
@ -1,4 +1,3 @@
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
@ -2,8 +2,8 @@
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 27-February-2015
|
||||
* @version V1.0.0
|
||||
* @date 04-September-2012
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F30x devices,
|
||||
* and is generated by the clock configuration tool
|
||||
@ -71,7 +71,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
@ -105,7 +105,13 @@
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/** @addtogroup STM32F30x_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Defines
|
||||
* @{
|
||||
@ -119,7 +125,13 @@
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @addtogroup STM32F30x_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Variables
|
||||
* @{
|
||||
@ -291,7 +303,11 @@ static void SetSysClock(void)
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
|
||||
/* Enable HSE */
|
||||
#ifdef PIOS_RCC_HSE_BYPASS
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
|
||||
#else
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
#endif /* PIOS_HSE_BYPASS */
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do {
|
||||
@ -1,7 +0,0 @@
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x004000 - 0x000080
|
||||
BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
|
||||
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x009000
|
||||
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
|
||||
}
|
||||
@ -1,197 +0,0 @@
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* Vectors, code and constant data.
|
||||
*/
|
||||
.text :
|
||||
{
|
||||
PROVIDE (pios_isr_vector_table_base = .);
|
||||
KEEP(*(.cpu_vectors)) /* CPU exception vectors */
|
||||
KEEP(*(.io_vectors)) /* I/O interrupt vectors */
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
} > FLASH
|
||||
|
||||
/*
|
||||
* Init section for UAVObjects.
|
||||
*/
|
||||
.initcalluavobj.init :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__uavobj_initcall_start = .;
|
||||
KEEP(*(.initcalluavobj.init))
|
||||
. = ALIGN(4);
|
||||
__uavobj_initcall_end = .;
|
||||
} >FLASH
|
||||
|
||||
/*
|
||||
* Module init section section
|
||||
*/
|
||||
.initcallmodule.init :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__module_initcall_start = .;
|
||||
KEEP(*(.initcallmodule.init))
|
||||
. = ALIGN(4);
|
||||
__module_initcall_end = .;
|
||||
} >FLASH
|
||||
|
||||
|
||||
/*
|
||||
* C++ exception handling.
|
||||
*/
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
/*
|
||||
* Markers for the end of the 'text' section and the in-flash start of
|
||||
* non-constant data
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
_sidata = .;
|
||||
|
||||
/*
|
||||
* Board info structure, normally only generated by the bootloader but can
|
||||
* be read by the application.
|
||||
*/
|
||||
PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
|
||||
.boardinfo :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.boardinfo))
|
||||
. = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO));
|
||||
} > BD_INFO
|
||||
|
||||
/*
|
||||
* Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow
|
||||
* results in a hard fault.
|
||||
*/
|
||||
.istack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_irq_stack_end = . ;
|
||||
*(.irqstack)
|
||||
_irq_stack_top = . ;
|
||||
} > CCSRAM
|
||||
|
||||
|
||||
/*
|
||||
* Non-const initialised data.
|
||||
*/
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .;
|
||||
*(.data .data.*)
|
||||
. = ALIGN(4);
|
||||
_edata = . ;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* Uninitialised data (BSS + commons).
|
||||
*/
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_sbss = . ;
|
||||
*(SORT_BY_ALIGNMENT(.bss*))
|
||||
*(COMMON)
|
||||
_ebss = . ;
|
||||
PROVIDE ( _end = _ebss ) ;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* The heap consumes the remainder of the SRAM.
|
||||
*/
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sheap = . ;
|
||||
|
||||
/*
|
||||
* This allows us to declare an object or objects up to the minimum acceptable
|
||||
* heap size and receive a linker error if the space available for the heap is
|
||||
* not sufficient.
|
||||
*/
|
||||
*(.heap)
|
||||
|
||||
/* extend the heap up to the top of SRAM */
|
||||
. = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap);
|
||||
_eheap = .;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* 'Fast' memory goes in the CCM SRAM
|
||||
*/
|
||||
.fast (NOLOAD) :
|
||||
{
|
||||
_sfast = . ;
|
||||
*(.fast)
|
||||
_efast = . ;
|
||||
} > CCSRAM
|
||||
|
||||
/*
|
||||
* The fastheap consumes the remainder of the CCSRAM.
|
||||
*/
|
||||
.fastheap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfastheap = . ;
|
||||
|
||||
/*
|
||||
* This allows us to declare an object or objects up to the minimum acceptable
|
||||
* heap size and receive a linker error if the space available for the heap is
|
||||
* not sufficient.
|
||||
*/
|
||||
*(.fastheap)
|
||||
|
||||
/* extend the heap up to the top of SRAM */
|
||||
. = ORIGIN(CCSRAM) + LENGTH(CCSRAM) - ABSOLUTE(_sfastheap);
|
||||
_efastheap = .;
|
||||
} > CCSRAM
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
@ -1,370 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 27-February-2015
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F30x devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f30x_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f30x.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f30x.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* Supported STM32F30x device
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 72000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 72000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 8000000
|
||||
*----------------------------------------------------------------------------
|
||||
* PLLMUL | 9
|
||||
*-----------------------------------------------------------------------------
|
||||
* PREDIV | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB Clock | DISABLE
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f30x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 72000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR &= 0xF87FC00C;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
|
||||
RCC->CFGR &= (uint32_t)0xFF80FFFF;
|
||||
|
||||
/* Reset PREDIV1[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||
|
||||
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer and set Flash Latency */
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
/* PCLK1 = HCLK / 2 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
||||
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
MEMORY
|
||||
{
|
||||
BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
|
||||
EE_BANK (rx) : ORIGIN = 0x08004000, LENGTH = 0x008000
|
||||
FLASH (rx) : ORIGIN = 0x0800C000, LENGTH = 0x034000
|
||||
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00A000
|
||||
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
|
||||
}
|
||||
@ -1,7 +0,0 @@
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x004000 - 0x000080
|
||||
BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
|
||||
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x009000
|
||||
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
|
||||
}
|
||||
@ -1,197 +0,0 @@
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* Vectors, code and constant data.
|
||||
*/
|
||||
.text :
|
||||
{
|
||||
PROVIDE (pios_isr_vector_table_base = .);
|
||||
KEEP(*(.cpu_vectors)) /* CPU exception vectors */
|
||||
KEEP(*(.io_vectors)) /* I/O interrupt vectors */
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
} > FLASH
|
||||
|
||||
/*
|
||||
* Init section for UAVObjects.
|
||||
*/
|
||||
.initcalluavobj.init :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__uavobj_initcall_start = .;
|
||||
KEEP(*(.initcalluavobj.init))
|
||||
. = ALIGN(4);
|
||||
__uavobj_initcall_end = .;
|
||||
} >FLASH
|
||||
|
||||
/*
|
||||
* Module init section section
|
||||
*/
|
||||
.initcallmodule.init :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__module_initcall_start = .;
|
||||
KEEP(*(.initcallmodule.init))
|
||||
. = ALIGN(4);
|
||||
__module_initcall_end = .;
|
||||
} >FLASH
|
||||
|
||||
|
||||
/*
|
||||
* C++ exception handling.
|
||||
*/
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
/*
|
||||
* Markers for the end of the 'text' section and the in-flash start of
|
||||
* non-constant data
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
_sidata = .;
|
||||
|
||||
/*
|
||||
* Board info structure, normally only generated by the bootloader but can
|
||||
* be read by the application.
|
||||
*/
|
||||
PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
|
||||
.boardinfo :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.boardinfo))
|
||||
. = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO));
|
||||
} > BD_INFO
|
||||
|
||||
/*
|
||||
* Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow
|
||||
* results in a hard fault.
|
||||
*/
|
||||
.istack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_irq_stack_end = . ;
|
||||
*(.irqstack)
|
||||
_irq_stack_top = . ;
|
||||
} > CCSRAM
|
||||
|
||||
|
||||
/*
|
||||
* Non-const initialised data.
|
||||
*/
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .;
|
||||
*(.data .data.*)
|
||||
. = ALIGN(4);
|
||||
_edata = . ;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* Uninitialised data (BSS + commons).
|
||||
*/
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_sbss = . ;
|
||||
*(SORT_BY_ALIGNMENT(.bss*))
|
||||
*(COMMON)
|
||||
_ebss = . ;
|
||||
PROVIDE ( _end = _ebss ) ;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* The heap consumes the remainder of the SRAM.
|
||||
*/
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sheap = . ;
|
||||
|
||||
/*
|
||||
* This allows us to declare an object or objects up to the minimum acceptable
|
||||
* heap size and receive a linker error if the space available for the heap is
|
||||
* not sufficient.
|
||||
*/
|
||||
*(.heap)
|
||||
|
||||
/* extend the heap up to the top of SRAM */
|
||||
. = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap);
|
||||
_eheap = .;
|
||||
} > SRAM
|
||||
|
||||
/*
|
||||
* 'Fast' memory goes in the CCM SRAM
|
||||
*/
|
||||
.fast (NOLOAD) :
|
||||
{
|
||||
_sfast = . ;
|
||||
*(.fast)
|
||||
_efast = . ;
|
||||
} > CCSRAM
|
||||
|
||||
/*
|
||||
* The fastheap consumes the remainder of the CCSRAM.
|
||||
*/
|
||||
.fastheap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfastheap = . ;
|
||||
|
||||
/*
|
||||
* This allows us to declare an object or objects up to the minimum acceptable
|
||||
* heap size and receive a linker error if the space available for the heap is
|
||||
* not sufficient.
|
||||
*/
|
||||
*(.fastheap)
|
||||
|
||||
/* extend the heap up to the top of SRAM */
|
||||
. = ORIGIN(CCSRAM) + LENGTH(CCSRAM) - ABSOLUTE(_sfastheap);
|
||||
_efastheap = .;
|
||||
} > CCSRAM
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
@ -1,7 +0,0 @@
|
||||
MEMORY
|
||||
{
|
||||
BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
|
||||
FLASH (rx) : ORIGIN = 0x08004000, LENGTH = 0x03C000
|
||||
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00A000
|
||||
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
|
||||
}
|
||||
@ -1,7 +0,0 @@
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x004000 - 0x000080
|
||||
BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
|
||||
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x009000
|
||||
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
|
||||
}
|
||||
@ -1,354 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 27-February-2015
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F30x devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f30x_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f30x.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f30x.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* Supported STM32F30x device
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 72000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 72000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 8000000
|
||||
*----------------------------------------------------------------------------
|
||||
* PLLMUL | 9
|
||||
*-----------------------------------------------------------------------------
|
||||
* PREDIV | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB Clock | DISABLE
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f30x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 72000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 };
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR &= 0xF87FC00C;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
|
||||
RCC->CFGR &= (uint32_t)0xFF80FFFF;
|
||||
|
||||
/* Reset PREDIV1[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||
|
||||
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp) {
|
||||
case 0x00: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = (pllmull >> 18) + 2;
|
||||
|
||||
if (pllsource == 0x00) {
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
} else {
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do {
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
} else {
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01) {
|
||||
/* Enable Prefetch Buffer and set Flash Latency */
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
/* PCLK1 = HCLK / 2 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
||||
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) {}
|
||||
} else { /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@ -1,8 +0,0 @@
|
||||
MEMORY
|
||||
{
|
||||
BD_INFO (r) : ORIGIN = 0x08004000 - 0x80, LENGTH = 0x000080
|
||||
EE_BANK (rx) : ORIGIN = 0x08004000, LENGTH = 0x008000
|
||||
FLASH (rx) : ORIGIN = 0x0800C000, LENGTH = 0x034000
|
||||
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00A000
|
||||
CCSRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x002000
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user