From c281420e252ca6b256b3ac7a3f87344e6d7ed8f1 Mon Sep 17 00:00:00 2001 From: Alessio Morale Date: Sat, 26 Apr 2014 22:14:47 +0200 Subject: [PATCH] OP-1307 Most(all?) F4Discovery has an "A" revision of STM32f4. Disable prefetch to overcome the "Section 2.1.1: ART Accelerator prefetch queue instruction is not supported" issue (DM00037591.pdf) --- .../ST/STM32F4xx/Source/discoveryf4bare/system_stm32f4xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flight/pios/stm32f4xx/libraries/CMSIS/Device/ST/STM32F4xx/Source/discoveryf4bare/system_stm32f4xx.c b/flight/pios/stm32f4xx/libraries/CMSIS/Device/ST/STM32F4xx/Source/discoveryf4bare/system_stm32f4xx.c index e6ffcd777..cbc36d6e3 100644 --- a/flight/pios/stm32f4xx/libraries/CMSIS/Device/ST/STM32F4xx/Source/discoveryf4bare/system_stm32f4xx.c +++ b/flight/pios/stm32f4xx/libraries/CMSIS/Device/ST/STM32F4xx/Source/discoveryf4bare/system_stm32f4xx.c @@ -398,7 +398,7 @@ static void SetSysClock(void) } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));