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OP-901 updated STM32 USB OTG Driver

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Alessio Morale 2013-04-13 19:49:37 +02:00
parent 1016b08b70
commit ccc24d844a
18 changed files with 1933 additions and 1337 deletions
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306
flight/PiOS/STM32F4xx/Libraries/STM32_USB_OTG_Driver/inc/usb_conf_template.h Normal file
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/**
******************************************************************************
* @file usb_conf.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief General low level driver configuration
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_CONF__H__
#define __USB_CONF__H__
/* Includes ------------------------------------------------------------------*/
#include "usb_conf.h"
/** @addtogroup USB_OTG_DRIVER
* @{
*/
/** @defgroup USB_CONF
* @brief USB low level driver configuration file
* @{
*/
/** @defgroup USB_CONF_Exported_Defines
* @{
*/
/* USB Core and PHY interface configuration.
Tip: To avoid modifying these defines each time you need to change the USB
configuration, you can declare the needed define in your toolchain
compiler preprocessor.
*/
/****************** USB OTG FS PHY CONFIGURATION *******************************
* The USB OTG FS Core supports one on-chip Full Speed PHY.
*
* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor
* when FS core is used.
*******************************************************************************/
#ifndef USE_USB_OTG_FS
//#define USE_USB_OTG_FS
#endif /* USE_USB_OTG_FS */
#ifdef USE_USB_OTG_FS
#define USB_OTG_FS_CORE
#endif
/****************** USB OTG HS PHY CONFIGURATION *******************************
* The USB OTG HS Core supports two PHY interfaces:
* (i) An ULPI interface for the external High Speed PHY: the USB HS Core will
* operate in High speed mode
* (ii) An on-chip Full Speed PHY: the USB HS Core will operate in Full speed mode
*
* You can select the PHY to be used using one of these two defines:
* (i) USE_ULPI_PHY: if the USB OTG HS Core is to be used in High speed mode
* (ii) USE_EMBEDDED_PHY: if the USB OTG HS Core is to be used in Full speed mode
*
* Notes:
* - The USE_ULPI_PHY symbol is defined in the project compiler preprocessor as
* default PHY when HS core is used.
* - On STM322xG-EVAL and STM324xG-EVAL boards, only configuration(i) is available.
* Configuration (ii) need a different hardware, for more details refer to your
* STM32 device datasheet.
*******************************************************************************/
#ifndef USE_USB_OTG_HS
//#define USE_USB_OTG_HS
#endif /* USE_USB_OTG_HS */
#ifndef USE_ULPI_PHY
//#define USE_ULPI_PHY
#endif /* USE_ULPI_PHY */
#ifndef USE_EMBEDDED_PHY
//#define USE_EMBEDDED_PHY
#endif /* USE_EMBEDDED_PHY */
#ifdef USE_USB_OTG_HS
#define USB_OTG_HS_CORE
#endif
/*******************************************************************************
* FIFO Size Configuration in Device mode
*
* (i) Receive data FIFO size = RAM for setup packets +
* OUT endpoint control information +
* data OUT packets + miscellaneous
* Space = ONE 32-bits words
* --> RAM for setup packets = 10 spaces
* (n is the nbr of CTRL EPs the device core supports)
* --> OUT EP CTRL info = 1 space
* (one space for status information written to the FIFO along with each
* received packet)
* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
* (MINIMUM to receive packets)
* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
* (if high-bandwidth EP is enabled or multiple isochronous EPs)
* --> miscellaneous = 1 space per OUT EP
* (one space for transfer complete status information also pushed to the
* FIFO with each endpoint's last packet)
*
* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
* that particular IN EP. More space allocated in the IN EP Tx FIFO results
* in a better performance on the USB and can hide latencies on the AHB.
*
* (iii) TXn min size = 16 words. (n : Transmit FIFO index)
* (iv) When a TxFIFO is not used, the Configuration should be as follows:
* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
* --> Txm can use the space allocated for Txn.
* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
* --> Txn should be configured with the minimum space of 16 words
* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top
* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
*******************************************************************************/
/*******************************************************************************
* FIFO Size Configuration in Host mode
*
* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or
* 2x (Largest Packet Size / 4) + 1, If a
* high-bandwidth channel or multiple isochronous
* channels are enabled
*
* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size
* for all supported nonperiodic OUT channels. Typically, a space
* corresponding to two Largest Packet Size is recommended.
*
* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is
* the largest maximum packet size for all supported periodic OUT channels.
* If there is at least one High Bandwidth Isochronous OUT endpoint,
* then the space must be at least two times the maximum packet size for
* that channel.
*******************************************************************************/
/****************** USB OTG HS CONFIGURATION **********************************/
#ifdef USB_OTG_HS_CORE
#define RX_FIFO_HS_SIZE 512
#define TX0_FIFO_HS_SIZE 512
#define TX1_FIFO_HS_SIZE 512
#define TX2_FIFO_HS_SIZE 0
#define TX3_FIFO_HS_SIZE 0
#define TX4_FIFO_HS_SIZE 0
#define TX5_FIFO_HS_SIZE 0
#define TXH_NP_HS_FIFOSIZ 96
#define TXH_P_HS_FIFOSIZ 96
// #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
// #define USB_OTG_HS_SOF_OUTPUT_ENABLED
// #define USB_OTG_INTERNAL_VBUS_ENABLED
#define USB_OTG_EXTERNAL_VBUS_ENABLED
#ifdef USE_ULPI_PHY
#define USB_OTG_ULPI_PHY_ENABLED
#endif
#ifdef USE_EMBEDDED_PHY
#define USB_OTG_EMBEDDED_PHY_ENABLED
#endif
#define USB_OTG_HS_INTERNAL_DMA_ENABLED
#define USB_OTG_HS_DEDICATED_EP1_ENABLED
#endif
/****************** USB OTG FS CONFIGURATION **********************************/
#ifdef USB_OTG_FS_CORE
#define RX_FIFO_FS_SIZE 128
#define TX0_FIFO_FS_SIZE 64
#define TX1_FIFO_FS_SIZE 128
#define TX2_FIFO_FS_SIZE 0
#define TX3_FIFO_FS_SIZE 0
#define TXH_NP_HS_FIFOSIZ 96
#define TXH_P_HS_FIFOSIZ 96
// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
// #define USB_OTG_FS_SOF_OUTPUT_ENABLED
#endif
/****************** USB OTG MISC CONFIGURATION ********************************/
//#define VBUS_SENSING_ENABLED
/****************** USB OTG MODE CONFIGURATION ********************************/
//#define USE_HOST_MODE
#define USE_DEVICE_MODE
//#define USE_OTG_MODE
#ifndef USB_OTG_FS_CORE
#ifndef USB_OTG_HS_CORE
#error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
#endif
#endif
#ifndef USE_DEVICE_MODE
#ifndef USE_HOST_MODE
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
#endif
#endif
#ifndef USE_USB_OTG_HS
#ifndef USE_USB_OTG_FS
#error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
#endif
#else //USE_USB_OTG_HS
#ifndef USE_ULPI_PHY
#ifndef USE_EMBEDDED_PHY
#error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined"
#endif
#endif
#endif
/****************** C Compilers dependant keywords ****************************/
/* In HS mode and when the DMA is used, all variables and data structures dealing
with the DMA during the transaction process should be 4-bytes aligned */
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
#if defined (__GNUC__) /* GNU Compiler */
#define __ALIGN_END __attribute__ ((aligned (4)))
#define __ALIGN_BEGIN
#else
#define __ALIGN_END
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#elif defined (__TASKING__) /* TASKING Compiler */
#define __ALIGN_BEGIN __align(4)
#endif /* __CC_ARM */
#endif /* __GNUC__ */
#else
#define __ALIGN_BEGIN
#define __ALIGN_END
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
/* __packed keyword used to decrease the data type alignment to 1-byte */
#if defined (__CC_ARM) /* ARM Compiler */
#define __packed __packed
#elif defined (__ICCARM__) /* IAR Compiler */
#define __packed __packed
#elif defined ( __GNUC__ ) /* GNU Compiler */
#define __packed __attribute__ ((__packed__))
#elif defined (__TASKING__) /* TASKING Compiler */
#define __packed __unaligned
#endif /* __CC_ARM */
/**
* @}
*/
/** @defgroup USB_CONF_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup USB_CONF_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USB_CONF_Exported_Variables
* @{
*/
/**
* @}
*/
/** @defgroup USB_CONF_Exported_FunctionsPrototype
* @{
*/
/**
* @}
*/
#endif //__USB_CONF__H__
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/Release_Notes.html
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@ -13,7 +13,7 @@ w\:* {behavior:url(#default#VML);}
<title>Release Notes for STM32F105/7xx and STM32F2xx USB OTG Driver</title><!--[if gte mso 9]><xml> <title>Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB OTG Driver</title><!--[if gte mso 9]><xml>
<o:DocumentProperties> <o:DocumentProperties>
<o:Author>STMicroelectronics</o:Author> <o:Author>STMicroelectronics</o:Author>
<o:LastAuthor>Raouf Hosni</o:LastAuthor> <o:LastAuthor>Raouf Hosni</o:LastAuthor>
@ -877,8 +877,8 @@ ul
</xml><![endif]--><!--[if gte mso 9]><xml> </xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit"> <o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1"/> <o:idmap v:ext="edit" data="1"/>
</o:shapelayout></xml><![endif]--></head> </o:shapelayout></xml><![endif]--><meta content="MCD Application Team" name="author"></head>
<body style="" lang="EN-US" link="blue" vlink="blue"> <body style="" link="blue" vlink="blue">
<div class="WordSection1"> <div class="WordSection1">
@ -897,9 +897,9 @@ ul
</tr> </tr>
<tr style=""> <tr style="">
<td style="padding: 1.5pt;"> <td style="padding: 1.5pt;">
<h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release Notes for STM32F105/7xx and STM32F2xx USB OTG Driver</span><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></h1> <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB OTG Driver</span><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright
2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p> 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p> <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
</td> </td>
</tr> </tr>
@ -910,20 +910,29 @@ ul
<td style="padding: 0in;" valign="top"> <td style="padding: 0in;" valign="top">
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2> <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
<ol style="margin-top: 0in;" start="1" type="1"> <ol style="margin-top: 0in;" start="1" type="1">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#History">STM32F105/7xx and STM32F2xx USB OTG Driver update History</a><o:p></o:p></span></li> <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#History">Update History</a><o:p></o:p></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#License">License</a><o:p></o:p></span></li> <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#License">License</a><o:p></o:p></span></li>
</ol> </ol>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F105/7xx and STM32F2xx USB OTG Driver&nbsp; update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 22-July-2011 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.0 / 19-March-2012<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p> Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Second official version supporting <span style="font-weight: bold; font-style: italic;">STM32F105/7</span> and <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename the Library from "<span style="font-style: italic;">STM32_USB_HOST_Driver</span>" to "<span style="font-style: italic;">STM32_USB_OTG_Driver</span>"</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for Device and OTG modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change HCD layer to support High speed core</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the Low level driver to support multi core support for Host mode</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Stop mechanism for Host and Device modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><br></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0&nbsp;- 11/29/2010<o:p></o:p></span></h3>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official support of </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F4xx</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Unmask Session request interrupt to handle the connect event during the core start-up</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove any reference to the USB HS external I2C PHY</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update optimization pragma for AR Compiler</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Handle Correctly the Low Speed device connection in HS mode</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add a wrapper to isolate the library from the low level driver: connection done through ISR structure<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous bug fix</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 22-July-2011 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Second official version supporting <span style="font-weight: bold; font-style: italic;">STM32F105/7</span> and <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename the Library from "<span style="font-style: italic;">STM32_USB_HOST_Driver</span>" to "<span style="font-style: italic;">STM32_USB_OTG_Driver</span>"</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for Device and OTG modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change HCD layer to support High speed core</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the Low level driver to support multi core support for Host mode</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Stop mechanism for Host and Device modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0&nbsp;- 11/29/2010<o:p></o:p></span></h3>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created&nbsp;</span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2> <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created&nbsp;</span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<p class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana; color: black;">The use of this STM32 software is governed by the terms and conditions of the License Agreement </span><span style="font-size: 10pt; font-family: Verdana; color: black;"><span style="font-weight: bold; font-style: italic;">"MCD-ST Liberty SW License Agreement 20Jul2011 v0.1.pdf"</span> </span><span style="font-size: 10pt; font-family: Verdana; color: black;">available in the root of this package.</span><span style="color: black;"><o:p>&nbsp;</o:p></span></p> <p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing permissions and
limitations under the License.</span>
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;"> <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
<hr align="center" size="2" width="100%"> <hr align="center" size="2" width="100%">
</span></div> </span></div>
<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For <p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32(<span style="color: black;">CORTEX M3) 32-Bit complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
</td> </td>
</tr> </tr>
</tbody></table> </tbody></table>

25
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_bsp.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_bsp.h * @file usb_bsp.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Specific api's relative to the used hardware platform * @brief Specific api's relative to the used hardware platform
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -25,6 +31,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "usb_core.h" #include "usb_core.h"
#include "usb_conf.h"
/** @addtogroup USB_OTG_DRIVER /** @addtogroup USB_OTG_DRIVER
* @{ * @{

49
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_core.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_core.h * @file usb_core.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Header of the Core Layer * @brief Header of the Core Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -63,7 +69,7 @@
/** /**
* @} * @}
*/ */
#define MAX_DATA_LENGTH 0xFF #define MAX_DATA_LENGTH 0x200
/** @defgroup USB_CORE_Exported_Types /** @defgroup USB_CORE_Exported_Types
* @{ * @{
@ -191,15 +197,15 @@ typedef struct _Device_TypeDef
const uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); const uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);
} USBD_DEVICE, *pUSBD_DEVICE; } USBD_DEVICE, *pUSBD_DEVICE;
typedef struct USB_OTG_hPort //typedef struct USB_OTG_hPort
{ //{
void (*Disconnect) (void *phost); // void (*Disconnect) (void *phost);
void (*Connect) (void *phost); // void (*Connect) (void *phost);
uint8_t ConnStatus; // uint8_t ConnStatus;
uint8_t DisconnStatus; // uint8_t DisconnStatus;
uint8_t ConnHandled; // uint8_t ConnHandled;
uint8_t DisconnHandled; // uint8_t DisconnHandled;
} USB_OTG_hPort_TypeDef; //} USB_OTG_hPort_TypeDef;
typedef struct _Device_cb typedef struct _Device_cb
{ {
@ -248,7 +254,10 @@ typedef struct _DCD
uint8_t device_config; uint8_t device_config;
uint8_t device_state; uint8_t device_state;
uint8_t device_status; uint8_t device_status;
uint8_t device_old_status;
uint8_t device_address; uint8_t device_address;
uint8_t connection_status;
uint8_t test_mode;
uint32_t DevRemoteWakeup; uint32_t DevRemoteWakeup;
USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS];
USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS];
@ -271,7 +280,7 @@ typedef struct _HCD
__IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS];
USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS];
uint16_t channel [USB_OTG_MAX_TX_FIFOS]; uint16_t channel [USB_OTG_MAX_TX_FIFOS];
USB_OTG_hPort_TypeDef *port_cb; // USB_OTG_hPort_TypeDef *port_cb;
} }
HCD_DEV , *USB_OTG_USBH_PDEV; HCD_DEV , *USB_OTG_USBH_PDEV;

24
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_dcd.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_dcd.h * @file usb_dcd.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Peripheral Driver Header file * @brief Peripheral Driver Header file
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */

24
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_dcd_int.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_dcd_int.h * @file usb_dcd_int.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Peripheral Device Interface Layer * @brief Peripheral Device Interface Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */

25
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_defines.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_defines.h * @file usb_defines.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Header of the Core Layer * @brief Header of the Core Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -57,7 +63,6 @@
#define USB_OTG_ULPI_PHY 1 #define USB_OTG_ULPI_PHY 1
#define USB_OTG_EMBEDDED_PHY 2 #define USB_OTG_EMBEDDED_PHY 2
#define USB_OTG_I2C_PHY 3
/** /**
* @} * @}

24
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_hcd.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_hcd.h * @file usb_hcd.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Host layer Header file * @brief Host layer Header file
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */

67
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_hcd_int.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_hcd_int.h * @file usb_hcd_int.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Peripheral Device Interface Layer * @brief Peripheral Device Interface Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -23,7 +29,6 @@
#ifndef __HCD_INT_H__ #ifndef __HCD_INT_H__
#define __HCD_INT_H__ #define __HCD_INT_H__
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "usb_hcd.h" #include "usb_hcd.h"
@ -49,6 +54,16 @@
/** @defgroup USB_HCD_INT_Exported_Types /** @defgroup USB_HCD_INT_Exported_Types
* @{ * @{
*/ */
typedef struct _USBH_HCD_INT
{
uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev);
uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev);
uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev);
}USBH_HCD_INT_cb_TypeDef;
extern USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops;
/** /**
* @} * @}
*/ */
@ -66,25 +81,25 @@
USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\ USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
}\ }\
#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ #define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
GINTMSK.b.chhltd = 0; \ INTMSK.b.chhltd = 0; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ #define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
GINTMSK.b.chhltd = 1; \ INTMSK.b.chhltd = 1; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ #define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
GINTMSK.b.ack = 0; \ INTMSK.b.ack = 0; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, GINTMSK.d32);}
#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ #define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef INTMSK; \
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
GINTMSK.b.ack = 1; \ INTMSK.b.ack = 1; \
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
/** /**
* @} * @}

29
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_otg.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_otg.h * @file usb_otg.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief OTG Core Header * @brief OTG Core Header
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -41,10 +47,9 @@
void USB_OTG_InitiateSRP(void); void USB_OTG_InitiateSRP(void);
void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode); void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode);
void USB_OTG_Switchback (USB_OTG_CORE_HANDLE *pdev); void USB_OTG_Switchback (USB_OTG_CORE_DEVICE *pdev);
uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev); uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_DEVICE *pdev);
uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev);
/** /**
* @} * @}
*/ */

186
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/inc/usb_regs.h
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_regs.h * @file usb_regs.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief hardware registers * @brief hardware registers
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -88,8 +94,7 @@ typedef struct _USB_OTG_GREGS //000h
__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
__IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
__IO uint32_t GI2CCTL; /* I2C Access Register 030h*/ uint32_t Reserved30[2]; /* Reserved 030h*/
uint32_t Reserved34; /* PHY Vendor Control Register 034h*/
__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
__IO uint32_t CID; /* User ID Register 03Ch*/ __IO uint32_t CID; /* User ID Register 03Ch*/
uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
@ -160,7 +165,7 @@ USB_OTG_INEPREGS;
typedef struct _USB_OTG_OUTEPREGS typedef struct _USB_OTG_OUTEPREGS
{ {
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
__IO uint32_t DOUTEPFRM; /* dev OUT Endpoint Frame number B00h + (ep_num * 20h) + 04h*/ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
@ -200,7 +205,7 @@ typedef struct _USB_OTG_HC_REGS
__IO uint32_t HCCHAR; __IO uint32_t HCCHAR;
__IO uint32_t HCSPLT; __IO uint32_t HCSPLT;
__IO uint32_t HCINT; __IO uint32_t HCINT;
__IO uint32_t HCGINTMSK; __IO uint32_t HCINTMSK;
__IO uint32_t HCTSIZ; __IO uint32_t HCTSIZ;
__IO uint32_t HCDMA; __IO uint32_t HCDMA;
uint32_t Reserved[2]; uint32_t Reserved[2];
@ -227,7 +232,7 @@ typedef struct USB_OTG_core_regs //000h
__IO uint32_t *PCGCCTL; __IO uint32_t *PCGCCTL;
} }
USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS; USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS;
typedef union _USB_OTG_OTGCTL_TypeDef typedef union _USB_OTG_GOTGCTL_TypeDef
{ {
uint32_t d32; uint32_t d32;
struct struct
@ -250,19 +255,18 @@ uint32_t Reserved12_15 :
4; 4;
uint32_t conidsts : uint32_t conidsts :
1; 1;
uint32_t Reserved17 : uint32_t dbct :
1; 1;
uint32_t asesvld : uint32_t asesvld :
1; 1;
uint32_t bsesvld : uint32_t bsesvld :
1; 1;
uint32_t currmod : uint32_t Reserved20_31 :
1; 12;
uint32_t Reserved21_31 :
11;
} }
b; b;
} USB_OTG_OTGCTL_TypeDef ; } USB_OTG_GOTGCTL_TypeDef ;
typedef union _USB_OTG_GOTGINT_TypeDef typedef union _USB_OTG_GOTGINT_TypeDef
{ {
uint32_t d32; uint32_t d32;
@ -320,15 +324,11 @@ typedef union _USB_OTG_GUSBCFG_TypeDef
{ {
uint32_t toutcal : uint32_t toutcal :
3; 3;
uint32_t phyif : uint32_t Reserved3_5 :
1; 3;
uint32_t ulpi_utmi_sel :
1;
uint32_t fsintf :
1;
uint32_t physel : uint32_t physel :
1; 1;
uint32_t ddrsel : uint32_t Reserved7 :
1; 1;
uint32_t srpcap : uint32_t srpcap :
1; 1;
@ -336,11 +336,11 @@ uint32_t hnpcap :
1; 1;
uint32_t usbtrdtim : uint32_t usbtrdtim :
4; 4;
uint32_t nptxfrwnden : uint32_t Reserved14 :
1; 1;
uint32_t phylpwrclksel : uint32_t phylpwrclksel :
1; 1;
uint32_t otgutmifssel : uint32_t Reserved16 :
1; 1;
uint32_t ulpi_fsls : uint32_t ulpi_fsls :
1; 1;
@ -350,12 +350,18 @@ uint32_t ulpi_clk_sus_m :
1; 1;
uint32_t ulpi_ext_vbus_drv : uint32_t ulpi_ext_vbus_drv :
1; 1;
uint32_t ulpi_int_vbus_indicator : uint32_t ulpi_int_vbus_ind :
1; 1;
uint32_t term_sel_dl_pulse : uint32_t term_sel_dl_pulse :
1; 1;
uint32_t Reserved : uint32_t ulpi_ind_cpl :
6; 1;
uint32_t ulpi_passthrough :
1;
uint32_t ulpi_protect_disable :
1;
uint32_t Reserved26_28 :
3;
uint32_t force_host : uint32_t force_host :
1; 1;
uint32_t force_dev : uint32_t force_dev :
@ -376,7 +382,7 @@ uint32_t hsftrst :
1; 1;
uint32_t hstfrm : uint32_t hstfrm :
1; 1;
uint32_t intknqflsh : uint32_t Reserved3 :
1; 1;
uint32_t rxfflsh : uint32_t rxfflsh :
1; 1;
@ -414,10 +420,8 @@ uint32_t ginnakeff :
1; 1;
uint32_t goutnakeff : uint32_t goutnakeff :
1; 1;
uint32_t Reserved8 : uint32_t Reserved8_9 :
1; 2;
uint32_t i2cintr :
1;
uint32_t erlysuspend : uint32_t erlysuspend :
1; 1;
uint32_t usbsuspend : uint32_t usbsuspend :
@ -484,10 +488,8 @@ uint32_t ginnakeff :
1; 1;
uint32_t goutnakeff : uint32_t goutnakeff :
1; 1;
uint32_t Reserved8 : uint32_t Reserved8_9 :
1; 2;
uint32_t i2cintr :
1;
uint32_t erlysuspend : uint32_t erlysuspend :
1; 1;
uint32_t usbsuspend : uint32_t usbsuspend :
@ -500,10 +502,8 @@ uint32_t isooutdrop :
1; 1;
uint32_t eopframe : uint32_t eopframe :
1; 1;
uint32_t intimerrx : uint32_t Reserved16_17 :
1; 2;
uint32_t epmismatch :
1;
uint32_t inepint: uint32_t inepint:
1; 1;
uint32_t outepintr : uint32_t outepintr :
@ -592,14 +592,15 @@ uint32_t nptxfspcavail :
16; 16;
uint32_t nptxqspcavail : uint32_t nptxqspcavail :
8; 8;
uint32_t nptxqtop_terminate : struct
{
uint32_t terminate :
1; 1;
uint32_t nptxqtop_timer : uint32_t token :
2;
uint32_t nptxqtop :
2; 2;
uint32_t chnum : uint32_t chnum :
2; 4;
} nptxqtop;
uint32_t Reserved : uint32_t Reserved :
1; 1;
} }
@ -617,36 +618,7 @@ uint32_t Reserved :
} }
b; b;
} USB_OTG_DTXFSTSn_TypeDef ; } USB_OTG_DTXFSTSn_TypeDef ;
typedef union _USB_OTG_GI2CCTL_TypeDef
{
uint32_t d32;
struct
{
uint32_t rwdata :
8;
uint32_t regaddr :
8;
uint32_t addr :
7;
uint32_t i2cen :
1;
uint32_t ack :
1;
uint32_t i2csuspctl :
1;
uint32_t i2cdevaddr :
2;
uint32_t dat_se0:
1;
uint32_t Reserved :
1;
uint32_t rw :
1;
uint32_t bsydne :
1;
}
b;
} USB_OTG_GI2CCTL_TypeDef ;
typedef union _USB_OTG_GCCFG_TypeDef typedef union _USB_OTG_GCCFG_TypeDef
{ {
uint32_t d32; uint32_t d32;
@ -656,7 +628,7 @@ uint32_t Reserved_in :
16; 16;
uint32_t pwdn : uint32_t pwdn :
1; 1;
uint32_t i2cifen : uint32_t Reserved_17 :
1; 1;
uint32_t vbussensingA : uint32_t vbussensingA :
1; 1;
@ -687,10 +659,8 @@ uint32_t devaddr :
7; 7;
uint32_t perfrint : uint32_t perfrint :
2; 2;
uint32_t Reserved13_17 : uint32_t Reserved12_31 :
5; 19;
uint32_t epmscnt :
4;
} }
b; b;
} USB_OTG_DCFG_TypeDef ; } USB_OTG_DCFG_TypeDef ;
@ -717,8 +687,10 @@ uint32_t sgoutnak :
1; 1;
uint32_t cgoutnak : uint32_t cgoutnak :
1; 1;
uint32_t poprg_done :
1;
uint32_t Reserved : uint32_t Reserved :
21; 20;
} }
b; b;
} USB_OTG_DCTL_TypeDef ; } USB_OTG_DCTL_TypeDef ;
@ -751,13 +723,13 @@ uint32_t xfercompl :
1; 1;
uint32_t epdisabled : uint32_t epdisabled :
1; 1;
uint32_t ahberr : uint32_t Reserved2 :
1; 1;
uint32_t timeout : uint32_t timeout :
1; 1;
uint32_t intktxfemp : uint32_t intktxfemp :
1; 1;
uint32_t intknepmis : uint32_t Reserved5 :
1; 1;
uint32_t inepnakeff : uint32_t inepnakeff :
1; 1;
@ -765,7 +737,7 @@ uint32_t emptyintr :
1; 1;
uint32_t txfifoundrn : uint32_t txfifoundrn :
1; 1;
uint32_t Reserved08_31 : uint32_t Reserved14_31 :
23; 23;
} }
b; b;
@ -780,7 +752,7 @@ uint32_t xfercompl :
1; 1;
uint32_t epdisabled : uint32_t epdisabled :
1; 1;
uint32_t ahberr : uint32_t Reserved2 :
1; 1;
uint32_t setup : uint32_t setup :
1; 1;
@ -821,8 +793,12 @@ uint32_t rx_thr_en :
1; 1;
uint32_t rx_thr_len : uint32_t rx_thr_len :
9; 9;
uint32_t Reserved26_31 : uint32_t Reserved26 :
6; 1;
uint32_t arp_en :
1;
uint32_t Reserved28_31 :
4;
} }
b; b;
} USB_OTG_DTHRCTL_TypeDef ; } USB_OTG_DTHRCTL_TypeDef ;
@ -945,16 +921,17 @@ uint32_t ptxfspcavail :
16; 16;
uint32_t ptxqspcavail : uint32_t ptxqspcavail :
8; 8;
uint32_t ptxqtop_terminate : struct
{
uint32_t terminate :
1; 1;
uint32_t ptxqtop_timer : uint32_t token :
2;
uint32_t ptxqtop :
2; 2;
uint32_t chnum : uint32_t chnum :
2; 4;
uint32_t ptxqtop_odd : uint32_t odd_even :
1; 1;
} ptxqtop;
} }
b; b;
} USB_OTG_HPTXSTS_TypeDef ; } USB_OTG_HPTXSTS_TypeDef ;
@ -1118,7 +1095,7 @@ uint32_t dopng :
} }
b; b;
} USB_OTG_HCTSIZn_TypeDef ; } USB_OTG_HCTSIZn_TypeDef ;
typedef union _USB_OTG_HCGINTMSK_TypeDef typedef union _USB_OTG_HCINTMSK_TypeDef
{ {
uint32_t d32; uint32_t d32;
struct struct
@ -1149,7 +1126,8 @@ uint32_t Reserved :
21; 21;
} }
b; b;
} USB_OTG_HCGINTMSK_TypeDef ; } USB_OTG_HCINTMSK_TypeDef ;
typedef union _USB_OTG_PCGCCTL_TypeDef typedef union _USB_OTG_PCGCCTL_TypeDef
{ {
uint32_t d32; uint32_t d32;
@ -1159,8 +1137,12 @@ uint32_t stoppclk :
1; 1;
uint32_t gatehclk : uint32_t gatehclk :
1; 1;
uint32_t Reserved : uint32_t Reserved2_3 :
30; 2;
uint32_t phy_susp :
1;
uint32_t Reserved5_31 :
27;
} }
b; b;
} USB_OTG_PCGCCTL_TypeDef ; } USB_OTG_PCGCCTL_TypeDef ;

32
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/src/usb_bsp_template.c
View File

@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file usb_bsp.c * @file usb_bsp.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief This file is responsible to offer board support package and is * @brief This file is responsible to offer board support package and is
* configurable by user. * configurable by user.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -85,7 +91,7 @@
* @retval None * @retval None
*/ */
void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) void USB_OTG_BSP_Init(void)
{ {
} }
@ -95,7 +101,7 @@ void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev)
* @param None * @param None
* @retval None * @retval None
*/ */
void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) void USB_OTG_BSP_EnableInterrupt(void)
{ {
} }
@ -108,7 +114,7 @@ void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev)
* @retval None * @retval None
*/ */
void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev, uint8_t state) void USB_OTG_BSP_DriveVBUS(uint32_t speed, uint8_t state)
{ {
} }
@ -120,7 +126,7 @@ void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev, uint8_t state)
* @retval None * @retval None
*/ */
void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev) void USB_OTG_BSP_ConfigVBUS(uint32_t speed)
{ {
} }

81
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/src/usb_core.c
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_core.c * @file usb_core.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief USB-OTG Core Layer * @brief USB-OTG Core Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -96,7 +102,7 @@ static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF);
#endif #endif
/* Clear any pending interrupts */ /* Clear any pending interrupts */
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF);
/* Enable the interrupts in the INTMSK */ /* Enable the interrupts in the INTMSK */
int_mask.b.wkupintr = 1; int_mask.b.wkupintr = 1;
int_mask.b.usbsuspend = 1; int_mask.b.usbsuspend = 1;
@ -255,10 +261,6 @@ USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev,
#else #else
#ifdef USB_OTG_EMBEDDED_PHY_ENABLED #ifdef USB_OTG_EMBEDDED_PHY_ENABLED
pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY;
#else
#ifdef USB_OTG_I2C_PHY_ENABLED
pdev->cfg.phy_itface = USB_OTG_I2C_PHY;
#endif
#endif #endif
#endif #endif
@ -323,7 +325,6 @@ USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_STS status = USB_OTG_OK; USB_OTG_STS status = USB_OTG_OK;
USB_OTG_GUSBCFG_TypeDef usbcfg; USB_OTG_GUSBCFG_TypeDef usbcfg;
USB_OTG_GCCFG_TypeDef gccfg; USB_OTG_GCCFG_TypeDef gccfg;
USB_OTG_GI2CCTL_TypeDef i2cctl;
USB_OTG_GAHBCFG_TypeDef ahbcfg; USB_OTG_GAHBCFG_TypeDef ahbcfg;
usbcfg.d32 = 0; usbcfg.d32 = 0;
@ -356,10 +357,6 @@ USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
#endif #endif
#endif #endif
usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */
usbcfg.b.ulpi_utmi_sel = 1; /* ULPI seleInterfacect */
usbcfg.b.phyif = 0; /* 8 bits */
usbcfg.b.ddrsel = 0; /* single data rate */
usbcfg.b.ulpi_fsls = 0; usbcfg.b.ulpi_fsls = 0;
usbcfg.b.ulpi_clk_sus_m = 0; usbcfg.b.ulpi_clk_sus_m = 0;
@ -389,10 +386,6 @@ USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
gccfg.d32 = 0; gccfg.d32 = 0;
gccfg.b.pwdn = 1; gccfg.b.pwdn = 1;
if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
{
gccfg.b.i2cifen = 1;
}
gccfg.b.vbussensingA = 1 ; gccfg.b.vbussensingA = 1 ;
gccfg.b.vbussensingB = 1 ; gccfg.b.vbussensingB = 1 ;
#ifndef VBUS_SENSING_ENABLED #ifndef VBUS_SENSING_ENABLED
@ -406,32 +399,6 @@ USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
USB_OTG_BSP_mDelay(20); USB_OTG_BSP_mDelay(20);
/* Program GUSBCFG.OtgUtmifsSel to I2C*/
usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
{
usbcfg.b.otgutmifssel = 1;
}
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
{
/*Program GI2CCTL.I2CEn*/
i2cctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GI2CCTL);
i2cctl.b.i2cdevaddr = 1;
i2cctl.b.i2cen = 0;
i2cctl.b.dat_se0 = 1;
i2cctl.b.addr = 0x2D;
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
USB_OTG_BSP_mDelay(200);
i2cctl.b.i2cen = 1;
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
USB_OTG_BSP_mDelay(200);
}
} }
/* case the HS core is working in FS mode */ /* case the HS core is working in FS mode */
if(pdev->cfg.dma_enable == 1) if(pdev->cfg.dma_enable == 1)
@ -670,7 +637,15 @@ USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
/* Initialize Host Configuration Register */ /* Initialize Host Configuration Register */
if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
{
USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ);
}
else
{
USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */ USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */
}
USB_OTG_ResetPort(pdev);
hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
hcfg.b.fslssupp = 0; hcfg.b.fslssupp = 0;
@ -722,7 +697,7 @@ USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
for (i = 0; i < pdev->cfg.host_channels; i++) for (i = 0; i < pdev->cfg.host_channels; i++)
{ {
USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF );
USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCGINTMSK, 0 ); USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 );
} }
#ifndef USE_OTG_MODE #ifndef USE_OTG_MODE
USB_OTG_DriveVbus(pdev, 1); USB_OTG_DriveVbus(pdev, 1);
@ -883,7 +858,7 @@ USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
{ {
USB_OTG_STS status = USB_OTG_OK; USB_OTG_STS status = USB_OTG_OK;
uint32_t intr_enable = 0; uint32_t intr_enable = 0;
USB_OTG_HCGINTMSK_TypeDef hcintmsk; USB_OTG_HCINTMSK_TypeDef hcintmsk;
USB_OTG_GINTMSK_TypeDef gintmsk; USB_OTG_GINTMSK_TypeDef gintmsk;
USB_OTG_HCCHAR_TypeDef hcchar; USB_OTG_HCCHAR_TypeDef hcchar;
USB_OTG_HCINTn_TypeDef hcint; USB_OTG_HCINTn_TypeDef hcint;
@ -955,7 +930,7 @@ USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
} }
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, hcintmsk.d32); USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32);
/* Enable the top level host channel interrupt. */ /* Enable the top level host channel interrupt. */
@ -1405,7 +1380,7 @@ USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev)
/* Disable all interrupts. */ /* Disable all interrupts. */
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0);
/* Clear any pending interrupts */ /* Clear any pending interrupts */
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF);
/* Enable the common interrupts */ /* Enable the common interrupts */
USB_OTG_EnableCommonInt(pdev); USB_OTG_EnableCommonInt(pdev);

24
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/src/usb_dcd.c
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_dcd.c * @file usb_dcd.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Peripheral Device Interface Layer * @brief Peripheral Device Interface Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */

70
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_dcd_int.c * @file usb_dcd_int.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Peripheral Device interrupt subroutines * @brief Peripheral Device interrupt subroutines
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -140,11 +146,7 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
/* Clear the bit in DOEPINTn for this interrupt */ /* Clear the bit in DOEPINTn for this interrupt */
CLEAR_OUT_EP_INTR(1, epdisabled); CLEAR_OUT_EP_INTR(1, epdisabled);
} }
/* AHB Error */
if ( doepint.b.ahberr )
{
CLEAR_OUT_EP_INTR(1, ahberr);
}
return 1; return 1;
} }
@ -173,10 +175,6 @@ uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
/* TX COMPLETE */ /* TX COMPLETE */
USBD_DCD_INT_fops->DataInStage(pdev , 1); USBD_DCD_INT_fops->DataInStage(pdev , 1);
} }
if ( diepint.b.ahberr )
{
CLEAR_IN_EP_INTR(1, ahberr);
}
if ( diepint.b.epdisabled ) if ( diepint.b.epdisabled )
{ {
CLEAR_IN_EP_INTR(1, epdisabled); CLEAR_IN_EP_INTR(1, epdisabled);
@ -189,10 +187,6 @@ uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
{ {
CLEAR_IN_EP_INTR(1, intktxfemp); CLEAR_IN_EP_INTR(1, intktxfemp);
} }
if (diepint.b.intknepmis)
{
CLEAR_IN_EP_INTR(1, intknepmis);
}
if (diepint.b.inepnakeff) if (diepint.b.inepnakeff)
{ {
CLEAR_IN_EP_INTR(1, inepnakeff); CLEAR_IN_EP_INTR(1, inepnakeff);
@ -390,7 +384,9 @@ static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_GINTSTS_TypeDef gintsts; USB_OTG_GINTSTS_TypeDef gintsts;
USB_OTG_PCGCCTL_TypeDef power; USB_OTG_PCGCCTL_TypeDef power;
USB_OTG_DSTS_TypeDef dsts; USB_OTG_DSTS_TypeDef dsts;
__IO uint8_t prev_status = 0;
prev_status = pdev->dev.device_status;
USBD_DCD_INT_fops->Suspend (pdev); USBD_DCD_INT_fops->Suspend (pdev);
dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
@ -400,7 +396,9 @@ static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
gintsts.b.usbsuspend = 1; gintsts.b.usbsuspend = 1;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
if((pdev->cfg.low_power) && (dsts.b.suspsts == 1)) if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) &&
(pdev->dev.connection_status == 1) &&
(prev_status == USB_OTG_CONFIGURED))
{ {
/* switch-off the clocks */ /* switch-off the clocks */
power.d32 = 0; power.d32 = 0;
@ -454,10 +452,6 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
} }
} }
} }
if ( diepint.b.ahberr )
{
CLEAR_IN_EP_INTR(epnum, ahberr);
}
if ( diepint.b.timeout ) if ( diepint.b.timeout )
{ {
CLEAR_IN_EP_INTR(epnum, timeout); CLEAR_IN_EP_INTR(epnum, timeout);
@ -466,10 +460,6 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
{ {
CLEAR_IN_EP_INTR(epnum, intktxfemp); CLEAR_IN_EP_INTR(epnum, intktxfemp);
} }
if (diepint.b.intknepmis)
{
CLEAR_IN_EP_INTR(epnum, intknepmis);
}
if (diepint.b.inepnakeff) if (diepint.b.inepnakeff)
{ {
CLEAR_IN_EP_INTR(epnum, inepnakeff); CLEAR_IN_EP_INTR(epnum, inepnakeff);
@ -550,11 +540,6 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
CLEAR_OUT_EP_INTR(epnum, epdisabled); CLEAR_OUT_EP_INTR(epnum, epdisabled);
} }
/* AHB Error */ /* AHB Error */
if ( doepint.b.ahberr )
{
CLEAR_OUT_EP_INTR(epnum, ahberr);
}
/* Setup Phase Done (control EPs) */
if ( doepint.b.setup ) if ( doepint.b.setup )
{ {
@ -670,6 +655,8 @@ static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
len32b = (len + 3) / 4; len32b = (len + 3) / 4;
txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
while (txstatus.b.txfspcavail > len32b && while (txstatus.b.txfspcavail > len32b &&
ep->xfer_count < ep->xfer_len && ep->xfer_count < ep->xfer_len &&
ep->xfer_len != 0) ep->xfer_len != 0)
@ -691,13 +678,6 @@ static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
} }
if (ep->xfer_count == ep->xfer_len || ep->xfer_len == 0) {
/* Turn off the Fifo Empty Interrupt */
uint32_t fifoemptymsk;
fifoemptymsk = 0x1 << epnum;
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
}
return 1; return 1;
} }
@ -744,7 +724,6 @@ static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
doepmsk.b.setup = 1; doepmsk.b.setup = 1;
doepmsk.b.xfercompl = 1; doepmsk.b.xfercompl = 1;
doepmsk.b.ahberr = 1;
doepmsk.b.epdisabled = 1; doepmsk.b.epdisabled = 1;
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
@ -753,8 +732,7 @@ static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
diepmsk.b.xfercompl = 1; diepmsk.b.xfercompl = 1;
diepmsk.b.timeout = 1; diepmsk.b.timeout = 1;
diepmsk.b.epdisabled = 1; diepmsk.b.epdisabled = 1;
diepmsk.b.ahberr = 1;
diepmsk.b.intknepmis = 1;
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );

24
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/src/usb_hcd.c
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_hcd.c * @file usb_hcd.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Host Interface Layer * @brief Host Interface Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */

124
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/src/usb_hcd_int.c
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_hcd_int.c * @file usb_hcd_int.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief Host driver interrupt subroutines * @brief Host driver interrupt subroutines
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -26,8 +32,6 @@
#if defined (__CC_ARM) /*!< ARM Compiler */ #if defined (__CC_ARM) /*!< ARM Compiler */
#pragma O0 #pragma O0
#elif defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma O0
#elif defined (__GNUC__) /*!< GNU Compiler */ #elif defined (__GNUC__) /*!< GNU Compiler */
#pragma GCC optimize ("O0") #pragma GCC optimize ("O0")
#elif defined (__TASKING__) /*!< TASKING Compiler */ #elif defined (__TASKING__) /*!< TASKING Compiler */
@ -220,9 +224,10 @@ static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev)
static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev) static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev)
{ {
USB_OTG_GINTSTS_TypeDef gintsts; USB_OTG_GINTSTS_TypeDef gintsts;
gintsts.d32 = 0; gintsts.d32 = 0;
USBH_HCD_INT_fops->SOF(pdev);
/* Clear interrupt */ /* Clear interrupt */
gintsts.b.sofintr = 1; gintsts.b.sofintr = 1;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
@ -240,10 +245,9 @@ static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev)
{ {
USB_OTG_GINTSTS_TypeDef gintsts; USB_OTG_GINTSTS_TypeDef gintsts;
pdev->host.ConnSts = 0;
gintsts.d32 = 0; gintsts.d32 = 0;
pdev->host.port_cb->Disconnect(pdev); USBH_HCD_INT_fops->DevDisconnected(pdev);
/* Clear interrupt */ /* Clear interrupt */
gintsts.b.disconnect = 1; gintsts.b.disconnect = 1;
@ -251,7 +255,9 @@ static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev)
return 1; return 1;
} }
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/** /**
* @brief USB_OTG_USBH_handle_nptxfempty_ISR * @brief USB_OTG_USBH_handle_nptxfempty_ISR
* Handles non periodic tx fifo empty. * Handles non periodic tx fifo empty.
@ -266,38 +272,40 @@ static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4; len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
while ((hnptxsts.b.nptxfspcavail > len_words)&& while ((hnptxsts.b.nptxfspcavail > len_words)&&
(pdev->host.hc[hnptxsts.b.chnum].xfer_len != 0)) (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len != 0))
{ {
len = hnptxsts.b.nptxfspcavail * 4; len = hnptxsts.b.nptxfspcavail * 4;
if (len > pdev->host.hc[hnptxsts.b.chnum].xfer_len) if (len > pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len)
{ {
/* Last packet */ /* Last packet */
len = pdev->host.hc[hnptxsts.b.chnum].xfer_len; len = pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len;
intmsk.d32 = 0; intmsk.d32 = 0;
intmsk.b.nptxfempty = 1; intmsk.b.nptxfempty = 1;
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
} }
len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4; len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.chnum].xfer_buff, hnptxsts.b.chnum, len); USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff, hnptxsts.b.nptxqtop.chnum, len);
pdev->host.hc[hnptxsts.b.chnum].xfer_buff += len; pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff += len;
pdev->host.hc[hnptxsts.b.chnum].xfer_len -= len; pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len -= len;
pdev->host.hc[hnptxsts.b.chnum].xfer_count += len; pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_count += len;
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
} }
return 1; return 1;
} }
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/** /**
* @brief USB_OTG_USBH_handle_ptxfempty_ISR * @brief USB_OTG_USBH_handle_ptxfempty_ISR
* Handles periodic tx fifo empty * Handles periodic tx fifo empty
@ -312,30 +320,30 @@ static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4; len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
while ((hptxsts.b.ptxfspcavail > len_words)&& while ((hptxsts.b.ptxfspcavail > len_words)&&
(pdev->host.hc[hptxsts.b.chnum].xfer_len != 0)) (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len != 0))
{ {
len = hptxsts.b.ptxfspcavail * 4; len = hptxsts.b.ptxfspcavail * 4;
if (len > pdev->host.hc[hptxsts.b.chnum].xfer_len) if (len > pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len)
{ {
len = pdev->host.hc[hptxsts.b.chnum].xfer_len; len = pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len;
/* Last packet */ /* Last packet */
intmsk.d32 = 0; intmsk.d32 = 0;
intmsk.b.ptxfempty = 1; intmsk.b.ptxfempty = 1;
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
} }
len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4; len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.chnum].xfer_buff, hptxsts.b.chnum, len); USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff, hptxsts.b.ptxqtop.chnum, len);
pdev->host.hc[hptxsts.b.chnum].xfer_buff += len; pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff += len;
pdev->host.hc[hptxsts.b.chnum].xfer_len -= len; pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len -= len;
pdev->host.hc[hptxsts.b.chnum].xfer_count += len; pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_count += len;
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
} }
@ -349,6 +357,9 @@ static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
* @param pdev: Selected device * @param pdev: Selected device
* @retval status * @retval status
*/ */
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev) static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
{ {
USB_OTG_HPRT0_TypeDef hprt0; USB_OTG_HPRT0_TypeDef hprt0;
@ -374,9 +385,9 @@ static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
/* Port Connect Detected */ /* Port Connect Detected */
if (hprt0.b.prtconndet) if (hprt0.b.prtconndet)
{ {
pdev->host.port_cb->Connect(pdev);
hprt0_dup.b.prtconndet = 1; hprt0_dup.b.prtconndet = 1;
do_reset = 1; USBH_HCD_INT_fops->DevConnected(pdev);
retval |= 1; retval |= 1;
} }
@ -384,9 +395,11 @@ static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
if (hprt0.b.prtenchng) if (hprt0.b.prtenchng)
{ {
hprt0_dup.b.prtenchng = 1; hprt0_dup.b.prtenchng = 1;
if (hprt0.b.prtena == 1) if (hprt0.b.prtena == 1)
{ {
pdev->host.ConnSts = 1;
USBH_HCD_INT_fops->DevConnected(pdev);
if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) || if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) ||
(hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED)) (hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED))
@ -399,7 +412,7 @@ static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 ); USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 );
if (hcfg.b.fslspclksel != HCFG_6_MHZ) if (hcfg.b.fslspclksel != HCFG_6_MHZ)
{ {
if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) if(pdev->cfg.phy_itface == USB_OTG_EMBEDDED_PHY)
{ {
USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ ); USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ );
} }
@ -432,14 +445,15 @@ static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
if (do_reset) if (do_reset)
{ {
USB_OTG_ResetPort(pdev); USB_OTG_ResetPort(pdev);
} }
/* Clear Port Interrupts */ /* Clear Port Interrupts */
USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32); USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32);
return retval; return retval;
} }
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/** /**
* @brief USB_OTG_USBH_handle_hc_n_Out_ISR * @brief USB_OTG_USBH_handle_hc_n_Out_ISR
* Handles interrupt for a specific Host Channel * Handles interrupt for a specific Host Channel
@ -451,13 +465,13 @@ uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t
{ {
USB_OTG_HCINTn_TypeDef hcint; USB_OTG_HCINTn_TypeDef hcint;
USB_OTG_HCGINTMSK_TypeDef hcintmsk; USB_OTG_HCINTMSK_TypeDef hcintmsk;
USB_OTG_HC_REGS *hcreg; USB_OTG_HC_REGS *hcreg;
USB_OTG_HCCHAR_TypeDef hcchar; USB_OTG_HCCHAR_TypeDef hcchar;
hcreg = pdev->regs.HC_REGS[num]; hcreg = pdev->regs.HC_REGS[num];
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK); hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
hcint.d32 = hcint.d32 & hcintmsk.d32; hcint.d32 = hcint.d32 & hcintmsk.d32;
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
@ -471,7 +485,12 @@ uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t
{ {
CLEAR_HC_INT(hcreg , ack); CLEAR_HC_INT(hcreg , ack);
} }
else if (hcint.b.frmovrun)
{
UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg ,frmovrun);
}
else if (hcint.b.xfercompl) else if (hcint.b.xfercompl)
{ {
pdev->host.ErrCnt[num] = 0; pdev->host.ErrCnt[num] = 0;
@ -567,7 +586,9 @@ uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t
return 1; return 1;
} }
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
/** /**
* @brief USB_OTG_USBH_handle_hc_n_In_ISR * @brief USB_OTG_USBH_handle_hc_n_In_ISR
* Handles interrupt for a specific Host Channel * Handles interrupt for a specific Host Channel
@ -578,7 +599,7 @@ uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t
uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
{ {
USB_OTG_HCINTn_TypeDef hcint; USB_OTG_HCINTn_TypeDef hcint;
USB_OTG_HCGINTMSK_TypeDef hcintmsk; USB_OTG_HCINTMSK_TypeDef hcintmsk;
USB_OTG_HCCHAR_TypeDef hcchar; USB_OTG_HCCHAR_TypeDef hcchar;
USB_OTG_HCTSIZn_TypeDef hctsiz; USB_OTG_HCTSIZn_TypeDef hctsiz;
USB_OTG_HC_REGS *hcreg; USB_OTG_HC_REGS *hcreg;
@ -586,7 +607,7 @@ uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t n
hcreg = pdev->regs.HC_REGS[num]; hcreg = pdev->regs.HC_REGS[num];
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK); hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
hcint.d32 = hcint.d32 & hcintmsk.d32; hcint.d32 = hcint.d32 & hcintmsk.d32;
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
hcintmsk.d32 = 0; hcintmsk.d32 = 0;
@ -704,7 +725,6 @@ uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t n
{ {
UNMASK_HOST_INT_CHH (num); UNMASK_HOST_INT_CHH (num);
USB_OTG_HC_Halt(pdev, num); USB_OTG_HC_Halt(pdev, num);
CLEAR_HC_INT(hcreg , nak);
} }
else if ((hcchar.b.eptype == EP_TYPE_CTRL)|| else if ((hcchar.b.eptype == EP_TYPE_CTRL)||
(hcchar.b.eptype == EP_TYPE_BULK)) (hcchar.b.eptype == EP_TYPE_BULK))
@ -715,6 +735,7 @@ uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t n
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
} }
pdev->host.HC_Status[num] = HC_NAK; pdev->host.HC_Status[num] = HC_NAK;
CLEAR_HC_INT(hcreg , nak);
} }
@ -728,7 +749,9 @@ uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t n
* @param pdev: Selected device * @param pdev: Selected device
* @retval status * @retval status
*/ */
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev) static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev)
{ {
USB_OTG_GRXFSTS_TypeDef grxsts; USB_OTG_GRXFSTS_TypeDef grxsts;
@ -794,6 +817,9 @@ static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev)
* @param pdev: Selected device * @param pdev: Selected device
* @retval status * @retval status
*/ */
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma optimize = none
#endif /* __CC_ARM */
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev) static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev)
{ {

267
flight/pios/stm32f4xx/libraries/STM32_USB_OTG_Driver/src/usb_otg.c
View File

@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file usb_otg.c * @file usb_otg.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.0.0 * @version V2.1.0
* @date 22-July-2011 * @date 19-March-2012
* @brief OTG Core Layer * @brief OTG Core Layer
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@ -72,6 +78,10 @@
* @{ * @{
*/ */
uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev); static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev);
/** /**
@ -106,15 +116,15 @@ uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
} }
if (gintsts.b.otgintr) if (gintsts.b.otgintr)
{ {
retval |= 1;//USB_OTG_HandleOTG_ISR(pdev); retval |= USB_OTG_HandleOTG_ISR(pdev);
} }
if (gintsts.b.conidstschng) if (gintsts.b.conidstschng)
{ {
retval |= 2;//USB_OTG_HandleConnectorIDStatusChange_ISR(pdev); retval |= USB_OTG_HandleConnectorIDStatusChange_ISR(pdev);
} }
if (gintsts.b.sessreqintr) if (gintsts.b.sessreqintr)
{ {
retval |= 3;//USB_OTG_HandleSessionRequest_ISR(pdev); retval |= USB_OTG_HandleSessionRequest_ISR(pdev);
} }
return retval; return retval;
} }
@ -148,6 +158,239 @@ static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev)
} }
/**
* @brief USB_OTG_HandleOTG_ISR
* handles the OTG Interrupts
* @param None
* @retval : status
*/
static uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GOTGINT_TypeDef gotgint;
USB_OTG_GOTGCTL_TypeDef gotgctl;
gotgint.d32 = 0;
gotgctl.d32 = 0;
gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (gotgint.b.sesenddet)
{
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (USB_OTG_IsDeviceMode(pdev))
{
}
else if (USB_OTG_IsHostMode(pdev))
{
}
}
/* ----> SRP SUCCESS or FAILURE INTERRUPT <---- */
if (gotgint.b.sesreqsucstschng)
{
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (gotgctl.b.sesreqscs) /* Session request success */
{
if (USB_OTG_IsDeviceMode(pdev))
{
}
/* Clear Session Request */
gotgctl.d32 = 0;
gotgctl.b.sesreq = 1;
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
}
else /* Session request failure */
{
if (USB_OTG_IsDeviceMode(pdev))
{
}
}
}
/* ----> HNP SUCCESS or FAILURE INTERRUPT <---- */
if (gotgint.b.hstnegsucstschng)
{
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
if (gotgctl.b.hstnegscs) /* Host negotiation success */
{
if (USB_OTG_IsHostMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */
{
}
}
else /* Host negotiation failure */
{
}
gotgint.b.hstnegsucstschng = 1; /* Ack "Host Negotiation Success Status Change" interrupt. */
}
/* ----> HOST NEGOTIATION DETECTED INTERRUPT <---- */
if (gotgint.b.hstnegdet)
{
if (USB_OTG_IsDeviceMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */
{
}
else
{
}
}
if (gotgint.b.adevtoutchng)
{}
if (gotgint.b.debdone)
{
USB_OTG_ResetPort(pdev);
}
/* Clear OTG INT */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
return 1;
}
/**
* @brief USB_OTG_HandleConnectorIDStatusChange_ISR
* handles the Connector ID Status Change Interrupt
* @param None
* @retval : status
*/
static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTMSK_TypeDef gintmsk;
USB_OTG_GOTGCTL_TypeDef gotgctl;
USB_OTG_GINTSTS_TypeDef gintsts;
gintsts.d32 = 0 ;
gintmsk.d32 = 0 ;
gotgctl.d32 = 0 ;
gintmsk.b.sofintr = 1;
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, gintmsk.d32, 0);
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts)
{
USB_OTG_DisableGlobalInt(pdev);
USB_OTG_CoreInitDev(pdev);
USB_OTG_EnableGlobalInt(pdev);
pdev->otg.OTG_State = B_PERIPHERAL;
}
else
{
USB_OTG_DisableGlobalInt(pdev);
USB_OTG_CoreInitHost(pdev);
USB_OTG_EnableGlobalInt(pdev);
pdev->otg.OTG_State = A_HOST;
}
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
return 1;
}
/**
* @brief USB_OTG_HandleSessionRequest_ISR
* Initiating the Session Request Protocol
* @param None
* @retval : status
*/
static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GINTSTS_TypeDef gintsts;
USB_OTG_GOTGCTL_TypeDef gotgctl;
gotgctl.d32 = 0;
gintsts.d32 = 0;
gotgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
if (USB_OTG_IsDeviceMode(pdev) && (gotgctl.b.bsesvld))
{
}
else if (gotgctl.b.asesvld)
{
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
return 1;
}
/**
* @brief USB_OTG_InitiateSRP
* Initiate an srp session
* @param None
* @retval : None
*/
void USB_OTG_InitiateSRP(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_GOTGCTL_TypeDef otgctl;
otgctl.d32 = 0;
otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
if (otgctl.b.sesreq)
{
return; /* SRP in progress */
}
otgctl.b.sesreq = 1;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
}
/**
* @brief USB_OTG_InitiateHNP
* Initiate HNP
* @param None
* @retval : None
*/
void USB_OTG_InitiateHNP(USB_OTG_CORE_HANDLE *pdev , uint8_t state, uint8_t mode)
{
USB_OTG_GOTGCTL_TypeDef otgctl;
USB_OTG_HPRT0_TypeDef hprt0;
otgctl.d32 = 0;
hprt0.d32 = 0;
otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
if (mode)
{ /* Device mode */
if (state)
{
otgctl.b.devhnpen = 1; /* B-Dev has been enabled to perform HNP */
otgctl.b.hnpreq = 1; /* Initiate an HNP req. to the connected USB host*/
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
}
}
else
{ /* Host mode */
if (state)
{
otgctl.b.hstsethnpen = 1; /* A-Dev has enabled B-device for HNP */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
/* Suspend the bus so that B-dev will disconnect indicating the initial condition for HNP to DWC_Core */
hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
hprt0.b.prtsusp = 1; /* The core clear this bit when disconnect interrupt generated (GINTSTS.DisconnInt = '1') */
USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
}
}
}
/** /**
* @brief USB_OTG_GetCurrentState * @brief USB_OTG_GetCurrentState
* Return current OTG State * Return current OTG State