From ce6bebceb69f6bb1367e1b2c3c7b9fcad8b9f6c6 Mon Sep 17 00:00:00 2001 From: James Cotton Date: Sat, 14 Jul 2012 19:36:07 -0500 Subject: [PATCH] Also strex needs to not clobber it's register to have predictable results. OPReview-227 --- flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/core_cm3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/core_cm3.c b/flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/core_cm3.c index 0e8c3c43c..d202e369b 100755 --- a/flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/core_cm3.c +++ b/flight/PiOS/STM32F10x/Libraries/CMSIS/Core/CM3/core_cm3.c @@ -767,7 +767,7 @@ uint32_t __STREXW(uint32_t value, uint32_t *addr) { uint32_t result=0; - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); return(result); }