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https://bitbucket.org/librepilot/librepilot.git
synced 2024-11-30 08:24:11 +01:00
Make the Overo module use the new driver
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a6ba379af9
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@ -55,8 +55,7 @@ static bool overoEnabled;
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// Private functions
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static void overoSyncTask(void *parameters);
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static int32_t packData(uint8_t * data, int32_t length);
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static int32_t transmitData();
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static void transmitDataDone(bool crc_ok, uint8_t crc_val);
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static void transmitDataDone();
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static void registerObject(UAVObjHandle obj);
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struct dma_transaction {
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@ -197,6 +196,9 @@ static void overoSyncTask(void *parameters)
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portTickType lastUpdateTime = xTaskGetTickCount();
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portTickType updateTime;
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// Set the comms callback
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PIOS_Overo_SetCallback(transmitDataDone);
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// Loop forever
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while (1) {
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// Wait for queue message
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@ -229,26 +231,6 @@ static void overoSyncTask(void *parameters)
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}
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}
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static void transmitDataDone(bool crc_ok, uint8_t crc_val)
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{
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uint8_t *rx_buffer;
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static signed portBASE_TYPE xHigherPriorityTaskWoken;
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rx_buffer = overosync->transactions[overosync->active_transaction_id].rx_buffer;
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// Release the semaphore and start another transaction (which grabs semaphore again but then
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// returns instantly). Because this is called by the DMA ISR we need to be aware of context
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// switches.
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xSemaphoreGiveFromISR(overosync->transaction_lock, &xHigherPriorityTaskWoken);
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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overosync->transaction_done = true;
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// Parse the data from overo
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//for (uint32_t i = 0; rx_buffer[0] != 0 && i < sizeof(rx_buffer) ; i++)
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// UAVTalkProcessInputStream(uavTalkCon, rx_buffer[i]);
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}
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/**
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* Transmit data buffer to the modem or USB port.
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* \param[in] data Data buffer to send
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@ -256,7 +238,6 @@ static void transmitDataDone(bool crc_ok, uint8_t crc_val)
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* \return -1 on failure
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* \return number of bytes transmitted on success
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*/
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uint32_t too_long = 0;
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static int32_t packData(uint8_t * data, int32_t length)
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{
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uint8_t *tx_buffer;
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@ -276,7 +257,7 @@ static int32_t packData(uint8_t * data, int32_t length)
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// Get offset into buffer and copy contents
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tx_buffer = overosync->transactions[overosync->loading_transaction_id].tx_buffer +
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overosync->write_pointer;
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overosync->write_pointer;
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memcpy(tx_buffer, &tickTime, sizeof(tickTime));
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memcpy(tx_buffer + sizeof(tickTime),data,length);
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overosync->write_pointer += length + sizeof(tickTime);
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@ -285,37 +266,19 @@ static int32_t packData(uint8_t * data, int32_t length)
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xSemaphoreGive(overosync->buffer_lock);
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/* // When the NSS line rises while we are packing data then a transaction doesn't start
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// because that means we will be here very shortly afterwards (priority of task making that
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// not always perfectly true) schedule the transaction here.
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if (buffer_swap_failed && (PIOS_DELAY_DiffuS(buffer_swap_timeval) < 50)) {
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buffer_swap_failed = false;
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transmitData();
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} else if (buffer_swap_failed) {
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buffer_swap_failed = false;
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too_long++;
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}
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*/
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return length;
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}
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static int32_t transmitData()
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/**
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* Callback from the overo spi driver at the end of each packet
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*/
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static void transmitDataDone()
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{
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uint8_t *tx_buffer, *rx_buffer;
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static signed portBASE_TYPE xHigherPriorityTaskWoken;
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// Get this lock first so we don't swap buffers and then fail
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// to start
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if (xSemaphoreTake(overosync->transaction_lock, 0) == pdFALSE)
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return -1;
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// Get lock to manipulate buffers
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if(xSemaphoreTake(overosync->buffer_lock, 0) == pdFALSE) {
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xSemaphoreGiveFromISR(overosync->transaction_lock, &xHigherPriorityTaskWoken);
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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buffer_swap_failed = true;
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buffer_swap_timeval = PIOS_DELAY_GetRaw();
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return -2;
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return;
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}
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overosync->transaction_done = false;
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@ -325,18 +288,20 @@ static int32_t transmitData()
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overosync->loading_transaction_id = (overosync->loading_transaction_id + 1) %
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NELEMENTS(overosync->transactions);
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// Release the buffer lock
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xSemaphoreGive(overosync->buffer_lock);
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// Get the new buffers and configure the overo driver
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tx_buffer = overosync->transactions[overosync->active_transaction_id].tx_buffer;
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rx_buffer = overosync->transactions[overosync->active_transaction_id].rx_buffer;
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PIOS_Overo_SetNewBuffer((uint8_t *) tx_buffer, (uint8_t *) rx_buffer,
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sizeof(overosync->transactions[overosync->active_transaction_id].tx_buffer));
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// Prepare the new loading buffer
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memset(overosync->transactions[overosync->loading_transaction_id].tx_buffer, 0xff,
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sizeof(overosync->transactions[overosync->loading_transaction_id].tx_buffer));
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overosync->write_pointer = 0;
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xSemaphoreGiveFromISR(overosync->buffer_lock, &xHigherPriorityTaskWoken);
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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return PIOS_Overo_SetNewBuffer((uint8_t *) tx_buffer, (uint8_t *) rx_buffer, sizeof(overosync->transactions[overosync->active_transaction_id].tx_buffer), &transmitDataDone) == 0 ? 0 : -3;
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}
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/**
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@ -103,8 +103,6 @@ struct pios_overo_dev * overo_dev;
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*/
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int32_t PIOS_Overo_Init(const struct pios_overo_cfg * cfg)
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{
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uint32_t init_ssel = 0;
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PIOS_Assert(cfg);
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overo_dev = (struct pios_overo_dev *) PIOS_OVERO_alloc();
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@ -122,27 +120,23 @@ int32_t PIOS_Overo_Init(const struct pios_overo_cfg * cfg)
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/* only legal for single-slave config */
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PIOS_Assert(overo_dev->cfg->slave_count == 1);
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init_ssel = 1;
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SPI_SSOutputCmd(overo_dev->cfg->regs, (overo_dev->cfg->init.SPI_Mode == SPI_Mode_Master) ? ENABLE : DISABLE);
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/* Initialize the GPIO pins */
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/* note __builtin_ctz() due to the difference between GPIO_PinX and GPIO_PinSourceX */
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if (overo_dev->cfg->remap) {
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GPIO_PinAFConfig(overo_dev->cfg->sclk.gpio,
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__builtin_ctz(overo_dev->cfg->sclk.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->mosi.gpio,
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__builtin_ctz(overo_dev->cfg->mosi.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->miso.gpio,
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__builtin_ctz(overo_dev->cfg->miso.init.GPIO_Pin),
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overo_dev->cfg->remap);
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for (uint32_t i = 0; i < init_ssel; i++) {
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GPIO_PinAFConfig(overo_dev->cfg->ssel[i].gpio,
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__builtin_ctz(overo_dev->cfg->ssel[i].init.GPIO_Pin),
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overo_dev->cfg->remap);
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}
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}
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GPIO_PinAFConfig(overo_dev->cfg->sclk.gpio,
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__builtin_ctz(overo_dev->cfg->sclk.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->mosi.gpio,
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__builtin_ctz(overo_dev->cfg->mosi.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->miso.gpio,
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__builtin_ctz(overo_dev->cfg->miso.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->ssel[0].gpio,
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__builtin_ctz(overo_dev->cfg->ssel[0].init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_Init(overo_dev->cfg->sclk.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->sclk.init));
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GPIO_Init(overo_dev->cfg->mosi.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->mosi.init));
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GPIO_Init(overo_dev->cfg->miso.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->miso.init));
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@ -202,7 +196,7 @@ out_fail:
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* \return -1 if disabled SPI port selected
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* \return -3 if function has been called during an ongoing DMA transfer
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*/
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int32_t PIOS_Overo_SetNewBuffer(const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
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int32_t PIOS_Overo_SetNewBuffer(const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len)
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{
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid)
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@ -212,13 +206,19 @@ int32_t PIOS_Overo_SetNewBuffer(const uint8_t *send_buffer, uint8_t *receive_buf
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overo_dev->new_tx_buffer = (uint32_t) send_buffer;
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overo_dev->new_rx_buffer = (uint32_t) receive_buffer;
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/* Set callback function */
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overo_dev->callback = callback;
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/* No error */
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return overrun ? -1 : 0;
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}
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/**
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* Set the callback function
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*/
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int32_t PIOS_Overo_SetCallback(void *callback)
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{
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overo_dev->callback = callback;
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return 0;
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}
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/**
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* On the rising edge of NSS schedule a new transaction. This cannot be
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* done by the DMA complete because there is 150 us between that and the
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@ -54,7 +54,8 @@ struct pios_overo_dev {
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};
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extern int32_t PIOS_Overo_Init(const struct pios_overo_cfg * cfg);
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extern int32_t PIOS_Overo_SetNewBuffer(const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback);
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extern int32_t PIOS_Overo_SetCallback(void *callback);
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extern int32_t PIOS_Overo_SetNewBuffer(const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len);
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#endif /* PIOS_OVERO_H */
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