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Code Issues Releases Activity

Merge remote-tracking branch 'origin/next' into thread/OP-935_Changes_Basic_Stab

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This commit is contained in:
Fredrik Arvidsson 2013-05-08 13:42:30 +02:00
commit ec27296b1b
24 changed files with 401 additions and 178 deletions
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6
Makefile
View File

@ -198,7 +198,6 @@ export OPGCSSYNTHDIR := $(BUILD_DIR)/openpilotgcs-synthetics
# Define supported board lists
ALL_BOARDS := coptercontrol oplinkmini revolution osd revoproto simposix
ALL_BOARDS_BU := coptercontrol oplinkmini
# Short names of each board (used to display board name in parallel builds)
coptercontrol_short := 'cc '
@ -211,14 +210,13 @@ simposix_short := 'posx'
# SimPosix only builds on Linux so drop it from the list for
# all other platforms.
ifneq ($(UNAME), Linux)
ALL_BOARDS := $(filter-out simposix, $(ALL_BOARDS))
ALL_BOARDS_BU := $(filter-out simposix, $(ALL_BOARDS_BU))
ALL_BOARDS := $(filter-out simposix, $(ALL_BOARDS))
endif
# Start out assuming that we'll build fw, bl and bu for all boards
FW_BOARDS := $(ALL_BOARDS)
BL_BOARDS := $(ALL_BOARDS)
BU_BOARDS := $(ALL_BOARDS_BU)
BU_BOARDS := $(ALL_BOARDS)
EF_BOARDS := $(ALL_BOARDS)
# SimPosix doesn't have a BL, BU or EF target so we need to

1
flight/pios/inc/pios_bl_helper.h
View File

@ -36,6 +36,7 @@ extern uint8_t PIOS_BL_HELPER_FLASH_Ini();
extern uint32_t PIOS_BL_HELPER_CRC_Memory_Calc();
extern void PIOS_BL_HELPER_FLASH_Read_Description(uint8_t * array, uint8_t size);
extern uint8_t PIOS_BL_HELPER_FLASH_Start();
extern uint8_t PIOS_BL_HELPER_FLASH_Erase_Bootloader();
extern void PIOS_BL_HELPER_CRC_Ini();
#endif /* PIOS_BL_HELPER_H */

65
flight/pios/stm32f10x/pios_bl_helper.c
View File

@ -28,12 +28,13 @@
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "pios.h"
#include <pios.h>
#ifdef PIOS_INCLUDE_BL_HELPER
#include <pios_board_info.h>
#include "stm32f10x_flash.h"
#include <stm32f10x_flash.h>
#include <stdbool.h>
uint8_t *PIOS_BL_HELPER_FLASH_If_Read(uint32_t SectorAddress)
{
@ -41,38 +42,58 @@ uint8_t *PIOS_BL_HELPER_FLASH_If_Read(uint32_t SectorAddress)
}
#if defined(PIOS_INCLUDE_BL_HELPER_WRITE_SUPPORT)
static bool erase_flash(uint32_t startAddress, uint32_t endAddress);
uint8_t PIOS_BL_HELPER_FLASH_Ini()
{
FLASH_Unlock();
return 1;
FLASH_Unlock();
return 1;
}
uint8_t PIOS_BL_HELPER_FLASH_Start()
{
const struct pios_board_info * bdinfo = &pios_board_info_blob;
uint32_t pageAdress = bdinfo->fw_base;
uint8_t fail = FALSE;
while ((pageAdress < (bdinfo->fw_base + bdinfo->fw_size + bdinfo->desc_size))
|| (fail == TRUE)) {
for (int retry = 0; retry < MAX_DEL_RETRYS; ++retry) {
if (FLASH_ErasePage(pageAdress) == FLASH_COMPLETE) {
fail = FALSE;
break;
} else {
fail = TRUE;
}
const struct pios_board_info * bdinfo = &pios_board_info_blob;
uint32_t startAddress = bdinfo->fw_base;
uint32_t endAddress = bdinfo->fw_base + bdinfo->fw_size + bdinfo->desc_size;
}
bool success = erase_flash(startAddress, endAddress);
return (success) ? 1 : 0;
}
uint8_t PIOS_BL_HELPER_FLASH_Erase_Bootloader() {
/// Bootloader memory space erase
uint32_t startAddress = BL_BANK_BASE;
uint32_t endAddress = BL_BANK_BASE + BL_BANK_SIZE;
bool success = erase_flash(startAddress, endAddress);
return (success) ? 1 : 0;
}
static bool erase_flash(uint32_t startAddress, uint32_t endAddress) {
uint32_t pageAddress = startAddress;
uint8_t fail = false;
while ((pageAddress < endAddress) && (fail == false)) {
for (int retry = 0; retry < MAX_DEL_RETRYS; ++retry) {
if (FLASH_ErasePage(pageAddress) == FLASH_COMPLETE) {
fail = false;
break;
} else {
fail = true;
}
}
#ifdef STM32F10X_HD
pageAdress += 2048;
pageAddress += 2048;
#elif defined (STM32F10X_MD)
pageAdress += 1024;
pageAddress += 1024;
#endif
}
return (fail == TRUE) ? 0 : 1;
}
return !fail;
}
#endif
uint32_t PIOS_BL_HELPER_CRC_Memory_Calc()

3
flight/pios/stm32f10x/pios_sys.c
View File

@ -50,6 +50,9 @@ void PIOS_SYS_Init(void)
/* Setup STM32 system (RCC, clock, PLL and Flash configuration) - CMSIS Function */
SystemInit();
/* Init the delay system */
PIOS_DELAY_Init();
/* Enable GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and AFIO clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_AFIO, ENABLE);

2
flight/pios/stm32f4xx/libraries/CMSIS2/Device/ST/STM32F4xx/Source/osd/system_stm32f4xx.c
View File

@ -393,7 +393,7 @@ static void SetSysClock(void)
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

2
flight/pios/stm32f4xx/libraries/CMSIS2/Device/ST/STM32F4xx/Source/revolution/system_stm32f4xx.c
View File

@ -393,7 +393,7 @@ static void SetSysClock(void)
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

2
flight/pios/stm32f4xx/libraries/CMSIS2/Device/ST/STM32F4xx/Source/revoproto/system_stm32f4xx.c
View File

@ -393,7 +393,7 @@ static void SetSysClock(void)
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

3
flight/pios/stm32f4xx/library.mk
View File

@ -10,6 +10,9 @@ LINKER_SCRIPTS_APP = $(PIOS_DEVLIB)link_stm32f4xx_fw_memory.ld \
$(PIOS_DEVLIB)link_stm32f4xx_sections.ld
LINKER_SCRIPTS_BL = $(PIOS_DEVLIB)link_stm32f4xx_bl_memory.ld \
$(PIOS_DEVLIB)link_stm32f4xx_sections.ld
# _compat linker script are aimed at bootloader updater to guarantee to be compatible with earlier bootloaders.
LINKER_SCRIPTS_COMPAT = $(PIOS_DEVLIB)link_stm32f4xx_fw_memory.ld \
$(PIOS_DEVLIB)link_stm32f4xx_sections_compat.ld
# Compiler options implied by the F4xx
CDEFS += -DSTM32F4XX

2
flight/pios/stm32f4xx/link_stm32f4xx_sections.ld
View File

@ -83,7 +83,7 @@ SECTIONS
_irq_stack_end = . ;
*(.irqstack)
_irq_stack_top = . ;
} > SRAM
} > CCSRAM
/*

176
flight/pios/stm32f4xx/link_stm32f4xx_sections_compat.ld Normal file
View File

@ -0,0 +1,176 @@
/* Section Definitions */
SECTIONS
{
/*
* Vectors, code and constant data.
*/
.text :
{
PROVIDE (pios_isr_vector_table_base = .);
KEEP(*(.cpu_vectors)) /* CPU exception vectors */
KEEP(*(.io_vectors)) /* I/O interrupt vectors */
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
} > FLASH
/*
* Init section for UAVObjects.
*/
.initcalluavobj.init :
{
. = ALIGN(4);
__uavobj_initcall_start = .;
KEEP(*(.initcalluavobj.init))
. = ALIGN(4);
__uavobj_initcall_end = .;
} >FLASH
/*
* Module init section section
*/
.initcallmodule.init :
{
. = ALIGN(4);
__module_initcall_start = .;
KEEP(*(.initcallmodule.init))
. = ALIGN(4);
__module_initcall_end = .;
} >FLASH
/*
* C++ exception handling.
*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/*
* Markers for the end of the 'text' section and the in-flash start of
* non-constant data
*/
. = ALIGN(4);
_etext = .;
_sidata = .;
/*
* Board info structure, normally only generated by the bootloader but can
* be read by the application.
*/
PROVIDE(pios_board_info_blob = ORIGIN(BD_INFO));
.boardinfo :
{
. = ALIGN(4);
KEEP(*(.boardinfo))
. = ALIGN(ORIGIN(BD_INFO)+LENGTH(BD_INFO));
} > BD_INFO
/*
* Place the IRQ/bootstrap stack at the bottom of SRAM so that an overflow
* results in a hard fault.
*/
.istack (NOLOAD) :
{
. = ALIGN(4);
_irq_stack_end = . ;
*(.irqstack)
_irq_stack_top = . ;
} > SRAM
/*
* Non-const initialised data.
*/
.data : AT (_sidata)
{
. = ALIGN(4);
_sdata = .;
*(.data .data.*)
. = ALIGN(4);
_edata = . ;
} > SRAM
/*
* Uninitialised data (BSS + commons).
*/
.bss (NOLOAD) :
{
_sbss = . ;
*(.bss .bss.*)
*(COMMON)
_ebss = . ;
PROVIDE ( _end = _ebss ) ;
} > SRAM
/*
* The heap consumes the remainder of the SRAM.
*/
.heap (NOLOAD) :
{
. = ALIGN(4);
_sheap = . ;
/*
* This allows us to declare an object or objects up to the minimum acceptable
* heap size and receive a linker error if the space available for the heap is
* not sufficient.
*/
*(.heap)
/* extend the heap up to the top of SRAM */
. = ORIGIN(SRAM) + LENGTH(SRAM) - ABSOLUTE(_sheap);
_eheap = .;
} > SRAM
/*
* 'Fast' memory goes in the CCM SRAM
*/
.fast (NOLOAD) :
{
_sfast = . ;
*(.fast)
_efast = . ;
} > CCSRAM
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

78
flight/pios/stm32f4xx/pios_bl_helper.c
View File

@ -28,12 +28,12 @@
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "pios.h"
#include <pios.h>
#ifdef PIOS_INCLUDE_BL_HELPER
#include <pios_board_info.h>
#include "stm32f4xx_flash.h"
#include <stm32f4xx_flash.h>
#include <stdbool.h>
uint8_t *PIOS_BL_HELPER_FLASH_If_Read(uint32_t SectorAddress)
@ -42,6 +42,9 @@ uint8_t *PIOS_BL_HELPER_FLASH_If_Read(uint32_t SectorAddress)
}
#if defined(PIOS_INCLUDE_BL_HELPER_WRITE_SUPPORT)
static bool erase_flash(uint32_t startAddress, uint32_t endAddress);
uint8_t PIOS_BL_HELPER_FLASH_Ini()
{
FLASH_Unlock();
@ -138,35 +141,54 @@ static bool PIOS_BL_HELPER_FLASH_GetSectorInfo(uint32_t address, uint8_t * secto
uint8_t PIOS_BL_HELPER_FLASH_Start()
{
const struct pios_board_info * bdinfo = &pios_board_info_blob;
uint32_t pageAddress = bdinfo->fw_base;
bool fail = false;
while ((pageAddress < (bdinfo->fw_base + bdinfo->fw_size + bdinfo->desc_size))
&& (fail == false)) {
uint8_t sector_number;
uint32_t sector_start;
uint32_t sector_size;
if (!PIOS_BL_HELPER_FLASH_GetSectorInfo(pageAddress,
&sector_number,
&sector_start,
&sector_size)) {
/* We're asking for an invalid flash address */
PIOS_Assert(0);
}
for (int retry = 0; retry < MAX_DEL_RETRYS; ++retry) {
if (FLASH_EraseSector(sector_number, VoltageRange_3) == FLASH_COMPLETE) {
fail = false;
break;
} else {
fail = true;
}
uint32_t startAddress = bdinfo->fw_base;
uint32_t endAddress = bdinfo->fw_base + bdinfo->fw_size + bdinfo->desc_size;
}
/* Move to the next sector */
pageAddress += sector_size;
}
bool success = erase_flash(startAddress, endAddress);
return (fail == true) ? 0 : 1;
return (success) ? 1 : 0;
}
uint8_t PIOS_BL_HELPER_FLASH_Erase_Bootloader() {
/// Bootloader memory space erase
uint32_t startAddress = BL_BANK_BASE;
uint32_t endAddress = BL_BANK_BASE + BL_BANK_SIZE;
bool success = erase_flash(startAddress, endAddress);
return (success) ? 1 : 0;
}
static bool erase_flash(uint32_t startAddress, uint32_t endAddress)
{
uint32_t pageAddress = startAddress;
bool fail = false;
while ((pageAddress < endAddress) && (fail == false)) {
uint8_t sector_number;
uint32_t sector_start;
uint32_t sector_size;
if (!PIOS_BL_HELPER_FLASH_GetSectorInfo(pageAddress,
&sector_number,
&sector_start,
&sector_size)) {
/* We're asking for an invalid flash address */
PIOS_Assert(0);
}
for (int retry = 0; retry < MAX_DEL_RETRYS; ++retry) {
if (FLASH_EraseSector(sector_number, VoltageRange_3) == FLASH_COMPLETE) {
fail = false;
break;
} else {
fail = true;
}
}
/* Move to the next sector */
pageAddress += sector_size;
}
return !fail;
}
#endif
uint32_t PIOS_BL_HELPER_CRC_Memory_Calc()

3
flight/targets/boards/coptercontrol/bootloader/main.c
View File

@ -156,8 +156,7 @@ int main() {
if (stopwatch > 50 * 1000 * 1000)
stopwatch = 0;
if ((stopwatch > 6 * 1000 * 1000) && (DeviceState
== BLidle))
if ((stopwatch > 6 * 1000 * 1000) && ((DeviceState == BLidle) || (DeviceState == DFUidle && !USB_connected)))
JumpToApp = TRUE;
processRX();

2
flight/targets/boards/osd/board-info.mk
View File

@ -1,6 +1,6 @@
BOARD_TYPE := 0x05
BOARD_REVISION := 0x01
BOOTLOADER_VERSION := 0x04
BOOTLOADER_VERSION := 0x05
HW_TYPE := 0x00
MCU := cortex-m4

6
flight/targets/boards/osd/bootloader/main.c
View File

@ -170,7 +170,11 @@ void jump_to_app() {
const struct pios_board_info * bdinfo = &pios_board_info_blob;
PIOS_LED_On(PIOS_LED_HEARTBEAT);
if (((*(__IO uint32_t*) bdinfo->fw_base) & 0x2FFE0000) == 0x20000000) { /* Jump to user application */
// Look at cm3_vectors struct in startup. In a fw image the first uint32_t contains the address of the top of irqstack
uint32_t fwIrqStackBase = (*(__IO uint32_t*) bdinfo->fw_base) & 0xFFFE0000;
// Check for the two possible irqstack locations (sram or core coupled sram)
if ( fwIrqStackBase == 0x20000000 || fwIrqStackBase == 0x10000000) {
/* Jump to user application */
FLASH_Lock();
RCC_APB2PeriphResetCmd(0xffffffff, ENABLE);
RCC_APB1PeriphResetCmd(0xffffffff, ENABLE);

4
flight/targets/boards/revolution/board-info.mk
View File

@ -1,6 +1,6 @@
BOARD_TYPE := 0x09
BOARD_REVISION := 0x03
BOOTLOADER_VERSION := 0x04
BOOTLOADER_VERSION := 0x05
HW_TYPE := 0x00
MCU := cortex-m4
@ -19,7 +19,7 @@ BL_BANK_SIZE := 0x00008000 # Should include BD_INFO region
# Leave the remaining 16KB and 64KB sectors for other uses
FW_BANK_BASE := 0x08020000 # Start of firmware flash
FW_BANK_SIZE := 0x00040000 # Should include FW_DESC_SIZE
FW_BANK_SIZE := 0x00060000 # Should include FW_DESC_SIZE
FW_DESC_SIZE := 0x00000064

9
flight/targets/boards/revolution/bootloader/main.c
View File

@ -161,8 +161,7 @@ int main() {
if (stopwatch > 50 * 1000 * 1000)
stopwatch = 0;
if ((stopwatch > 6 * 1000 * 1000) && (DeviceState
== BLidle))
if ((stopwatch > 6 * 1000 * 1000) && ((DeviceState == BLidle) || (DeviceState == DFUidle && !USB_connected)))
JumpToApp = true;
processRX();
@ -174,7 +173,11 @@ void jump_to_app() {
const struct pios_board_info * bdinfo = &pios_board_info_blob;
PIOS_LED_On(PIOS_LED_HEARTBEAT);
if (((*(__IO uint32_t*) bdinfo->fw_base) & 0x2FFE0000) == 0x20000000) { /* Jump to user application */
// Look at cm3_vectors struct in startup. In a fw image the first uint32_t contains the address of the top of irqstack
uint32_t fwIrqStackBase = (*(__IO uint32_t*) bdinfo->fw_base) & 0xFFFE0000;
// Check for the two possible irqstack locations (sram or core coupled sram)
if ( fwIrqStackBase == 0x20000000 || fwIrqStackBase == 0x10000000) {
/* Jump to user application */
FLASH_Lock();
RCC_APB2PeriphResetCmd(0xffffffff, ENABLE);
RCC_APB1PeriphResetCmd(0xffffffff, ENABLE);

4
flight/targets/boards/revoproto/board-info.mk
View File

@ -1,6 +1,6 @@
BOARD_TYPE := 0x09
BOARD_REVISION := 0x02
BOOTLOADER_VERSION := 0x04
BOOTLOADER_VERSION := 0x05
HW_TYPE := 0x00
MCU := cortex-m4
@ -19,7 +19,7 @@ BL_BANK_SIZE := 0x00008000 # Should include BD_INFO region
# Leave the remaining 16KB and 64KB sectors for other uses
FW_BANK_BASE := 0x08020000 # Start of firmware flash
FW_BANK_SIZE := 0x00040000 # Should include FW_DESC_SIZE
FW_BANK_SIZE := 0x00060000 # Should include FW_DESC_SIZE
FW_DESC_SIZE := 0x00000064

9
flight/targets/boards/revoproto/bootloader/main.c
View File

@ -161,8 +161,7 @@ int main() {
if (stopwatch > 50 * 1000 * 1000)
stopwatch = 0;
if ((stopwatch > 6 * 1000 * 1000) && (DeviceState
== BLidle))
if ((stopwatch > 6 * 1000 * 1000) && ((DeviceState == BLidle) || (DeviceState == DFUidle && !USB_connected)))
JumpToApp = true;
processRX();
@ -174,7 +173,11 @@ void jump_to_app() {
const struct pios_board_info * bdinfo = &pios_board_info_blob;
PIOS_LED_On(PIOS_LED_HEARTBEAT);
if (((*(__IO uint32_t*) bdinfo->fw_base) & 0x2FFE0000) == 0x20000000) { /* Jump to user application */
// Look at cm3_vectors struct in startup. In a fw image the first uint32_t contains the address of the top of irqstack
uint32_t fwIrqStackBase = (*(__IO uint32_t*) bdinfo->fw_base) & 0xFFFE0000;
// Check for the two possible irqstack locations (sram or core coupled sram)
if ( fwIrqStackBase == 0x20000000 || fwIrqStackBase == 0x10000000) {
/* Jump to user application */
FLASH_Lock();
RCC_APB2PeriphResetCmd(0xffffffff, ENABLE);
RCC_APB1PeriphResetCmd(0xffffffff, ENABLE);

11
flight/targets/common/bootloader_updater/Makefile
View File

@ -39,7 +39,6 @@ HWDEFSINC = ../../boards/$(BOARD_NAME)
# Use file-extension c for "c-only"-files
SRC += $(OPSYSTEM)/main.c
SRC += $(OPSYSTEM)/pios_board.c
## PIOS Hardware
ifeq ($(MCU),cortex-m3)
include $(PIOS)/stm32f10x/library.mk
@ -47,6 +46,16 @@ ifeq ($(MCU),cortex-m3)
# Set linker-script name depending on selected submodel name
LDFLAGS += -T$(LINKER_SCRIPTS_PATH)/link_$(BOARD)_memory.ld
LDFLAGS += -T$(LINKER_SCRIPTS_PATH)/link_$(BOARD)_sections.ld
else ifeq ($(MCU),cortex-m4)
include $(PIOS)/stm32f4xx/library.mk
# Set linker-script name depending on selected submodel name
LDFLAGS += -T$(PIOS_DEVLIB)/link_stm32f4xx_fw_memory.ld
# Using the _compat ld script ensure that the bootloader updated is compiled with irqstack in sram
# This allow to be used with bootloader earlier than rel5
LDFLAGS += -T$(PIOS_DEVLIB)/link_stm32f4xx_sections_compat.ld
SRC += $(HWDEFSINC)/firmware/cm3_fault_handlers.c
SRC += $(HWDEFSINC)/firmware/dcc_stdio.c
else
$(error Unsupported MCU for BootloaderUpdater: $(MCU))
endif

2
flight/targets/common/bootloader_updater/inc/pios_config.h
View File

@ -34,9 +34,9 @@
#define PIOS_INCLUDE_DELAY
#define PIOS_INCLUDE_SYS
#define PIOS_INCLUDE_IRQ
#define PIOS_INCLUDE_GPIO
#define PIOS_INCLUDE_LED
#define PIOS_INCLUDE_BL_HELPER
#define PIOS_INCLUDE_BL_HELPER_WRITE_SUPPORT
#endif /* PIOS_CONFIG_H */

149
flight/targets/common/bootloader_updater/main.c
View File

@ -29,6 +29,7 @@
#include <pios.h>
#include <pios_board_info.h>
#include <stdbool.h>
#include <pios_bl_helper.h>
#define MAX_WRI_RETRYS 3
/* Prototype of PIOS_Board_Init() function */
@ -43,105 +44,87 @@ void error(int, int);
extern uint32_t _binary_start;
extern uint32_t _binary_end;
extern uint32_t _binary_size;
const uint32_t * embedded_image_start = (uint32_t *) &(_binary_start);
const uint32_t * embedded_image_end = (uint32_t *) &(_binary_end);
const uint32_t *embedded_image_start = (uint32_t *) &(_binary_start);
const uint32_t *embedded_image_end = (uint32_t *) &(_binary_end);
const uint32_t embedded_image_size = (uint32_t) &(_binary_size);
int main()
{
PIOS_SYS_Init();
PIOS_Board_Init();
PIOS_LED_On(PIOS_LED_HEARTBEAT);
PIOS_DELAY_WaitmS(3000);
PIOS_LED_Off(PIOS_LED_HEARTBEAT);
PIOS_SYS_Init();
PIOS_Board_Init();
PIOS_LED_On(PIOS_LED_HEARTBEAT);
PIOS_DELAY_WaitmS(3000);
PIOS_LED_Off(PIOS_LED_HEARTBEAT);
/// Self overwrite check
uint32_t base_address = SCB->VTOR;
if ((0x08000000 + embedded_image_size) > base_address)
error(PIOS_LED_HEARTBEAT, 1);
///
/// Self overwrite check
uint32_t base_address = SCB ->VTOR;
if ((BL_BANK_BASE + embedded_image_size) > base_address)
error(PIOS_LED_HEARTBEAT, 1);
///
/*
* Make sure the bootloader we're carrying is for the same
* board type and board revision as the one we're running on.
*
* Assume the bootloader in flash and the bootloader contained in
* the updater both carry a board_info_blob at the end of the image.
*/
/*
* Make sure the bootloader we're carrying is for the same
* board type and board revision as the one we're running on.
*
* Assume the bootloader in flash and the bootloader contained in
* the updater both carry a board_info_blob at the end of the image.
*/
/* Calculate how far the board_info_blob is from the beginning of the bootloader */
uint32_t board_info_blob_offset = (uint32_t) &pios_board_info_blob - (uint32_t)0x08000000;
/* Calculate how far the board_info_blob is from the beginning of the bootloader */
uint32_t board_info_blob_offset = (uint32_t) &pios_board_info_blob - (uint32_t) BL_BANK_BASE;
/* Use the same offset into our embedded bootloader image */
struct pios_board_info * new_board_info_blob = (struct pios_board_info *)
((uint32_t)embedded_image_start + board_info_blob_offset);
/* Use the same offset into our embedded bootloader image */
struct pios_board_info *new_board_info_blob = (struct pios_board_info *) ((uint32_t) embedded_image_start + board_info_blob_offset);
/* Compare the two board info blobs to make sure they're for the same HW revision */
if ((pios_board_info_blob.magic != new_board_info_blob->magic) ||
(pios_board_info_blob.board_type != new_board_info_blob->board_type) ||
(pios_board_info_blob.board_rev != new_board_info_blob->board_rev)) {
error(PIOS_LED_HEARTBEAT, 2);
}
/* Compare the two board info blobs to make sure they're for the same HW revision */
if ((pios_board_info_blob.magic != new_board_info_blob->magic) ||
(pios_board_info_blob.board_type != new_board_info_blob->board_type) ||
(pios_board_info_blob.board_rev != new_board_info_blob->board_rev)) {
error(PIOS_LED_HEARTBEAT, 2);
}
/* Embedded bootloader looks like it's the right one for this HW, proceed... */
/* Embedded bootloader looks like it's the right one for this HW, proceed... */
FLASH_Unlock();
FLASH_Unlock();
/// Bootloader memory space erase
uint32_t pageAddress;
pageAddress = 0x08000000;
bool fail = false;
while ((pageAddress < base_address) && (fail == false)) {
for (int retry = 0; retry < MAX_DEL_RETRYS; ++retry) {
if (FLASH_ErasePage(pageAddress) == FLASH_COMPLETE) {
fail = false;
break;
} else {
fail = true;
}
}
#ifdef STM32F10X_HD
pageAddress += 2048;
#elif defined (STM32F10X_MD)
pageAddress += 1024;
#endif
}
bool fail;
if (fail == true)
error(PIOS_LED_HEARTBEAT, 3);
fail = (PIOS_BL_HELPER_FLASH_Erase_Bootloader() != 1);
if (fail == true){
error(PIOS_LED_HEARTBEAT, 3);
}
///
/// Bootloader programing
for (uint32_t offset = 0; offset < embedded_image_size / sizeof(uint32_t); ++offset) {
bool result = false;
PIOS_LED_Toggle(PIOS_LED_HEARTBEAT);
for (uint8_t retry = 0; retry < MAX_WRI_RETRYS; ++retry) {
if (result == false) {
result = (FLASH_ProgramWord(BL_BANK_BASE + (offset * 4), embedded_image_start[offset]) == FLASH_COMPLETE);
}
}
if (result == false) {
error(PIOS_LED_HEARTBEAT, 4);
}
}
///
for (uint8_t x = 0; x < 3; ++x) {
PIOS_LED_On(PIOS_LED_HEARTBEAT);
PIOS_DELAY_WaitmS(1000);
PIOS_LED_Off(PIOS_LED_HEARTBEAT);
PIOS_DELAY_WaitmS(1000);
}
///
/// Bootloader programing
for (uint32_t offset = 0; offset < embedded_image_size / sizeof(uint32_t); ++offset) {
bool result = false;
PIOS_LED_Toggle(PIOS_LED_HEARTBEAT);
for (uint8_t retry = 0; retry < MAX_WRI_RETRYS; ++retry) {
if (result == false) {
result = (FLASH_ProgramWord(0x08000000 + (offset * 4), embedded_image_start[offset])
== FLASH_COMPLETE) ? true : false;
}
}
if (result == false)
error(PIOS_LED_HEARTBEAT, 4);
}
///
for (uint8_t x = 0; x < 3; ++x) {
PIOS_LED_On(PIOS_LED_HEARTBEAT);
PIOS_DELAY_WaitmS(1000);
PIOS_LED_Off(PIOS_LED_HEARTBEAT);
PIOS_DELAY_WaitmS(1000);
}
/// Invalidate the bootloader updater so we won't run
/// the update again on the next power cycle.
FLASH_ProgramWord(base_address, 0);
FLASH_Lock();
/// Invalidate the bootloader updater so we won't run
/// the update again on the next power cycle.
FLASH_ProgramWord(base_address, 0);
FLASH_Lock();
for (;;) {
PIOS_DELAY_WaitmS(1000);
}
for (;;) {
PIOS_DELAY_WaitmS(1000);
}
}
@ -157,4 +140,4 @@ void error(int led, int code)
}
PIOS_DELAY_WaitmS(3000);
}
}
}

12
flight/targets/common/bootloader_updater/pios_board.c
View File

@ -38,15 +38,6 @@
void PIOS_Board_Init(void) {
const struct pios_board_info * bdinfo = &pios_board_info_blob;
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* Delay system */
PIOS_DELAY_Init();
/* LEDs */
#if defined(PIOS_INCLUDE_LED)
const struct pios_led_cfg * led_cfg = PIOS_BOARD_HW_DEFS_GetLedCfg(bdinfo->board_rev);
@ -55,5 +46,8 @@ void PIOS_Board_Init(void) {
#endif /* PIOS_INCLUDE_LED */
/* Initialize the PiOS library */
#if defined(PIOS_INCLUDE_GPIO)
PIOS_GPIO_Init();
#endif /* PIOS_INCLUDE_GPIO */
}

8
make/boot-defs.mk
View File

@ -107,14 +107,8 @@ EXTRA_LIBDIRS +=
# EXTRA_LIBS = newlib-lpc
EXTRA_LIBS +=
# Provide (only) the bootloader with board-specific defines
BLONLY_CDEFS += -DBOARD_TYPE=$(BOARD_TYPE)
BLONLY_CDEFS += -DBOARD_REVISION=$(BOARD_REVISION)
BLONLY_CDEFS += -DHW_TYPE=$(HW_TYPE)
BLONLY_CDEFS += -DBOOTLOADER_VERSION=$(BOOTLOADER_VERSION)
# Compiler flags
CDEFS += $(BLONLY_CDEFS)
CDEFS +=
# Set linker-script name depending on selected submodel name
ifeq ($(MCU),cortex-m3)

20
make/common-defs.mk
View File

@ -95,11 +95,6 @@ endif
#ADEFS = -DUSE_IRQ_ASM_WRAPPER
ADEFS = -D__ASSEMBLY__
# Provide board-specific defines
CDEFS += -DFW_BANK_BASE=$(FW_BANK_BASE)
CDEFS += -DFW_BANK_SIZE=$(FW_BANK_SIZE)
CDEFS += -DFW_DESC_SIZE=$(FW_DESC_SIZE)
# Compiler flag to set the C Standard level.
# c89 - "ANSI" C
# gnu89 - c89 plus GCC extensions
@ -129,6 +124,21 @@ CFLAGS += -Werror
CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) -I.
CFLAGS += -Wa,-adhlns=$(addprefix $(OUTDIR)/, $(notdir $(addsuffix .lst, $(basename $<))))
# Provides board-specific defines
BOARD_CDEFS += -DBOARD_TYPE=$(BOARD_TYPE)
BOARD_CDEFS += -DBOARD_REVISION=$(BOARD_REVISION)
BOARD_CDEFS += -DHW_TYPE=$(HW_TYPE)
BOARD_CDEFS += -DBOOTLOADER_VERSION=$(BOOTLOADER_VERSION)
BOARD_CDEFS += -DFW_BANK_BASE=$(FW_BANK_BASE)
BOARD_CDEFS += -DFW_BANK_SIZE=$(FW_BANK_SIZE)
BOARD_CDEFS += -DFW_DESC_SIZE=$(FW_DESC_SIZE)
BOARD_CDEFS += -DBL_BANK_BASE=$(BL_BANK_BASE)
BOARD_CDEFS += -DBL_BANK_SIZE=$(BL_BANK_SIZE)
BOARD_CDEFS += -DBL_DESC_SIZE=$(BL_DESC_SIZE)
CDEFS += $(BOARD_CDEFS)
ifeq ($(DEBUG), YES)
CFLAGS += -DDEBUG
else