diff --git a/flight/AHRS/Makefile b/flight/AHRS/Makefile new file mode 100644 index 000000000..0e70e1895 --- /dev/null +++ b/flight/AHRS/Makefile @@ -0,0 +1,559 @@ + ##### + # Project: OpenPilot AHRS + # + # + # Makefile for OpenPilot AHRS project + # + # The OpenPilot Team, http://www.openpilot.org, Copyright (C) 2009. + # + # + # This program is free software; you can redistribute it and/or modify + # it under the terms of the GNU General Public License as published by + # the Free Software Foundation; either version 3 of the License, or + # (at your option) any later version. + # + # This program is distributed in the hope that it will be useful, but + # WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + # or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + # for more details. + # + # You should have received a copy of the GNU General Public License along + # with this program; if not, write to the Free Software Foundation, Inc., + # 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ##### + + +# Set developer code and compile options +# Set to YES for debugging +DEBUG = YES +# Set to YES when using Code Sourcery toolchain +CODE_SOURCERY = YES + +# Toolchain prefix (i.e arm-elf- -> arm-elf-gcc.exe) +TCHAIN_PREFIX = arm-none-eabi- + +ifeq ($(CODE_SOURCERY), YES) +REMOVE_CMD = cs-rm +else +REMOVE_CMD = rm +endif + +FLASH_TOOL = OPENOCD + +# YES enables -mthumb option to flags for source-files listed +# in SRC and CPPSRC +USE_THUMB_MODE = YES + +# MCU name, submodel and board +# - MCU used for compiler-option (-mcpu) +# - MODEL used for linker-script name (-T) and passed as define +# - BOARD just passed as define (optional) +MCU = cortex-m3 +CHIP = STM32F103CBT +MODEL = MD +BOARD = STM32103CB_AHRS + +# Directory for output files (lst, obj, dep, elf, sym, map, hex, bin etc.) +OUTDIR = Build + +# Target file name (without extension). +TARGET = AHRS + +# Paths +AHRS = ./ +AHRSINC = $(AHRS)/inc +PIOS = ../PiOS +PIOSINC = $(PIOS)/inc +PIOSSTM32F10X = $(PIOS)/STM32F10x +PIOSCOMMON = $(PIOS)/Common +APPLIBDIR = ../Libraries +STMLIBDIR = $(APPLIBDIR) +STMSPDDIR = $(STMLIBDIR)/STM32F10x_StdPeriph_Driver +STMUSBDIR = $(STMLIBDIR)/STM32_USB-FS-Device_Driver +STMSPDSRCDIR = $(STMSPDDIR)/src +STMSPDINCDIR = $(STMSPDDIR)/inc +CMSISDIR = $(STMLIBDIR)/CMSIS/Core/CM3 + + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files + +## AHRS: +SRC = ahrs.c + +## PIOS Hardware (STM32F10x) +SRC += $(PIOSSTM32F10X)/pios_sys.c +SRC += $(PIOSSTM32F10X)/pios_led.c +SRC += $(PIOSSTM32F10X)/pios_delay.c +SRC += $(PIOSSTM32F10X)/pios_usart.c +SRC += $(PIOSSTM32F10X)/pios_irq.c +SRC += $(PIOSSTM32F10X)/pios_adc.c +SRC += $(PIOSSTM32F10X)/pios_spi.c + +## PIOS Hardware (Common) +SRC += $(PIOSCOMMON)/pios_com.c +SRC += $(PIOSCOMMON)/printf-stdarg.c + +## CMSIS for STM32 +SRC += $(CMSISDIR)/core_cm3.c +SRC += $(CMSISDIR)/system_stm32f10x.c + +## Used parts of the STM-Library +SRC += $(STMSPDSRCDIR)/stm32f10x_adc.c +SRC += $(STMSPDSRCDIR)/stm32f10x_bkp.c +SRC += $(STMSPDSRCDIR)/stm32f10x_crc.c +SRC += $(STMSPDSRCDIR)/stm32f10x_dac.c +SRC += $(STMSPDSRCDIR)/stm32f10x_dma.c +SRC += $(STMSPDSRCDIR)/stm32f10x_exti.c +SRC += $(STMSPDSRCDIR)/stm32f10x_flash.c +SRC += $(STMSPDSRCDIR)/stm32f10x_gpio.c +SRC += $(STMSPDSRCDIR)/stm32f10x_i2c.c +SRC += $(STMSPDSRCDIR)/stm32f10x_pwr.c +SRC += $(STMSPDSRCDIR)/stm32f10x_rcc.c +SRC += $(STMSPDSRCDIR)/stm32f10x_rtc.c +SRC += $(STMSPDSRCDIR)/stm32f10x_spi.c +SRC += $(STMSPDSRCDIR)/stm32f10x_tim.c +SRC += $(STMSPDSRCDIR)/stm32f10x_usart.c +SRC += $(STMSPDSRCDIR)/misc.c + +# List C source files here which must be compiled in ARM-Mode (no -mthumb). +# use file-extension c for "c-only"-files +## just for testing, timer.c could be compiled in thumb-mode too +SRCARM = + +# List C++ source files here. +# use file-extension .cpp for C++-files (not .C) +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension .cpp for C++-files (not .C) +#CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = $(PIOSSTM32F10X)/startup_stm32f10x_$(MODEL).S + +# List Assembler source files here which must be assembled in ARM-Mode.. +ASRCARM = + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS += $(PIOS) +EXTRAINCDIRS += $(PIOSINC) +EXTRAINCDIRS += $(PIOSSTM32F10X) +EXTRAINCDIRS += $(PIOSCOMMON) +EXTRAINCDIRS += $(STMSPDINCDIR) +EXTRAINCDIRS += $(CMSISDIR) +EXTRAINCDIRS += $(AHRSINC) + +# List any extra directories to look for library files here. +# Also add directories where the linker should search for +# includes from linker-script to the list +# Each directory must be seperated by a space. +EXTRA_LIBDIRS = + +# Extra Libraries +# Each library-name must be seperated by a space. +# i.e. to link with libxyz.a, libabc.a and libefsl.a: +# EXTRA_LIBS = xyz abc efsl +# for newlib-lpc (file: libnewlibc-lpc.a): +# EXTRA_LIBS = newlib-lpc +EXTRA_LIBS = + +# Path to Linker-Scripts +LINKERSCRIPTPATH = $(PIOSSTM32F10X) + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) + +ifeq ($(DEBUG),YES) +OPT = 0 +else +OPT = s +endif + +# Output format. (can be ihex or binary or both) +# binary to create a load-image in raw-binary format i.e. for SAM-BA, +# ihex to create a load-image in Intel hex format +#LOADFORMAT = ihex +#LOADFORMAT = binary +LOADFORMAT = both + +# Debugging format. +DEBUGF = dwarf-2 + +# Place project-specific -D (define) and/or +# -U options for C here. +CDEFS = -DSTM32F10X_$(MODEL) +CDEFS += -DUSE_STDPERIPH_DRIVER +CDEFS += -DUSE_$(BOARD) + +# Place project-specific -D and/or -U options for +# Assembler with preprocessor here. +#ADEFS = -DUSE_IRQ_ASM_WRAPPER +ADEFS = -D__ASSEMBLY__ + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +#----- + +# Compiler flags. + +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) + +ifeq ($(DEBUG),YES) +CFLAGS = -g$(DEBUGF) +endif + +CFLAGS += -O$(OPT) +CFLAGS += -mcpu=$(MCU) -mthumb +CFLAGS += $(CDEFS) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) -I. + +CFLAGS += -mapcs-frame +CFLAGS += -fomit-frame-pointer +ifeq ($(CODE_SOURCERY), YES) +CFLAGS += -fpromote-loop-indices +endif + +CFLAGS += -Wall +CFLAGS += -Wa,-adhlns=$(addprefix $(OUTDIR)/, $(notdir $(addsuffix .lst, $(basename $<)))) +# Compiler flags to generate dependency files: +CFLAGS += -MD -MP -MF $(OUTDIR)/dep/$(@F).d + +# flags only for C +#CONLYFLAGS += -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlns: create listing +ASFLAGS = -mcpu=$(MCU) -mthumb -I. -x assembler-with-cpp +ASFLAGS += $(ADEFS) +ASFLAGS += -Wa,-adhlns=$(addprefix $(OUTDIR)/, $(notdir $(addsuffix .lst, $(basename $<)))) +ASFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +MATH_LIB = -lm + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -nostartfiles -Wl,-Map=$(OUTDIR)/$(TARGET).map,--cref,--gc-sections +LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS)) +LDFLAGS += -lc +LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS)) +LDFLAGS += $(MATH_LIB) +LDFLAGS += -lc -lgcc + +# Set linker-script name depending on selected submodel name +LDFLAGS +=-T$(LINKERSCRIPTPATH)/link_stm32f10x_$(MODEL).ld + +# --------------------------------------------------------------------------- +# Options for OpenOCD flash-programming +# see openocd.pdf/openocd.texi for further information +# +OOCD_LOADFILE+=$(OUTDIR)/$(TARGET).elf +# if OpenOCD is in the $PATH just set OPENOCDEXE=openocd +OOCD_EXE=openocd +# debug level +OOCD_CL=-d0 +# interface and board/target settings (using the OOCD target-library here) +OOCD_CL+=-f project/OpenOCD/floss-jtag.cfg -f project/OpenOCD/stm32.cfg +# initialize +OOCD_CL+=-c init +# show the targets +OOCD_CL+=-c targets +# commands to prepare flash-write +OOCD_CL+= -c "reset halt" +# flash erase +OOCD_CL+=-c "stm32x mass_erase 0" +# flash-write +OOCD_CL+=-c "flash write_image $(OOCD_LOADFILE)" +# Verify +OOCD_CL+=-c "verify_image $(OOCD_LOADFILE)" +# reset target +OOCD_CL+=-c "reset run" +# terminate OOCD after programming +OOCD_CL+=-c shutdown +# --------------------------------------------------------------------------- + + +# Define programs and commands. +CC = $(TCHAIN_PREFIX)gcc +CPP = $(TCHAIN_PREFIX)g++ +AR = $(TCHAIN_PREFIX)ar +OBJCOPY = $(TCHAIN_PREFIX)objcopy +OBJDUMP = $(TCHAIN_PREFIX)objdump +SIZE = $(TCHAIN_PREFIX)size +NM = $(TCHAIN_PREFIX)nm +REMOVE = $(REMOVE_CMD) -f +###SHELL = sh +###COPY = cp + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------" +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after build: +MSG_LOAD_FILE = Creating load file: +MSG_EXTENDED_LISTING = Creating Extended Listing/Disassembly: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = "**** Linking :" +MSG_COMPILING = "**** Compiling C :" +MSG_COMPILING_ARM = "**** Compiling C (ARM-only):" +MSG_COMPILINGCPP = "Compiling C++ :" +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = "**** Assembling:" +MSG_ASSEMBLING_ARM = "****Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_FORMATERROR = Can not handle output-format +MSG_ASMFROMC = "Creating asm-File from C-Source:" +MSG_ASMFROMC_ARM = "Creating asm-File from C-Source (ARM-only):" + +# List of all source files. +ALLSRC = $(ASRCARM) $(ASRC) $(SRCARM) $(SRC) $(CPPSRCARM) $(CPPSRC) +# List of all source files without directory and file-extension. +ALLSRCBASE = $(notdir $(basename $(ALLSRC))) + +# Define all object files. +ALLOBJ = $(addprefix $(OUTDIR)/, $(addsuffix .o, $(ALLSRCBASE))) + +# Define all listing files (used for make clean). +LSTFILES = $(addprefix $(OUTDIR)/, $(addsuffix .lst, $(ALLSRCBASE))) +# Define all depedency-files (used for make clean). +DEPFILES = $(addprefix $(OUTDIR)/dep/, $(addsuffix .o.d, $(ALLSRCBASE))) + +elf: $(OUTDIR)/$(TARGET).elf +lss: $(OUTDIR)/$(TARGET).lss +sym: $(OUTDIR)/$(TARGET).sym +hex: $(OUTDIR)/$(TARGET).hex +bin: $(OUTDIR)/$(TARGET).bin + +# Default target. +#all: begin gccversion sizebefore build sizeafter finished end +all: begin gccversion build sizeafter finished end + +ifeq ($(LOADFORMAT),ihex) +build: elf hex lss sym +else +ifeq ($(LOADFORMAT),binary) +build: elf bin lss sym +else +ifeq ($(LOADFORMAT),both) +build: elf hex bin lss sym +else +$(error "$(MSG_FORMATERROR) $(FORMAT)") +endif +endif +endif + + +# Eye candy. +begin: +## @echo + @echo $(MSG_BEGIN) + +finished: +## @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) +## @echo + +# Display sizes of sections. +ELFSIZE = $(SIZE) -A $(OUTDIR)/$(TARGET).elf +##ELFSIZE = $(SIZE) --format=Berkeley --common $(OUTDIR)/$(TARGET).elf +sizebefore: +# @if [ -f $(OUTDIR)/$(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: +# @if [ -f $(OUTDIR)/$(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + @echo $(MSG_SIZE_AFTER) + $(ELFSIZE) + +# Display compiler version information. +gccversion : + @$(CC) --version +# @echo $(ALLOBJ) + +# Program the device. +ifeq ($(FLASH_TOOL),OPENOCD) +# Program the device with Dominic Rath's OPENOCD in "batch-mode", needs cfg and "reset-script". +program: $(OUTDIR)/$(TARGET).elf + @echo "Programming with OPENOCD" + $(OOCD_EXE) $(OOCD_CL) +endif + +# Create final output file (.hex) from ELF output file. +%.hex: %.elf +## @echo + @echo $(MSG_LOAD_FILE) $@ + $(OBJCOPY) -O ihex $< $@ + +# Create final output file (.bin) from ELF output file. +%.bin: %.elf +## @echo + @echo $(MSG_LOAD_FILE) $@ + $(OBJCOPY) -O binary $< $@ + +# Create extended listing file/disassambly from ELF output file. +# using objdump testing: option -C +%.lss: %.elf +## @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C -r $< > $@ +# $(OBJDUMP) -x -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf +## @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(ALLOBJ) +%.elf: $(ALLOBJ) + @echo + @echo $(MSG_LINKING) $@ +# use $(CC) for C-only projects or $(CPP) for C++-projects: + $(CC) $(THUMB) $(CFLAGS) $(ALLOBJ) --output $@ $(LDFLAGS) +# $(CPP) $(THUMB) $(CFLAGS) $(ALLOBJ) --output $@ $(LDFLAGS) + + +# Assemble: create object files from assembler source files. +define ASSEMBLE_TEMPLATE +$(OUTDIR)/$(notdir $(basename $(1))).o : $(1) +## @echo + @echo $(MSG_ASSEMBLING) $$< "->" $$@ + $(CC) -c $(THUMB) $$(ASFLAGS) $$< -o $$@ +endef +$(foreach src, $(ASRC), $(eval $(call ASSEMBLE_TEMPLATE, $(src)))) + +# Assemble: create object files from assembler source files. ARM-only +define ASSEMBLE_ARM_TEMPLATE +$(OUTDIR)/$(notdir $(basename $(1))).o : $(1) +## @echo + @echo $(MSG_ASSEMBLING_ARM) $$< "->" $$@ + $(CC) -c $$(ASFLAGS) $$< -o $$@ +endef +$(foreach src, $(ASRCARM), $(eval $(call ASSEMBLE_ARM_TEMPLATE, $(src)))) + + +# Compile: create object files from C source files. +define COMPILE_C_TEMPLATE +$(OUTDIR)/$(notdir $(basename $(1))).o : $(1) +## @echo + @echo $(MSG_COMPILING) $$< "->" $$@ + $(CC) -c $(THUMB) $$(CFLAGS) $$(CONLYFLAGS) $$< -o $$@ +endef +$(foreach src, $(SRC), $(eval $(call COMPILE_C_TEMPLATE, $(src)))) + +# Compile: create object files from C source files. ARM-only +define COMPILE_C_ARM_TEMPLATE +$(OUTDIR)/$(notdir $(basename $(1))).o : $(1) +## @echo + @echo $(MSG_COMPILING_ARM) $$< "->" $$@ + $(CC) -c $$(CFLAGS) $$(CONLYFLAGS) $$< -o $$@ +endef +$(foreach src, $(SRCARM), $(eval $(call COMPILE_C_ARM_TEMPLATE, $(src)))) + + +# Compile: create object files from C++ source files. +define COMPILE_CPP_TEMPLATE +$(OUTDIR)/$(notdir $(basename $(1))).o : $(1) +## @echo + @echo $(MSG_COMPILINGCPP) $$< "->" $$@ + $(CC) -c $(THUMB) $$(CFLAGS) $$(CPPFLAGS) $$< -o $$@ +endef +$(foreach src, $(CPPSRC), $(eval $(call COMPILE_CPP_TEMPLATE, $(src)))) + +# Compile: create object files from C++ source files. ARM-only +define COMPILE_CPP_ARM_TEMPLATE +$(OUTDIR)/$(notdir $(basename $(1))).o : $(1) +## @echo + @echo $(MSG_COMPILINGCPP_ARM) $$< "->" $$@ + $(CC) -c $$(CFLAGS) $$(CPPFLAGS) $$< -o $$@ +endef +$(foreach src, $(CPPSRCARM), $(eval $(call COMPILE_CPP_ARM_TEMPLATE, $(src)))) + + +# Compile: create assembler files from C source files. ARM/Thumb +$(SRC:.c=.s) : %.s : %.c + @echo $(MSG_ASMFROMC) $< to $@ + $(CC) $(THUMB) -S $(CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create assembler files from C source files. ARM only +$(SRCARM:.c=.s) : %.s : %.c + @echo $(MSG_ASMFROMC_ARM) $< to $@ + $(CC) -S $(CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Generate Doxygen documents +docs: + doxygen $(DOXYGENDIR)/doxygen.cfg + +# Target: clean project. +clean: begin clean_list finished end + +clean_list : +## @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(OUTDIR)/$(TARGET).map + $(REMOVE) $(OUTDIR)/$(TARGET).elf + $(REMOVE) $(OUTDIR)/$(TARGET).hex + $(REMOVE) $(OUTDIR)/$(TARGET).bin + $(REMOVE) $(OUTDIR)/$(TARGET).sym + $(REMOVE) $(OUTDIR)/$(TARGET).lss + $(REMOVE) $(ALLOBJ) + $(REMOVE) $(LSTFILES) + $(REMOVE) $(DEPFILES) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + + +# Create output files directory +# all known MS Windows OS define the ComSpec environment variable +ifdef ComSpec +$(shell md $(OUTDIR) 2>NUL) +else +$(shell mkdir $(OUTDIR) 2>/dev/null) +endif + +# Include the dependency files. +ifdef ComSpec +-include $(shell md $(OUTDIR)\dep 2>NUL) $(wildcard $(OUTDIR)/dep/*) +else +-include $(shell mkdir $(OUTDIR) 2>/dev/null) $(shell mkdir $(OUTDIR)/dep 2>/dev/null) $(wildcard $(OUTDIR)/dep/*) +endif + + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin lss sym clean clean_list program + diff --git a/flight/AHRS/ahrs.c b/flight/AHRS/ahrs.c new file mode 100644 index 000000000..a23c210ae --- /dev/null +++ b/flight/AHRS/ahrs.c @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * + * @file ahrs.c + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010. + * @brief Main AHRS functions + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* OpenPilot Includes */ +#include "ahrs.h" + +/* Global Variables */ + +/* Local Variables */ + +/* Function Prototypes */ + +/** +* OpenPilot Main function +*/ +int main() +{ + /* Brings up System using CMSIS functions, enables the LEDs. */ + PIOS_SYS_Init(); + + /* Delay system */ + PIOS_DELAY_Init(); + + /* Toggle LED's forever */ + PIOS_LED_On(LED1); + PIOS_LED_On(LED2); + for(;;) + { + PIOS_LED_Toggle(LED2); + PIOS_DELAY_WaitmS(100); + } + + /* If all is well we will never reach here as the scheduler will now be running. */ + /* If we do get here, it will most likely be because we ran out of heap space. */ + return 0; +} diff --git a/flight/AHRS/inc/ahrs.h b/flight/AHRS/inc/ahrs.h new file mode 100644 index 000000000..d58f45a1b --- /dev/null +++ b/flight/AHRS/inc/ahrs.h @@ -0,0 +1,34 @@ +/** + ****************************************************************************** + * + * @file ahrs.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010. + * @brief Main AHRS header. + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#ifndef AHRS_H +#define AHRS_H + + +/* PIOS Includes */ +#include + +#endif /* AHRS_H */ diff --git a/flight/AHRS/inc/pios_board.h b/flight/AHRS/inc/pios_board.h new file mode 100644 index 000000000..a27d92c68 --- /dev/null +++ b/flight/AHRS/inc/pios_board.h @@ -0,0 +1,271 @@ +/** + ****************************************************************************** + * + * @file pios_board.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010. + * @brief Defines board hardware for the OpenPilot Version 0.1 hardware. + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#ifndef PIOS_BOARD_H +#define PIOS_BOARD_H + + +//------------------------ +// DMA Channels Used +//------------------------ +/* Channel 1 - */ +/* Channel 2 - SPI1 RX */ +/* Channel 3 - SPI1 TX */ +/* Channel 4 - SPI2 RX */ +/* Channel 5 - SPI2 TX */ +/* Channel 6 - */ +/* Channel 7 - */ +/* Channel 8 - */ +/* Channel 9 - */ +/* Channel 10 - */ +/* Channel 11 - */ +/* Channel 12 - */ + +//------------------------ +// PIOS_LED +//------------------------ +#define PIOS_LED_LED1_GPIO_PORT GPIOC +#define PIOS_LED_LED1_GPIO_PIN GPIO_Pin_12 +#define PIOS_LED_LED1_GPIO_CLK RCC_APB2Periph_GPIOC +#define PIOS_LED_LED2_GPIO_PORT GPIOC +#define PIOS_LED_LED2_GPIO_PIN GPIO_Pin_13 +#define PIOS_LED_LED2_GPIO_CLK RCC_APB2Periph_GPIOC +#define PIOS_LED_NUM 2 +#define PIOS_LED_PORTS { PIOS_LED_LED1_GPIO_PORT, PIOS_LED_LED2_GPIO_PORT } +#define PIOS_LED_PINS { PIOS_LED_LED1_GPIO_PIN, PIOS_LED_LED2_GPIO_PIN } +#define PIOS_LED_CLKS { PIOS_LED_LED1_GPIO_CLK, PIOS_LED_LED2_GPIO_CLK } + +//------------------------ +// PIOS_I2C +//------------------------ +#define PIOS_I2C_GPIO_PORT GPIOB +#define PIOS_I2C_SDA_PIN GPIO_Pin_11 +#define PIOS_I2C_SCL_PIN GPIO_Pin_10 +#define PIOS_I2C_DUTY_CYCLE I2C_DutyCycle_2 +#define PIOS_I2C_BUS_FREQ 400000 +#define PIOS_I2C_TIMEOUT_VALUE 5000 +#define PIOS_I2C_IRQ_EV_PRIORITY 2 +#define PIOS_I2C_IRQ_ER_PRIORITY 2 + +//------------------------ +// PIOS_BMP085 +//------------------------ +#define PIOS_BMP085_EOC_GPIO_PORT GPIOC +#define PIOS_BMP085_EOC_GPIO_PIN GPIO_Pin_15 +#define PIOS_BMP085_EOC_PORT_SOURCE GPIO_PortSourceGPIOG +#define PIOS_BMP085_EOC_PIN_SOURCE GPIO_PinSource8 +#define PIOS_BMP085_EOC_CLK RCC_APB2Periph_GPIOC +#define PIOS_BMP085_EOC_EXTI_LINE EXTI_Line15 +#define PIOS_BMP085_EOC_IRQn EXTI15_10_IRQn + +//------------------------- +// PIOS_USART1 (TELEM) +//------------------------- +#define PIOS_USART1_ENABLED 1 +#define PIOS_USART1_USART USART2 +#define PIOS_USART1_GPIO_PORT GPIOA +#define PIOS_USART1_RX_PIN GPIO_Pin_3 +#define PIOS_USART1_TX_PIN GPIO_Pin_2 +#define PIOS_USART1_REMAP_FUNC { } +#define PIOS_USART1_IRQ_CHANNEL USART2_IRQn +#define PIOS_USART1_IRQHANDLER_FUNC void USART2_IRQHandler(void) +#define PIOS_USART1_CLK_FUNC RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE) +#define PIOS_USART1_NVIC_PRIO PIOS_IRQ_PRIO_HIGHEST +#define PIOS_USART1_BAUDRATE 57600 + +//------------------------- +// PIOS_USART2 (GPS) +//------------------------- +#define PIOS_USART2_ENABLED 1 +#define PIOS_USART2_USART USART3 +#define PIOS_USART2_GPIO_PORT GPIOC +#define PIOS_USART2_RX_PIN GPIO_Pin_11 +#define PIOS_USART2_TX_PIN GPIO_Pin_10 +#define PIOS_USART2_REMAP_FUNC { GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE); } +#define PIOS_USART2_IRQ_CHANNEL USART3_IRQn +#define PIOS_USART2_IRQHANDLER_FUNC void USART3_IRQHandler(void) +#define PIOS_USART2_CLK_FUNC RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE) +#define PIOS_USART2_NVIC_PRIO PIOS_IRQ_PRIO_HIGHEST +#define PIOS_USART2_BAUDRATE 57600 + +//------------------------- +// PIOS_USART3 (AUX) (RX5/RX6) +//------------------------- +#define PIOS_USART3_ENABLED 0 +#define PIOS_USART3_USART USART1 +#define PIOS_USART3_GPIO_PORT GPIOA +#define PIOS_USART3_RX_PIN GPIO_Pin_10 +#define PIOS_USART3_TX_PIN GPIO_Pin_9 +#define PIOS_USART3_REMAP_FUNC { } +#define PIOS_USART3_IRQ_CHANNEL USART1_IRQn +#define PIOS_USART3_IRQHANDLER_FUNC void USART1_IRQHandler(void) +#define PIOS_USART3_CLK_FUNC RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) +#define PIOS_USART3_NVIC_PRIO PIOS_IRQ_PRIO_HIGH +#define PIOS_USART3_BAUDRATE 57600 + +//------------------------- +// PIOS_USART +//------------------------- +#define PIOS_USART_NUM 3 +#define PIOS_USART_RX_BUFFER_SIZE 1024 +#define PIOS_USART_TX_BUFFER_SIZE 256 +#define PIOS_COM_DEBUG_PORT GPS + +//------------------------- +// SPI +//------------------------- +#define PIOS_SPI_IRQ_DMA_PRIORITY PIOS_IRQ_PRIO_HIGH +#define PIOS_SPI_NUM 2 +#define PIOS_SPI0_ENABLED 1 +#define PIOS_SPI0_PTR SPI1 +#define PIOS_SPI0_DMA_RX_PTR DMA1_Channel2 +#define PIOS_SPI0_DMA_TX_PTR DMA1_Channel3 +#define PIOS_SPI0_DMA_RX_IRQ_FLAGS (DMA1_FLAG_TC2 | DMA1_FLAG_TE2 | DMA1_FLAG_HT2 | DMA1_FLAG_GL2) +#define PIOS_SPI0_DMA_IRQ_CHANNEL DMA1_Channel2_IRQn +#define PIOS_SPI0_DMA_IRQHANDLER_FUNC void DMA1_Channel2_IRQHandler(void) +#define PIOS_SPI0_RCLK1_PORT GPIOA +#define PIOS_SPI0_RCLK1_PIN GPIO_Pin_4 +#define PIOS_SPI0_SCLK_PORT GPIOA +#define PIOS_SPI0_SCLK_PIN GPIO_Pin_5 +#define PIOS_SPI0_MISO_PORT GPIOA +#define PIOS_SPI0_MISO_PIN GPIO_Pin_6 +#define PIOS_SPI0_MOSI_PORT GPIOA +#define PIOS_SPI0_MOSI_PIN GPIO_Pin_7 +#define PIOS_SPI1_ENABLED 1 +#define PIOS_SPI1_PTR SPI2 +#define PIOS_SPI1_DMA_RX_PTR DMA1_Channel4 +#define PIOS_SPI1_DMA_TX_PTR DMA1_Channel5 +#define PIOS_SPI1_DMA_RX_IRQ_FLAGS (DMA1_FLAG_TC4 | DMA1_FLAG_TE4 | DMA1_FLAG_HT4 | DMA1_FLAG_GL4) +#define PIOS_SPI1_DMA_IRQ_CHANNEL DMA1_Channel4_IRQn +#define PIOS_SPI1_DMA_IRQHANDLER_FUNC void DMA1_Channel4_IRQHandler(void) +#define PIOS_SPI1_RCLK1_PORT GPIOB +#define PIOS_SPI1_RCLK1_PIN GPIO_Pin_12 +#define PIOS_SPI1_SCLK_PORT GPIOB +#define PIOS_SPI1_SCLK_PIN GPIO_Pin_13 +#define PIOS_SPI1_MISO_PORT GPIOB +#define PIOS_SPI1_MISO_PIN GPIO_Pin_14 +#define PIOS_SPI1_MOSI_PORT GPIOB +#define PIOS_SPI1_MOSI_PIN GPIO_Pin_15 + +//------------------------- +// PIOS_SDCARD +//------------------------- +#define PIOS_SDCARD_SPI 0 + +//------------------------- +// Delay Timer +//------------------------- +#define PIOS_DELAY_TIMER TIM2 +#define PIOS_DELAY_TIMER_RCC RCC_APB1Periph_TIM2 + +//------------------------- +// Master Clock +//------------------------- +#define PIOS_MASTER_CLOCK 72000000 +#define PIOS_PERIPHERAL_CLOCK (PIOS_MASTER_CLOCK / 2) + +//------------------------- +// Interrupt Priorities +//------------------------- +#define PIOS_IRQ_PRIO_LOW 12 // lower than RTOS +#define PIOS_IRQ_PRIO_MID 8 // higher than RTOS +#define PIOS_IRQ_PRIO_HIGH 5 // for SPI, ADC, I2C etc... +#define PIOS_IRQ_PRIO_HIGHEST 4 // for USART etc... + +//------------------------- +// Receiver PWM inputs +//------------------------- +#define RECEIVER1_GPIO_PORT GPIOB +#define RECEIVER1_PIN GPIO_Pin_0 // PB0 +#define RECEIVER1_TIM_PORT TIM3 +#define RECEIVER1_CH TIM_Channel_3 // TIM3_CH3 +#define RECEIVER2_GPIO_PORT GPIOB +#define RECEIVER2_PIN GPIO_Pin_1 // PB1 +#define RECEIVER2_TIM_PORT TIM3 +#define RECEIVER2_CH TIM_Channel_4 // TIM3_CH4 +#define RECEIVER3_GPIO_PORT GPIOA +#define RECEIVER3_PIN GPIO_Pin_8 // PA8 +#define RECEIVER3_TIM_PORT TIM1 +#define RECEIVER3_CH TIM_Channel_1 // TIM1_CH1 +#define RECEIVER4_GPIO_PORT GPIOA +#define RECEIVER4_PIN GPIO_Pin_0 // PA0 +#define RECEIVER4_TIM_PORT TIM5 +#define RECEIVER4_CH TIM_Channel_1 // TIM5_CH1 +#define RECEIVER5_GPIO_PORT GPIOA +#define RECEIVER5_PIN GPIO_Pin_10 // PA10 +#define RECEIVER5_TIM_PORT TIM1 +#define RECEIVER5_CH TIM_Channel_3 // TIM1_CH3 +#define RECEIVER6_GPIO_PORT GPIOA +#define RECEIVER6_PIN GPIO_Pin_9 // PA9 +#define RECEIVER6_TIM_PORT TIM1 +#define RECEIVER6_CH TIM_Channel_2 // TIM1_CH2 +#define RECEIVER7_GPIO_PORT GPIOB +#define RECEIVER7_PIN GPIO_Pin_4 // PB4 +#define RECEIVER7_TIM_PORT TIM3 +#define RECEIVER7_CH TIM_Channel_1 // TIM3_CH1 +#define RECEIVER8_GPIO_PORT GPIOB +#define RECEIVER8_PIN GPIO_Pin_5 // PB5 +#define RECEIVER8_TIM_PORT TIM3 +#define RECEIVER8_CH TIM_Channel_2 // TIM3_CH2 +#define NUM_RECEIVER_INPUTS 6 + +//------------------------- +// Servo outputs +//------------------------- +#define SERVO1TO4_PORT GPIOB +#define SERVO1_PIN GPIO_Pin_6 +#define SERVO2_PIN GPIO_Pin_7 +#define SERVO3_PIN GPIO_Pin_8 +#define SERVO4_PIN GPIO_Pin_9 +#define SERVO5TO8_PORT GPIOC +#define SERVO5_PIN GPIO_Pin_6 +#define SERVO6_PIN GPIO_Pin_7 +#define SERVO7_PIN GPIO_Pin_8 +#define SERVO8_PIN GPIO_Pin_9 +#define NUM_SERVO_OUTPUTS 8 + +//------------------------- +// ADC +//------------------------- +#define ADC_GPIO_PORT GPIOC +#define ADC_Z_PIN GPIO_Pin_0 // ADC123_IN10 +#define ADC_A_PIN GPIO_Pin_1 // ADC123_IN11 +#define ADC_B_PIN GPIO_Pin_2 // ADC123_IN12 +#define ADC_Z_CHANNEL ADC_Channel_10 +#define ADC_A_CHANNEL ADC_Channel_11 +#define ADC_B_CHANNEL ADC_Channel_12 +#define NUM_ADC_PINS 4 // 3 but actually 4 because of temp sensor +#define ADC_IRQ_PRIO PIOS_IRQ_PRIO_HIGH + +//------------------------- +// USB +//------------------------- +#define PIOS_USB_ENABLED 1 +#define PIOS_USB_DETECT_GPIO_PORT GPIOC +#define PIOS_USB_DETECT_GPIO_PIN GPIO_Pin_4 +#define PIOS_IRQ_USB_PRIORITY PIOS_IRQ_PRIO_MID + +#endif /* PIOS_BOARD_H */ diff --git a/flight/AHRS/inc/pios_config.h b/flight/AHRS/inc/pios_config.h new file mode 100644 index 000000000..8bd5ba5a5 --- /dev/null +++ b/flight/AHRS/inc/pios_config.h @@ -0,0 +1,51 @@ +/** + ****************************************************************************** + * + * @file pios_config.h + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010. + * @brief PiOS configuration header. + * - Central compile time config for the project. + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#ifndef PIOS_CONFIG_H +#define PIOS_CONFIG_H + +/* Enable/Disable PiOS Modules */ +//#define PIOS_DONT_USE_ADC +//#define PIOS_DONT_USE_DELAY +#define PIOS_DONT_USE_I2C +//#define PIOS_DONT_USE_IRQ +//#define PIOS_DONT_USE_LED +#define PIOS_DONT_USE_PWM +#define PIOS_DONT_USE_SERVO +//#define PIOS_DONT_USE_SPI +//#define PIOS_DONT_USE_SYS +//#define PIOS_DONT_USE_USART +#define PIOS_DONT_USE_USB_COM +#define PIOS_DONT_USE_USB_HID +#define PIOS_DONT_USE_USB +#define PIOS_DONT_USE_BMP085 +#define PIOS_DONT_USE_COM +#define PIOS_DONT_USE_SDCARD +#define PIOS_DONT_USE_SETTINGS + + +#endif /* PIOS_CONFIG_H */ diff --git a/flight/PiOS/STM32F10x/link_stm32f10x_MD.ld b/flight/PiOS/STM32F10x/link_stm32f10x_MD.ld new file mode 100644 index 000000000..f2fb75481 --- /dev/null +++ b/flight/PiOS/STM32F10x/link_stm32f10x_MD.ld @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * + * @file link_stm32f10x_HD.ld + * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2009. + * @brief PiOS linker for the OpenPilot AHRS board + * @see The GNU Public License (GPL) Version 3 + * + *****************************************************************************/ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* Memory Spaces Definitions */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 +} + +/* higher address of the user mode stack */ +_estack = 0x20010000; + +/* default stack sizes. + +These are used by the startup in order to allocate stacks for the different modes. + +Note: FreeRTOS gives each task an own stack +*/ + +__Stack_Size = 128 ; + +PROVIDE ( _Stack_Size = __Stack_Size ) ; + +__Stack_Init = _estack - __Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ +PROVIDE ( _Stack_Init = __Stack_Init ) ; + +/* +There will be a link error if there is not this amount of RAM free at the end. +*/ +_Minimum_Stack_Size = 0x100 ; + +/* Check valid alignment for VTOR */ +ASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), "Start of memory region flash not aligned for startup vector table"); + + +/* +this sends all unreferenced IRQHandlers to reset +*/ + + +PROVIDE ( Undefined_Handler = 0 ) ; +PROVIDE ( SWI_Handler = 0 ) ; +PROVIDE ( IRQ_Handler = 0 ) ; +PROVIDE ( Prefetch_Handler = 0 ) ; +PROVIDE ( Abort_Handler = 0 ) ; +PROVIDE ( FIQ_Handler = 0 ) ; + +PROVIDE ( NMI_Handler = 0 ) ; +PROVIDE ( HardFault_Handler = 0 ) ; +PROVIDE ( MemManage_Handler = 0 ) ; +PROVIDE ( BusFault_Handler = 0 ) ; +PROVIDE ( UsageFault_Handler = 0 ) ; +PROVIDE ( SVC_Handler = 0 ) ; +PROVIDE ( DebugMon_Handler = 0 ) ; +PROVIDE ( PendSV_Handler = 0 ) ; +PROVIDE ( SysTick_Handler = 0 ) ; + +PROVIDE ( WWDG_IRQHandler = 0 ) ; +PROVIDE ( PVD_IRQHandler = 0 ) ; +PROVIDE ( TAMPER_IRQHandler = 0 ) ; +PROVIDE ( RTC_IRQHandler = 0 ) ; +PROVIDE ( FLASH_IRQHandler = 0 ) ; +PROVIDE ( RCC_IRQHandler = 0 ) ; +PROVIDE ( EXTI0_IRQHandler = 0 ) ; +PROVIDE ( EXTI1_IRQHandler = 0 ) ; +PROVIDE ( EXTI2_IRQHandler = 0 ) ; +PROVIDE ( EXTI3_IRQHandler = 0 ) ; +PROVIDE ( EXTI4_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel1_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel2_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel3_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel4_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel5_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel6_IRQHandler = 0 ) ; +PROVIDE ( DMAChannel7_IRQHandler = 0 ) ; +PROVIDE ( ADC_IRQHandler = 0 ) ; +PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ; +PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ; +PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ; +PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ; +PROVIDE ( EXTI9_5_IRQHandler = 0 ) ; +PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ; +PROVIDE ( TIM1_UP_IRQHandler = 0 ) ; +PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ; +PROVIDE ( TIM1_CC_IRQHandler = 0 ) ; +PROVIDE ( TIM2_IRQHandler = 0 ) ; +PROVIDE ( TIM3_IRQHandler = 0 ) ; +PROVIDE ( TIM4_IRQHandler = 0 ) ; +PROVIDE ( I2C1_EV_IRQHandler = 0 ) ; +PROVIDE ( I2C1_ER_IRQHandler = 0 ) ; +PROVIDE ( I2C2_EV_IRQHandler = 0 ) ; +PROVIDE ( I2C2_ER_IRQHandler = 0 ) ; +PROVIDE ( SPI1_IRQHandler = 0 ) ; +PROVIDE ( SPI2_IRQHandler = 0 ) ; +PROVIDE ( USART1_IRQHandler = 0 ) ; +PROVIDE ( USART2_IRQHandler = 0 ) ; +PROVIDE ( USART3_IRQHandler = 0 ) ; +PROVIDE ( EXTI15_10_IRQHandler = 0 ) ; +PROVIDE ( RTCAlarm_IRQHandler = 0 ) ; +PROVIDE ( USBWakeUp_IRQHandler = 0 ) ; +PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ; +PROVIDE ( TIM8_UP_IRQHandler = 0 ) ; +PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ; +PROVIDE ( TIM8_CC_IRQHandler = 0 ) ; +PROVIDE ( ADC3_IRQHandler = 0 ) ; +PROVIDE ( FSMC_IRQHandler = 0 ) ; +PROVIDE ( SDIO_IRQHandler = 0 ) ; +PROVIDE ( TIM5_IRQHandler = 0 ) ; +PROVIDE ( SPI3_IRQHandler = 0 ) ; +PROVIDE ( UART4_IRQHandler = 0 ) ; +PROVIDE ( UART5_IRQHandler = 0 ) ; +PROVIDE ( TIM6_IRQHandler = 0 ) ; +PROVIDE ( TIM7_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ; +PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ; + + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/*this allows to compile the ST lib in "non-debug" mode*/ + + +/* Peripheral and SRAM base address in the alias region */ +PERIPH_BB_BASE = 0x42000000; +SRAM_BB_BASE = 0x22000000; + +/* Peripheral and SRAM base address in the bit-band region */ +SRAM_BASE = 0x20000000; +PERIPH_BASE = 0x40000000; + +/* Flash registers base address */ +PROVIDE ( FLASH_BASE = 0x40022000); +/* Flash Option Bytes base address */ +PROVIDE ( OB_BASE = 0x1FFFF800); + +/* Peripheral memory map */ +APB1PERIPH_BASE = PERIPH_BASE ; +APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ; +AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ; + +PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ; +PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ; +PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ; +PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ; +PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ; +PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ; +PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ; +PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ; +PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ; +PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ; +PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ; +PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ; +PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ; +PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ; + +PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ; +PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ; +PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ; +PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ; +PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ; +PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ; +PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ; +PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ; +PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ; +PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ; +PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ; +PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ; + +PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ; +PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ; +PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ; +PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ; +PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ; +PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ; +PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ; +PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ; +PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ; + +/* System Control Space memory map */ +SCS_BASE = 0xE000E000; + +PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ; +PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ; +PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ; + + +/* Sections Definitions */ + +SECTIONS +{ + + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ + .flashtext : + { + . = ALIGN(4); + *(.flashtext) /* Startup code */ + . = ALIGN(4); + } >FLASH + + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >FLASH + + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM + + + + /* this is the FLASH Bank1 */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + .b1text : + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata*) + } >FLASHB1 + + /* this is the EXTMEM */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + + /* EXTMEM Bank0 */ + .eb0text : + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata*) + } >EXTMEMB3 + + __exidx_start = .; + __exidx_end = .; + + /* after that it's only debugging information. */ + + /* remove the debugging information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + + diff --git a/flight/PiOS/STM32F10x/startup_stm32f10x_MD.S b/flight/PiOS/STM32F10x/startup_stm32f10x_MD.S new file mode 100644 index 000000000..f547c6701 --- /dev/null +++ b/flight/PiOS/STM32F10x/startup_stm32f10x_MD.S @@ -0,0 +1,356 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team / Angus Peart + * @version V3.1.1 + * @date 07/27/2009 + * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global SystemInit_ExtMemCtl_Dummy +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + diff --git a/flight/PiOS/inc/pios_sdcard.h b/flight/PiOS/inc/pios_sdcard.h index 05c68a370..1cfd22c25 100644 --- a/flight/PiOS/inc/pios_sdcard.h +++ b/flight/PiOS/inc/pios_sdcard.h @@ -27,6 +27,8 @@ #ifndef PIOS_SDCARD_H #define PIOS_SDCARD_H +#if !defined(PIOS_DONT_USE_SDCARD) + /* Public Functions */ typedef struct { uint8_t CSDStruct; /* CSD structure */ @@ -105,4 +107,6 @@ extern int32_t PIOS_SDCARD_ReadLine(PFILEINFO fileinfo, uint8_t *buffer, uint32_ extern int32_t PIOS_SDCARD_FileCopy(char *Source, char *Destination); extern int32_t PIOS_SDCARD_FileDelete(char *Filename); +#endif + #endif /* PIOS_SDCARD_H */ diff --git a/flight/PiOS/pios.h b/flight/PiOS/pios.h index 3cbd59333..448059903 100644 --- a/flight/PiOS/pios.h +++ b/flight/PiOS/pios.h @@ -44,6 +44,7 @@ #include #include +#if !defined(PIOS_DONT_USE_SDCARD) /* Dosfs Includes */ #include @@ -52,6 +53,7 @@ /* Mass Storage Device Includes */ #include +#endif /* PIOS Hardware Includes (STM32F10x) */ #include @@ -76,7 +78,9 @@ /* More added here as they get written */ +#if !defined(PIOS_DONT_USE_USB) /* USB Libs */ #include +#endif #endif /* PIOS_H */