The exti layer now allows drivers to register interrupt callbacks
during board initialization. All details of the driver using a
particular EXTI pin have been removed from the EXTI layer so it
can now be used on any board without board-specific modification.
This includes some nice refinements provided by Mike Smith during
initial review. His original commits have been squashed into this
one.
Way too much was being exposed in the API for the
HMC5843. This commit properly hides internal
details of the driver.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1629 ebee16cc-31ac-478f-84a7-5cbb03baadba
The DRDY signal from the magnetometer is connected to PB8
on the STM32. This pin is now configured as an external
interrupt and is now used to signal when new data is
available from the magnetometer.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1628 ebee16cc-31ac-478f-84a7-5cbb03baadba
I2C bus errors are now recoverable. The bus is properly reset
and an error indication is now provided to the caller whenever
a bus error occurs during processing of the transaction list.
For now, the users of the I2C layer just retry infinitely on
failure. The BMP085 and HMC5843 code should be changed to
report errors to its callers to allow a more sensible retry
strategy.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1625 ebee16cc-31ac-478f-84a7-5cbb03baadba
The info field in the pios_i2c_txn list can now be used
to provide a const string which describes the context
for this transaction.
This is very helpful when diagnosing an error that occurs
somewhere in the middle of the I2C FSM since the FSM runs
primarily in the ISR where the original context for the
transactions is no longer available in the traceback.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1622 ebee16cc-31ac-478f-84a7-5cbb03baadba
This file had mixed line endings. Now they're all the same.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1353 ebee16cc-31ac-478f-84a7-5cbb03baadba
The STM32 I2C block has a number of errata associated with it.
These errata are primarily related to timing sensitivities between
the peripheral and the interrupt handler. In particular, the
correct generation of the stop bit relies on the I2C IRQ running
immediately and not being held off for any reason.
NOTE: The I2C interrupts must be the highest priority IRQs in the
system to ensure correct operation.
I2C protocol is now implemented as a formal state machine.
See: stm32_i2c_fsm.{dot,jpg} for FSM description.
I2C init is now expressed by const initializers in pios_board.c
for both OP and AHRS boards.
I2C device drivers (ie. bmp085/hmc5843) now pass in const arrays
of an unlimited number of bus transfers to be done atomically.
The I2C adapter driver now handles all bus-level locking across the
list of transactions. Generation of start/restart/stop conditions
are handled automatically over the list of transactions.
Timeouts have been removed from the API for now. May be added
back later.
This driver has run error free on both the OP and AHRS boards for
up to 48hrs but it still sometimes fails earlier than that on the OP
board. There is another possible set of improvements to the driver
that could employ the DMA engine for transfers of >= 2bytes. This
change would reduce the timing sensitivities between the peripheral
and the driver but unfortunately, both the SPI and I2C interfaces
share the DMA1 engine. That means only one of these two peripherals
can use the DMA engine and right now, SPI between OP and AHRS is
already using it.
Failures are currently fatal and will lock up the CPU. This allows
useful information to be obtained in the failure cases.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1241 ebee16cc-31ac-478f-84a7-5cbb03baadba
