sometimes thrown, and made errors not lock it up by default. It works for me,
but since this has historically been associated with lots of lock ups please
check your systems carefully.
PiOS/I2C: Make the bus by default try to recover from errors instead of locking
up
PiOS/I2C: After a bus error and clocking all previous data create a STOP
condition to make sure bus is released (note, this also requires creating a
START condition first)
PiOS/I2C: If the same event hits the I2C bus twice in a row then disregard
second one, there is no situation where we should get the same event multiple
times that matters and this gets us out really quickly to catch the real
events. I was seeing this with repeated 0x70084 which means byte transmitted.
This is related to STM32 bugs in the IRQ timings I believe.
PiOS/I2C: 1) Mask out some bits we don't care about in the event flags
2) Don't lock up if the give semaphore fails, although why it does is strange
3) Recover from bus failure through the "auto" state path instead of just
coding state
PiOS/I2C: Change the reset bus code to follow
http://www.analog.com/static/imported-files/application_notes/54305147357414AN686_0.pdf
(thanks for the reference Neontangerine). Although this may actually NOT clear
the bus the first time through, subsequent bus errors should eventually clock
it out. The up side is it is less likely to clock a bunch of 1s into an ESC
and make it run up.
PiOS/I2C: Some cleaned up code for getting a snippet of the history when
something strange happens
PiOS/I2C: Export logging information from I2C through a UAV object
PiOS/I2C: Improve the diagnostic information
PiOS/I2C: Need to handle the event 0x30084. This seems to happen between a
byte transmitted and new byte started
PiOS/I2C: Handle the NACK condition by simply going to the stopping state.
PiOS/I2C: Add a new NACK state to handle sending the STOP signal after a NACK
following the STM documentation. Other error conditions still are not dealt
with.
PiOS/I2C: Should handle the NACK condition from all the write cases. Need to
think about read cases
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2239 ebee16cc-31ac-478f-84a7-5cbb03baadba
and starting transmission again. This should address the bootloader locking up
on verify.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2235 ebee16cc-31ac-478f-84a7-5cbb03baadba
configuration structures are const which keeps them in flash instead of ram.
However the library needs to declare them const for the compiler to work.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2231 ebee16cc-31ac-478f-84a7-5cbb03baadba
only one receive task. This is less generally safe but decreases the
frequency of resets in our current configuration
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2144 ebee16cc-31ac-478f-84a7-5cbb03baadba
similar driver format to the PIOS_USART system. (p.s. are you happy now, PT?)
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2029 ebee16cc-31ac-478f-84a7-5cbb03baadba
running and block the interrupts while modifying the buffers
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2003 ebee16cc-31ac-478f-84a7-5cbb03baadba
The DRDY signal from the magnetometer is connected to PB8
on the STM32. This pin is now configured as an external
interrupt and is now used to signal when new data is
available from the magnetometer.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1628 ebee16cc-31ac-478f-84a7-5cbb03baadba
I2C bus errors are now recoverable. The bus is properly reset
and an error indication is now provided to the caller whenever
a bus error occurs during processing of the transaction list.
For now, the users of the I2C layer just retry infinitely on
failure. The BMP085 and HMC5843 code should be changed to
report errors to its callers to allow a more sensible retry
strategy.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1625 ebee16cc-31ac-478f-84a7-5cbb03baadba
AUTO transitions in the FSM are now handled immediately
after processing each newly injected event rather than only
at the end of the EV ISR.
This consolidation allows the upcoming addition of event
injection from both the EV and ER ISR contexts.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1624 ebee16cc-31ac-478f-84a7-5cbb03baadba
Occasionally, the I2C driver races with the STM32 I2C peripheral
at the end of a bus cycle. This leaves the bus in an errored
state and the stop condition is not properly asserted on the bus.
The polling for the stopped condition was previously implemented
in ISR context since it was expected to be nearly instananeous.
In the error condition, however, the stop condition will never
happen. The polling for this case is now done by the initiating
task (or mainloop on the AHRS) to prevent the timeout condition
from triggering the watchdog.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1623 ebee16cc-31ac-478f-84a7-5cbb03baadba
Differentiate the _FSM_ faulted from the (soon to
exist _BUS_ faulted state.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1621 ebee16cc-31ac-478f-84a7-5cbb03baadba
1. Added reenumeration function and call it on USB init (device will appear after reprogramming now)
2. Moved buffer.c to general flight/Libraries location
3. Removed the 62 byte transmission limitation by adding a transmission buffer
4. Sped up USB communication by increasing endpoint polling frequency
Note, that the nonblocking and blocking USB send functions are not blocking entirely correcting. The blocking calls the nonblocking, and the nonblocking blocks until the last chunk has started tranmission if it's a big transmission. The buffering I added would generalize to non-blocking nicely, but would require using the EP1(IN) callback to handle most of the tranmission. This creates a lot of issues if one function is pushing data onto the buffer and the interrupt is sending.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1403 ebee16cc-31ac-478f-84a7-5cbb03baadba
The transition from the ADDR state to the read state
was broken for non-final reads. The FSM diagram was
also wrong for this transition.
Since reads are always the last transaction in a sequence
in our current usage, this doesn't actually fix any known
bugs.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1350 ebee16cc-31ac-478f-84a7-5cbb03baadba
Since the i2c bus is bidirectional, there are certain
states (eg. part way through a read) where the slave
device is in control of driving the SDA line.
On a cold start (power on), the slave devices are all
quiescent and will not drive the bus. However, on a warm
start (eg. watchdog or jtag restart), it is possible that as
the CPU boots, the slave device may be holding the SDA line
low. This is a bus busy condition and will prevent the I2C
bus master in the CPU from being able to seize the bus during
init.
The fix for this is to clock the i2c bus sufficiently to ensure
that the the slave device finishes its transaction and releases
the bus.
Once the slave has released the bus, the bus master can properly
initialize and assert a STOP condition on the bus.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1349 ebee16cc-31ac-478f-84a7-5cbb03baadba
The STM32 I2C block has a number of errata associated with it.
These errata are primarily related to timing sensitivities between
the peripheral and the interrupt handler. In particular, the
correct generation of the stop bit relies on the I2C IRQ running
immediately and not being held off for any reason.
NOTE: The I2C interrupts must be the highest priority IRQs in the
system to ensure correct operation.
I2C protocol is now implemented as a formal state machine.
See: stm32_i2c_fsm.{dot,jpg} for FSM description.
I2C init is now expressed by const initializers in pios_board.c
for both OP and AHRS boards.
I2C device drivers (ie. bmp085/hmc5843) now pass in const arrays
of an unlimited number of bus transfers to be done atomically.
The I2C adapter driver now handles all bus-level locking across the
list of transactions. Generation of start/restart/stop conditions
are handled automatically over the list of transactions.
Timeouts have been removed from the API for now. May be added
back later.
This driver has run error free on both the OP and AHRS boards for
up to 48hrs but it still sometimes fails earlier than that on the OP
board. There is another possible set of improvements to the driver
that could employ the DMA engine for transfers of >= 2bytes. This
change would reduce the timing sensitivities between the peripheral
and the driver but unfortunately, both the SPI and I2C interfaces
share the DMA1 engine. That means only one of these two peripherals
can use the DMA engine and right now, SPI between OP and AHRS is
already using it.
Failures are currently fatal and will lock up the CPU. This allows
useful information to be obtained in the failure cases.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1241 ebee16cc-31ac-478f-84a7-5cbb03baadba
Mark the I2C_InitStruct parameter as const so that we can pass
const data as the initializer.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1240 ebee16cc-31ac-478f-84a7-5cbb03baadba
PIOS SPI devices may now make use of automatic CRC generation
and checking on block transfers. Only supports CRC8 for now.
Since the SPI interface CRC calculation continues across message
boundaries (ie. not reset on every transfer), we must manually reset
the CRC registers for every transfer to allow the two sides of the
link to resynchronize.
Unfortunately, resetting the CRC registers requires disabling the
SPI peripheral which must now be done on every block transfer.
Note: The last byte of the tx buffer is never sent and is assumed to
be a place holder for the tx CRC8.
Note: The last byte of the rx buffer is expected to hold the rx CRC8.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1011 ebee16cc-31ac-478f-84a7-5cbb03baadba
Tx buffers should not be modified. This allows passing const data
to the transfer function.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1010 ebee16cc-31ac-478f-84a7-5cbb03baadba
The com layer transmit functions should provide guarantees
that they will not modify the buffer that you're transmitting.
Declaring the parameter as a pointer to const keeps the underlying
implementations honest.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1001 ebee16cc-31ac-478f-84a7-5cbb03baadba
TransferByte API is simplified to either assert or
return the rx byte.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@999 ebee16cc-31ac-478f-84a7-5cbb03baadba
SPI block transfers were broken in commit r759. Block
transfers are primarily used by the SD card interface so
this also broke accesses to the SD card.
SD card accesses should be fixed now. Verified by writing
config objects in the GCS and confirming that they survived
a reboot of the OP board.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@808 ebee16cc-31ac-478f-84a7-5cbb03baadba
- Created a pluggable COM layer
- Converted COM + USART init into static initializers
rather than typedefs
- Generalized the USB HID COM API to match the USART
API.
- Changed USART and COM layers to be data driven rather
than #ifdef'ing/switching on the specifics of each port
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@760 ebee16cc-31ac-478f-84a7-5cbb03baadba
Added support for SPI slave configurations to the pios SPI layer.
Converted the board specific configuration for the PIOS SPI layer to
use const static initializers rather than #defines (see pios_board.c).
SPI interface between the OP board and the AHRS is now operational at
a basic level, capable of moving simple single byte messages between
boards. Multi-byte, CRC protected messages will be added on top of this.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@759 ebee16cc-31ac-478f-84a7-5cbb03baadba
Many of the STM32 library functions take a pointer to an
initialization structure. In nearly every case, this struct
is a read-only (ie. const) parameter.
It is advantageous (and good coding practice) to actually declare
read-only data as const so that the compiler can place the const data
in the .rodata section which resides in flash and doesn't consume any
RAM. This has the added bonus advantage that it is impossible for the
running application to corrupt the read-only data.
In order to allow passing pointers to const data into the library
functions, it is essential that the function prototypes also declare
their associated read-only parameters as const. This commit adds
the const attribute to those parameters that are actually read-only.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@758 ebee16cc-31ac-478f-84a7-5cbb03baadba
No functionality changed. Clean up only.
Changed a few of the (1 << x) constructs to use existing macro
definitions to improve code readability.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@757 ebee16cc-31ac-478f-84a7-5cbb03baadba
No functionality changed. Clean up only.
Make early init code (Reset_Handler) use the existing irq stack
rather than the hard-coded one.
Remove (now) unused references to the hard-coded stack.
Removed the link-time check for a minimal task stack in RAM since
FreeRTOS allocates user stacks from the heap which is already reserved
in the .bss section (as symbol xHeap).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@756 ebee16cc-31ac-478f-84a7-5cbb03baadba
The previous fix in r652 was _almost_ right. There was
still a one word (4-byte) overlap between _irq_stack_top
and the start of the data segment.
_irq_stack_end + _irq_stack_size leaves the '.' pointer at
the word immediatly after the stack. This commit corrects
this error and places _irq_stack_top on the last word
_inside_ the reserved space for the irq stack.
[Before]
$ ./tools/arm-2009q3/bin/arm-none-eabi-nm -n ./build/openpilot/OpenPilot.elf
...
20000000 A SRAM_BASE
20000000 B _irq_stack_end
20000400 d LED_GPIO_PORT <--- overlap
20000400 B _irq_stack_top <--- overlap
20000400 D _sdata
20000408 d ADC_GPIO_PORT
...
[After]
$ ./tools/arm-2009q3/bin/arm-none-eabi-nm -n ./build/openpilot/OpenPilot.elf
...
20000000 A SRAM_BASE
20000000 B _irq_stack_end
200003fc B _irq_stack_top
20000400 d LED_GPIO_PORT
20000400 D _sdata
20000408 d ADC_GPIO_PORT
...
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@668 ebee16cc-31ac-478f-84a7-5cbb03baadba
This commit fixes all existing warnings.
All basic compiler warnings will now be treated as errors.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@658 ebee16cc-31ac-478f-84a7-5cbb03baadba
This fixes the COM interface over USB HID to the point where
it can establish and maintain solid communications with the UAVObject
Browser in the GCS.
Tested only on Linux. The USB HID interface is still disabled for now
until it is tested successfully by a wider group.
Edit telemetry.c and set ALLOW_HID_TELEMETRY to 1 to enable telemetry
over the USB HID interface and report your results in the forum.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@656 ebee16cc-31ac-478f-84a7-5cbb03baadba
The MSP (IRQ stack) was trampling across the data segment. This was
especially disastrous in the USB interrupts since they allocate and
fill buffers on the stack.
The root of this trampling was that no RAM was being reserved for the
MSP and a hard-coded value of (0x20000400) was used as the initial MSP
base address. This resulted in the first 1K bytes of the .data segment
overlapping with the IRQ stack. As can be expected, all sorts of badness
resulted when interrupts were firing and trampling over variables.
This change reserves the first _isr_stack_size bytes at the beginning of
RAM for the MSP. If an ISR call chain runs off of the end of the MSP,
a Hard Fault will be generated as the (now invalid) sp is accessed.
There are two stack pointers in the Cortex-M3 CPU. These are MSP (Main
Stack Pointer) and PSP (Process Stack Pointer).
Which stack is in use at any given time is determined by the following table:
Mode CONTROL[ASPSEL] Stack
---- --------------- -----
Thread 0 MSP
Thread 1 PSP
Handler x MSP
Out of reset, the CPU is in Thread mode using the MSP. The initial value
of the MSP is automatically loaded from address 0 (lowest word in boot
region -- typically FLASH) immediately prior to jumping to the reset vector.
When running at interrupt level, the Cortex-M3 always uses the MSP and the
ASPSEL bit is forced to zero.
FreeRTOS allocates a separate stack for each task upon task creation. These
task stacks are allocated from the heap. FreeRTOS sets the active stack to
the PSP whenever running in a task context (both in privileged mode and user
mode).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@652 ebee16cc-31ac-478f-84a7-5cbb03baadba
PIOS_SYS: Added system reset function.
OpenPilot Makefile: Default USE_BOOTLOADER should be NO.
OpenPilot Bootloader: Removed LED initialisation.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@303 ebee16cc-31ac-478f-84a7-5cbb03baadba
Added timer usage diagram to pios_board.h
Removed bloat for extra optimisation in PIOS_DELAY.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@265 ebee16cc-31ac-478f-84a7-5cbb03baadba
