- New Attitude module for AHRS (skeleton)
- New AttitudeSettings UAVobject
- New AttitudeActual UAVobject
- Regenerated UAVobjects
- Added new UAVobjects to OpenPilot and GCS builds
- New PiOS driver for OpenPilot AHRS (stubs only)
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@655 ebee16cc-31ac-478f-84a7-5cbb03baadba
Since the EXTI and NVIC init routines automatically enable the IRQ when it
is configured, it is possible for the EOC interrupt to fire immediately
upon configuring the IRQ.
Since the handler for the EOC interrupt (EXTI15_10_IRQHandler) does a
xSemaphoreGiveFromISR, it is important to have the semaphore initialized
prior to enabling the interrupt.
Also, added missing include for altitude module.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@654 ebee16cc-31ac-478f-84a7-5cbb03baadba
The MSP (IRQ stack) was trampling across the data segment. This was
especially disastrous in the USB interrupts since they allocate and
fill buffers on the stack.
The root of this trampling was that no RAM was being reserved for the
MSP and a hard-coded value of (0x20000400) was used as the initial MSP
base address. This resulted in the first 1K bytes of the .data segment
overlapping with the IRQ stack. As can be expected, all sorts of badness
resulted when interrupts were firing and trampling over variables.
This change reserves the first _isr_stack_size bytes at the beginning of
RAM for the MSP. If an ISR call chain runs off of the end of the MSP,
a Hard Fault will be generated as the (now invalid) sp is accessed.
There are two stack pointers in the Cortex-M3 CPU. These are MSP (Main
Stack Pointer) and PSP (Process Stack Pointer).
Which stack is in use at any given time is determined by the following table:
Mode CONTROL[ASPSEL] Stack
---- --------------- -----
Thread 0 MSP
Thread 1 PSP
Handler x MSP
Out of reset, the CPU is in Thread mode using the MSP. The initial value
of the MSP is automatically loaded from address 0 (lowest word in boot
region -- typically FLASH) immediately prior to jumping to the reset vector.
When running at interrupt level, the Cortex-M3 always uses the MSP and the
ASPSEL bit is forced to zero.
FreeRTOS allocates a separate stack for each task upon task creation. These
task stacks are allocated from the heap. FreeRTOS sets the active stack to
the PSP whenever running in a task context (both in privileged mode and user
mode).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@652 ebee16cc-31ac-478f-84a7-5cbb03baadba
NOTE: Delete any metaobjects that you may have saved in the SD card (delete all .obj files).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@643 ebee16cc-31ac-478f-84a7-5cbb03baadba
This module reads from the BMP085 pressure sensor. It periodically
updates the pressure (kPa) and temperature (C) as well as the
calculated altitude (m).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@640 ebee16cc-31ac-478f-84a7-5cbb03baadba
FreeRTOS has a strict requirement that even interrupt-safe API calls (ie.
those ending in "FromISR") can only be called from ISRs that are at lesser
or equal priorities to configMAX_SYSCALL_INTERRUPT_PRIORITY. See the
"configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY"
section at:
http://www.freertos.org/a00110.html
The interrupt numbers used on the Cortex-M3 CPU has a somewhat backward
representation of the interrupt numbers so 255 = lowest priority and
0 = highest priority.
The calculation is further complicated by the STM32 implementation only using
the upper 4 bits of the priority value. Only 0x00, 0x10, 0x20, ..., 0xE0, 0xF0
represent useful interrupt priorities.
FreeRTOS requires that MAX_SYSCALL and KERNEL interrupt priorities are expressed
as raw unshifted 8-bit values to be programmed directly into the BASEPRI register.
The priority values passed to the NVIC initialization, however, are expected
to be 4-bit values and are shifted up by 4 within NVIC_Init() for you.
The end result is that we need this arrangement:
[highest priority]
NVIC_0 (Non-maskable-interrupt)
NVIC_1
NVIC_2
[Must NOT call FreeRTOS APIs above here]
configMAX_SYSCALL_INTERRUPT_PRIORITY (now at 48 = 0x30 = NVIC_3)
PIOS_IRQ_PRIO_HIGHEST (cur. NVIC_4)
PIOS_IRQ_PRIO_HIGH (cur. NVIC_5)
PIOS_IRQ_PRIO_MID (cur. NVIC_8)
PIOS_IRQ_PRIO_LOW (cur. NVIC_12)
configKERNEL_INTERRUPT_PRIORITY (240 = 0xF0 = NVIC_15)
[lowest priority]
The previous config had configMAX_SYSCALL_INTERRUPT_PRIORITY set at
191 (0xBF) which is effectively NVIC_11. This was allowing all of
the MID, HIGH and HIGHEST interrupt handlers to preempt the OS in
its critical sections. Since some of these ISRs were calling
FreeRTOS APIs, this would result in corrupting internal data structures
within the OS.
It should be ok to move the configKERNEL_INTERRUPT_PRIORITY to a higher
priority as long as it is less than configMAX_SYSCALL_INTERRUPT_PRIORITY.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@637 ebee16cc-31ac-478f-84a7-5cbb03baadba
This fixes the gdb stepi command to allow the M3 core to make
forward progress even when interrupts are pending. M3 Core interrupts
are masked/unmasked in pre and post command hooks.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@636 ebee16cc-31ac-478f-84a7-5cbb03baadba
Moved the generated python classes from the flight directory to the
ground directory since they are only used on the host, not the
embedded targets.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@628 ebee16cc-31ac-478f-84a7-5cbb03baadba
The uavobjectgenerator can now generate python classes for each
UAVObject definition. This is useful for writing simple test
applications in python that can exercise the UAVObject handling
code on the embedded boards.
This is a work in progress so the structure of the generated
classes is likely to change.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@623 ebee16cc-31ac-478f-84a7-5cbb03baadba
The gdb commands step, next and finish on the M3 core would
never make forward progress since there is almost always an
interrupt pending. This is a known problem on the M3, and is
fixed by adding pre and post command hooks which mask and unmask
all ISRs on the M3 core.
Step, next and finish now work as expected, but care should be
taken when using these commands across any part of the code that
actually _needs_ the interrupts in order to make forward progress.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@622 ebee16cc-31ac-478f-84a7-5cbb03baadba
Commit @583 uncomments the HIDTest task creation. HIDTest task is configured to run at
priority 4 (== tskIDLE_PRIORITY + 4) which is higher priority than the "System" task at
priority 3 (== tskIDLE_PRIORITY + 3).
The HIDTest task never blocks so it prevents the system task (and any other task of priority
less than 4) from ever running.
This commit does not fix the root problem of HIDTest never blocking, but rather lowers
its priority to be equal to the system task so that they share the CPU. This is a
temporary workaround.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@586 ebee16cc-31ac-478f-84a7-5cbb03baadba
