The transition from the ADDR state to the read state
was broken for non-final reads. The FSM diagram was
also wrong for this transition.
Since reads are always the last transaction in a sequence
in our current usage, this doesn't actually fix any known
bugs.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1350 ebee16cc-31ac-478f-84a7-5cbb03baadba
Since the i2c bus is bidirectional, there are certain
states (eg. part way through a read) where the slave
device is in control of driving the SDA line.
On a cold start (power on), the slave devices are all
quiescent and will not drive the bus. However, on a warm
start (eg. watchdog or jtag restart), it is possible that as
the CPU boots, the slave device may be holding the SDA line
low. This is a bus busy condition and will prevent the I2C
bus master in the CPU from being able to seize the bus during
init.
The fix for this is to clock the i2c bus sufficiently to ensure
that the the slave device finishes its transaction and releases
the bus.
Once the slave has released the bus, the bus master can properly
initialize and assert a STOP condition on the bus.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1349 ebee16cc-31ac-478f-84a7-5cbb03baadba
into NED reference frame and used in the INSGPS algorithm, although currently this
information isn't propagated back to OP. Data structures related to the GPS position
into the algorithm and the position estimate out will likely be in flux.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1334 ebee16cc-31ac-478f-84a7-5cbb03baadba
Altitude/pressure sensor data is sent to the AHRS whenever
the AltitudeActual object is updated.
Altitude, Pressure and Temperature are sent as floats.
Same as in the UAVObject that goes to the GCS.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1291 ebee16cc-31ac-478f-84a7-5cbb03baadba
The STM32 I2C block has a number of errata associated with it.
These errata are primarily related to timing sensitivities between
the peripheral and the interrupt handler. In particular, the
correct generation of the stop bit relies on the I2C IRQ running
immediately and not being held off for any reason.
NOTE: The I2C interrupts must be the highest priority IRQs in the
system to ensure correct operation.
I2C protocol is now implemented as a formal state machine.
See: stm32_i2c_fsm.{dot,jpg} for FSM description.
I2C init is now expressed by const initializers in pios_board.c
for both OP and AHRS boards.
I2C device drivers (ie. bmp085/hmc5843) now pass in const arrays
of an unlimited number of bus transfers to be done atomically.
The I2C adapter driver now handles all bus-level locking across the
list of transactions. Generation of start/restart/stop conditions
are handled automatically over the list of transactions.
Timeouts have been removed from the API for now. May be added
back later.
This driver has run error free on both the OP and AHRS boards for
up to 48hrs but it still sometimes fails earlier than that on the OP
board. There is another possible set of improvements to the driver
that could employ the DMA engine for transfers of >= 2bytes. This
change would reduce the timing sensitivities between the peripheral
and the driver but unfortunately, both the SPI and I2C interfaces
share the DMA1 engine. That means only one of these two peripherals
can use the DMA engine and right now, SPI between OP and AHRS is
already using it.
Failures are currently fatal and will lock up the CPU. This allows
useful information to be obtained in the failure cases.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1241 ebee16cc-31ac-478f-84a7-5cbb03baadba
Mark the I2C_InitStruct parameter as const so that we can pass
const data as the initializer.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1240 ebee16cc-31ac-478f-84a7-5cbb03baadba
The AHRS comms module now sync's with the AHRS and
exchanges interesting data periodically. Whenever
the link to the AHRS is down, the AHRSComms alarm is
raised.
This is fairly basic for now but provides the last
piece of the infrastructure to move data back/forth
between the OP and the AHRS.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1014 ebee16cc-31ac-478f-84a7-5cbb03baadba
PIOS SPI devices may now make use of automatic CRC generation
and checking on block transfers. Only supports CRC8 for now.
Since the SPI interface CRC calculation continues across message
boundaries (ie. not reset on every transfer), we must manually reset
the CRC registers for every transfer to allow the two sides of the
link to resynchronize.
Unfortunately, resetting the CRC registers requires disabling the
SPI peripheral which must now be done on every block transfer.
Note: The last byte of the tx buffer is never sent and is assumed to
be a place holder for the tx CRC8.
Note: The last byte of the rx buffer is expected to hold the rx CRC8.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1011 ebee16cc-31ac-478f-84a7-5cbb03baadba
Tx buffers should not be modified. This allows passing const data
to the transfer function.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1010 ebee16cc-31ac-478f-84a7-5cbb03baadba
This defines the SPI message format as well as a few
initial messages for moving data across the link.
The v0 messages are place holders for firmware download
in the bootloader.
The v1 messages are to be used by the main application.
Note: This is not the final protocol definition.
Subject to change without notice.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1004 ebee16cc-31ac-478f-84a7-5cbb03baadba
The com layer transmit functions should provide guarantees
that they will not modify the buffer that you're transmitting.
Declaring the parameter as a pointer to const keeps the underlying
implementations honest.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1001 ebee16cc-31ac-478f-84a7-5cbb03baadba
TransferByte API is simplified to either assert or
return the rx byte.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@999 ebee16cc-31ac-478f-84a7-5cbb03baadba
SD R1 response format is defined as any byte with the MSb
cleared. The code was testing for any byte that was not 0xFF
which can lead to misinterpreting a byte as the response.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@998 ebee16cc-31ac-478f-84a7-5cbb03baadba
SPI block transfers were broken in commit r759. Block
transfers are primarily used by the SD card interface so
this also broke accesses to the SD card.
SD card accesses should be fixed now. Verified by writing
config objects in the GCS and confirming that they survived
a reboot of the OP board.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@808 ebee16cc-31ac-478f-84a7-5cbb03baadba
- Created a pluggable COM layer
- Converted COM + USART init into static initializers
rather than typedefs
- Generalized the USB HID COM API to match the USART
API.
- Changed USART and COM layers to be data driven rather
than #ifdef'ing/switching on the specifics of each port
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@760 ebee16cc-31ac-478f-84a7-5cbb03baadba
Added support for SPI slave configurations to the pios SPI layer.
Converted the board specific configuration for the PIOS SPI layer to
use const static initializers rather than #defines (see pios_board.c).
SPI interface between the OP board and the AHRS is now operational at
a basic level, capable of moving simple single byte messages between
boards. Multi-byte, CRC protected messages will be added on top of this.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@759 ebee16cc-31ac-478f-84a7-5cbb03baadba
Many of the STM32 library functions take a pointer to an
initialization structure. In nearly every case, this struct
is a read-only (ie. const) parameter.
It is advantageous (and good coding practice) to actually declare
read-only data as const so that the compiler can place the const data
in the .rodata section which resides in flash and doesn't consume any
RAM. This has the added bonus advantage that it is impossible for the
running application to corrupt the read-only data.
In order to allow passing pointers to const data into the library
functions, it is essential that the function prototypes also declare
their associated read-only parameters as const. This commit adds
the const attribute to those parameters that are actually read-only.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@758 ebee16cc-31ac-478f-84a7-5cbb03baadba
No functionality changed. Clean up only.
Changed a few of the (1 << x) constructs to use existing macro
definitions to improve code readability.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@757 ebee16cc-31ac-478f-84a7-5cbb03baadba
No functionality changed. Clean up only.
Make early init code (Reset_Handler) use the existing irq stack
rather than the hard-coded one.
Remove (now) unused references to the hard-coded stack.
Removed the link-time check for a minimal task stack in RAM since
FreeRTOS allocates user stacks from the heap which is already reserved
in the .bss section (as symbol xHeap).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@756 ebee16cc-31ac-478f-84a7-5cbb03baadba
The previous fix in r652 was _almost_ right. There was
still a one word (4-byte) overlap between _irq_stack_top
and the start of the data segment.
_irq_stack_end + _irq_stack_size leaves the '.' pointer at
the word immediatly after the stack. This commit corrects
this error and places _irq_stack_top on the last word
_inside_ the reserved space for the irq stack.
[Before]
$ ./tools/arm-2009q3/bin/arm-none-eabi-nm -n ./build/openpilot/OpenPilot.elf
...
20000000 A SRAM_BASE
20000000 B _irq_stack_end
20000400 d LED_GPIO_PORT <--- overlap
20000400 B _irq_stack_top <--- overlap
20000400 D _sdata
20000408 d ADC_GPIO_PORT
...
[After]
$ ./tools/arm-2009q3/bin/arm-none-eabi-nm -n ./build/openpilot/OpenPilot.elf
...
20000000 A SRAM_BASE
20000000 B _irq_stack_end
200003fc B _irq_stack_top
20000400 d LED_GPIO_PORT
20000400 D _sdata
20000408 d ADC_GPIO_PORT
...
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@668 ebee16cc-31ac-478f-84a7-5cbb03baadba
This commit fixes all existing warnings.
All basic compiler warnings will now be treated as errors.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@658 ebee16cc-31ac-478f-84a7-5cbb03baadba
This fixes the COM interface over USB HID to the point where
it can establish and maintain solid communications with the UAVObject
Browser in the GCS.
Tested only on Linux. The USB HID interface is still disabled for now
until it is tested successfully by a wider group.
Edit telemetry.c and set ALLOW_HID_TELEMETRY to 1 to enable telemetry
over the USB HID interface and report your results in the forum.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@656 ebee16cc-31ac-478f-84a7-5cbb03baadba
- New Attitude module for AHRS (skeleton)
- New AttitudeSettings UAVobject
- New AttitudeActual UAVobject
- Regenerated UAVobjects
- Added new UAVobjects to OpenPilot and GCS builds
- New PiOS driver for OpenPilot AHRS (stubs only)
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@655 ebee16cc-31ac-478f-84a7-5cbb03baadba
Since the EXTI and NVIC init routines automatically enable the IRQ when it
is configured, it is possible for the EOC interrupt to fire immediately
upon configuring the IRQ.
Since the handler for the EOC interrupt (EXTI15_10_IRQHandler) does a
xSemaphoreGiveFromISR, it is important to have the semaphore initialized
prior to enabling the interrupt.
Also, added missing include for altitude module.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@654 ebee16cc-31ac-478f-84a7-5cbb03baadba
The MSP (IRQ stack) was trampling across the data segment. This was
especially disastrous in the USB interrupts since they allocate and
fill buffers on the stack.
The root of this trampling was that no RAM was being reserved for the
MSP and a hard-coded value of (0x20000400) was used as the initial MSP
base address. This resulted in the first 1K bytes of the .data segment
overlapping with the IRQ stack. As can be expected, all sorts of badness
resulted when interrupts were firing and trampling over variables.
This change reserves the first _isr_stack_size bytes at the beginning of
RAM for the MSP. If an ISR call chain runs off of the end of the MSP,
a Hard Fault will be generated as the (now invalid) sp is accessed.
There are two stack pointers in the Cortex-M3 CPU. These are MSP (Main
Stack Pointer) and PSP (Process Stack Pointer).
Which stack is in use at any given time is determined by the following table:
Mode CONTROL[ASPSEL] Stack
---- --------------- -----
Thread 0 MSP
Thread 1 PSP
Handler x MSP
Out of reset, the CPU is in Thread mode using the MSP. The initial value
of the MSP is automatically loaded from address 0 (lowest word in boot
region -- typically FLASH) immediately prior to jumping to the reset vector.
When running at interrupt level, the Cortex-M3 always uses the MSP and the
ASPSEL bit is forced to zero.
FreeRTOS allocates a separate stack for each task upon task creation. These
task stacks are allocated from the heap. FreeRTOS sets the active stack to
the PSP whenever running in a task context (both in privileged mode and user
mode).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@652 ebee16cc-31ac-478f-84a7-5cbb03baadba
This module reads from the BMP085 pressure sensor. It periodically
updates the pressure (kPa) and temperature (C) as well as the
calculated altitude (m).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@640 ebee16cc-31ac-478f-84a7-5cbb03baadba
FreeRTOS has a strict requirement that even interrupt-safe API calls (ie.
those ending in "FromISR") can only be called from ISRs that are at lesser
or equal priorities to configMAX_SYSCALL_INTERRUPT_PRIORITY. See the
"configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY"
section at:
http://www.freertos.org/a00110.html
The interrupt numbers used on the Cortex-M3 CPU has a somewhat backward
representation of the interrupt numbers so 255 = lowest priority and
0 = highest priority.
The calculation is further complicated by the STM32 implementation only using
the upper 4 bits of the priority value. Only 0x00, 0x10, 0x20, ..., 0xE0, 0xF0
represent useful interrupt priorities.
FreeRTOS requires that MAX_SYSCALL and KERNEL interrupt priorities are expressed
as raw unshifted 8-bit values to be programmed directly into the BASEPRI register.
The priority values passed to the NVIC initialization, however, are expected
to be 4-bit values and are shifted up by 4 within NVIC_Init() for you.
The end result is that we need this arrangement:
[highest priority]
NVIC_0 (Non-maskable-interrupt)
NVIC_1
NVIC_2
[Must NOT call FreeRTOS APIs above here]
configMAX_SYSCALL_INTERRUPT_PRIORITY (now at 48 = 0x30 = NVIC_3)
PIOS_IRQ_PRIO_HIGHEST (cur. NVIC_4)
PIOS_IRQ_PRIO_HIGH (cur. NVIC_5)
PIOS_IRQ_PRIO_MID (cur. NVIC_8)
PIOS_IRQ_PRIO_LOW (cur. NVIC_12)
configKERNEL_INTERRUPT_PRIORITY (240 = 0xF0 = NVIC_15)
[lowest priority]
The previous config had configMAX_SYSCALL_INTERRUPT_PRIORITY set at
191 (0xBF) which is effectively NVIC_11. This was allowing all of
the MID, HIGH and HIGHEST interrupt handlers to preempt the OS in
its critical sections. Since some of these ISRs were calling
FreeRTOS APIs, this would result in corrupting internal data structures
within the OS.
It should be ok to move the configKERNEL_INTERRUPT_PRIORITY to a higher
priority as long as it is less than configMAX_SYSCALL_INTERRUPT_PRIORITY.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@637 ebee16cc-31ac-478f-84a7-5cbb03baadba
PIOS_SYS: Added system reset function.
OpenPilot Makefile: Default USE_BOOTLOADER should be NO.
OpenPilot Bootloader: Removed LED initialisation.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@303 ebee16cc-31ac-478f-84a7-5cbb03baadba
