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Commit Graph

5 Commits

Author SHA1 Message Date
peabody124
00a3e82c70 CC-6 PIOS/SPI: Add semaphore to SPI device structure that can be used to ensure
only one CS line is asserted.  No checks are enforced on this by the SPI code
as I cant see a clean way of it being aware of the CS lines.  We could add
another CS mode those which is driver managed per transfer and has a GPIO i
line for each device.

git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2579 ebee16cc-31ac-478f-84a7-5cbb03baadba
2011-01-24 07:52:17 +00:00
peabody124
3c021c09d9 Flight/PiOS: Whitespace changes
find ./flight/PiOS/inc/ \! \( -name '*~' -a -prune \) -type f    | xargs -I{}
bash -c 'echo {}; dos2unix {}; gnuindent -npro -kr -i8 -ts8 -sob -ss -ncs -cp1
-il0 -hnl -l150 {};'

git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1777 ebee16cc-31ac-478f-84a7-5cbb03baadba
2010-09-27 07:28:45 +00:00
peabody124
d928676f5e More documentation updates, standardizing format to include addtogroup at the beginning of headers so files are associated with modules
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1121 ebee16cc-31ac-478f-84a7-5cbb03baadba
2010-07-16 19:53:35 +00:00
stac
a3a2dbd634 spi: Add support for hardware CRC generation/checking
PIOS SPI devices may now make use of automatic CRC generation
and checking on block transfers.  Only supports CRC8 for now.

Since the SPI interface CRC calculation continues across message
boundaries (ie. not reset on every transfer), we must manually reset
the CRC registers for every transfer to allow the two sides of the
link to resynchronize.

Unfortunately, resetting the CRC registers requires disabling the
SPI peripheral which must now be done on every block transfer.

Note: The last byte of the tx buffer is never sent and is assumed to
      be a place holder for the tx CRC8.
Note: The last byte of the rx buffer is expected to hold the rx CRC8.

git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1011 ebee16cc-31ac-478f-84a7-5cbb03baadba
2010-07-04 02:21:42 +00:00
stac
8d015a57d0 pios spi: support both master and slave configs
Added support for SPI slave configurations to the pios SPI layer.

Converted the board specific configuration for the PIOS SPI layer to
use const static initializers rather than #defines (see pios_board.c).

SPI interface between the OP board and the AHRS is now operational at
a basic level, capable of moving simple single byte messages between
boards.  Multi-byte, CRC protected messages will be added on top of this.

git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@759 ebee16cc-31ac-478f-84a7-5cbb03baadba
2010-06-13 04:23:44 +00:00