The EOC EXTI interrupt configuration was incorrectly
pointing at GPIOG pin 8 rather than GPIOC pin 15.
This was preventing the EOC interrupt from working
properly.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1626 ebee16cc-31ac-478f-84a7-5cbb03baadba
No functional changes.
The closing comment on some of the USB_HID related
ifdefs was outdated. Fixed.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1541 ebee16cc-31ac-478f-84a7-5cbb03baadba
The STM32 I2C block has a number of errata associated with it.
These errata are primarily related to timing sensitivities between
the peripheral and the interrupt handler. In particular, the
correct generation of the stop bit relies on the I2C IRQ running
immediately and not being held off for any reason.
NOTE: The I2C interrupts must be the highest priority IRQs in the
system to ensure correct operation.
I2C protocol is now implemented as a formal state machine.
See: stm32_i2c_fsm.{dot,jpg} for FSM description.
I2C init is now expressed by const initializers in pios_board.c
for both OP and AHRS boards.
I2C device drivers (ie. bmp085/hmc5843) now pass in const arrays
of an unlimited number of bus transfers to be done atomically.
The I2C adapter driver now handles all bus-level locking across the
list of transactions. Generation of start/restart/stop conditions
are handled automatically over the list of transactions.
Timeouts have been removed from the API for now. May be added
back later.
This driver has run error free on both the OP and AHRS boards for
up to 48hrs but it still sometimes fails earlier than that on the OP
board. There is another possible set of improvements to the driver
that could employ the DMA engine for transfers of >= 2bytes. This
change would reduce the timing sensitivities between the peripheral
and the driver but unfortunately, both the SPI and I2C interfaces
share the DMA1 engine. That means only one of these two peripherals
can use the DMA engine and right now, SPI between OP and AHRS is
already using it.
Failures are currently fatal and will lock up the CPU. This allows
useful information to be obtained in the failure cases.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1241 ebee16cc-31ac-478f-84a7-5cbb03baadba
- syntax error in pios_board_posix.c introduced with Doxygen comment blocks
- platform dependant code had been added to openpilot.c instead of pios_board.c
- redundant header inclusion (stm32... already included by PiOS)
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1171 ebee16cc-31ac-478f-84a7-5cbb03baadba
PIOS SPI devices may now make use of automatic CRC generation
and checking on block transfers. Only supports CRC8 for now.
Since the SPI interface CRC calculation continues across message
boundaries (ie. not reset on every transfer), we must manually reset
the CRC registers for every transfer to allow the two sides of the
link to resynchronize.
Unfortunately, resetting the CRC registers requires disabling the
SPI peripheral which must now be done on every block transfer.
Note: The last byte of the tx buffer is never sent and is assumed to
be a place holder for the tx CRC8.
Note: The last byte of the rx buffer is expected to hold the rx CRC8.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1011 ebee16cc-31ac-478f-84a7-5cbb03baadba
The input data lines between the OP and AHRS boards had internal
pull-ups enabled. This seemed to be causing issues early on
during development of the inter-board comms. Not sure if this
is still necessary but this is how the current code was tested.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1006 ebee16cc-31ac-478f-84a7-5cbb03baadba
Mark the device specific DMA IRQ handlers as strongly linked
aliases for the genericly named interrupt vector symbol.
Here's how this works...
* The address of the symbol DMA1_Channel2_IRQHandler is written
into the DMA1/Channel2 interrupt vector by the linker script.
* The startup_*.S file specifies Default_Handler() as a weakly
linked alias for DMA1_Channel2_IRQHandler.
* We now override the weakly linked alias with the strongly linked
PIOS_SPI_sdcard_irq_handler().
* This results in the address of PIOS_SPI_sdcard_irq_handler() being
written to the vector table for the DMA1/Channel2 interrupt.
* The PIOS_SPI_sdcard_irq_handler() function is now called whenever
the DMA1/Channel2 interrupt fires.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1003 ebee16cc-31ac-478f-84a7-5cbb03baadba
- Created a pluggable COM layer
- Converted COM + USART init into static initializers
rather than typedefs
- Generalized the USB HID COM API to match the USART
API.
- Changed USART and COM layers to be data driven rather
than #ifdef'ing/switching on the specifics of each port
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@760 ebee16cc-31ac-478f-84a7-5cbb03baadba
Added support for SPI slave configurations to the pios SPI layer.
Converted the board specific configuration for the PIOS SPI layer to
use const static initializers rather than #defines (see pios_board.c).
SPI interface between the OP board and the AHRS is now operational at
a basic level, capable of moving simple single byte messages between
boards. Multi-byte, CRC protected messages will be added on top of this.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@759 ebee16cc-31ac-478f-84a7-5cbb03baadba
Both EVents and ERrors were mistakenly being mapped to the
EVent IRQ channel.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@659 ebee16cc-31ac-478f-84a7-5cbb03baadba
This commit fixes all existing warnings.
All basic compiler warnings will now be treated as errors.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@658 ebee16cc-31ac-478f-84a7-5cbb03baadba
This fixes the COM interface over USB HID to the point where
it can establish and maintain solid communications with the UAVObject
Browser in the GCS.
Tested only on Linux. The USB HID interface is still disabled for now
until it is tested successfully by a wider group.
Edit telemetry.c and set ALLOW_HID_TELEMETRY to 1 to enable telemetry
over the USB HID interface and report your results in the forum.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@656 ebee16cc-31ac-478f-84a7-5cbb03baadba
- New Attitude module for AHRS (skeleton)
- New AttitudeSettings UAVobject
- New AttitudeActual UAVobject
- Regenerated UAVobjects
- Added new UAVobjects to OpenPilot and GCS builds
- New PiOS driver for OpenPilot AHRS (stubs only)
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@655 ebee16cc-31ac-478f-84a7-5cbb03baadba
This module reads from the BMP085 pressure sensor. It periodically
updates the pressure (kPa) and temperature (C) as well as the
calculated altitude (m).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@640 ebee16cc-31ac-478f-84a7-5cbb03baadba
FreeRTOS has a strict requirement that even interrupt-safe API calls (ie.
those ending in "FromISR") can only be called from ISRs that are at lesser
or equal priorities to configMAX_SYSCALL_INTERRUPT_PRIORITY. See the
"configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY"
section at:
http://www.freertos.org/a00110.html
The interrupt numbers used on the Cortex-M3 CPU has a somewhat backward
representation of the interrupt numbers so 255 = lowest priority and
0 = highest priority.
The calculation is further complicated by the STM32 implementation only using
the upper 4 bits of the priority value. Only 0x00, 0x10, 0x20, ..., 0xE0, 0xF0
represent useful interrupt priorities.
FreeRTOS requires that MAX_SYSCALL and KERNEL interrupt priorities are expressed
as raw unshifted 8-bit values to be programmed directly into the BASEPRI register.
The priority values passed to the NVIC initialization, however, are expected
to be 4-bit values and are shifted up by 4 within NVIC_Init() for you.
The end result is that we need this arrangement:
[highest priority]
NVIC_0 (Non-maskable-interrupt)
NVIC_1
NVIC_2
[Must NOT call FreeRTOS APIs above here]
configMAX_SYSCALL_INTERRUPT_PRIORITY (now at 48 = 0x30 = NVIC_3)
PIOS_IRQ_PRIO_HIGHEST (cur. NVIC_4)
PIOS_IRQ_PRIO_HIGH (cur. NVIC_5)
PIOS_IRQ_PRIO_MID (cur. NVIC_8)
PIOS_IRQ_PRIO_LOW (cur. NVIC_12)
configKERNEL_INTERRUPT_PRIORITY (240 = 0xF0 = NVIC_15)
[lowest priority]
The previous config had configMAX_SYSCALL_INTERRUPT_PRIORITY set at
191 (0xBF) which is effectively NVIC_11. This was allowing all of
the MID, HIGH and HIGHEST interrupt handlers to preempt the OS in
its critical sections. Since some of these ISRs were calling
FreeRTOS APIs, this would result in corrupting internal data structures
within the OS.
It should be ok to move the configKERNEL_INTERRUPT_PRIORITY to a higher
priority as long as it is less than configMAX_SYSCALL_INTERRUPT_PRIORITY.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@637 ebee16cc-31ac-478f-84a7-5cbb03baadba
Commit @583 uncomments the HIDTest task creation. HIDTest task is configured to run at
priority 4 (== tskIDLE_PRIORITY + 4) which is higher priority than the "System" task at
priority 3 (== tskIDLE_PRIORITY + 3).
The HIDTest task never blocks so it prevents the system task (and any other task of priority
less than 4) from ever running.
This commit does not fix the root problem of HIDTest never blocking, but rather lowers
its priority to be equal to the system task so that they share the CPU. This is a
temporary workaround.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@586 ebee16cc-31ac-478f-84a7-5cbb03baadba
Added timer usage diagram to pios_board.h
Removed bloat for extra optimisation in PIOS_DELAY.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@265 ebee16cc-31ac-478f-84a7-5cbb03baadba
