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4847a04db8
TIM5-8. Also TIM1 was not handled probably (for CC either) as the name of the IRQ is TIM1_CC and TIM1_UP for the capture compare versus update. I haven't checked the downstream code that the registers it uses to map from a context to event is invariant under timer channel.
428 lines
11 KiB
C
428 lines
11 KiB
C
#include "pios.h"
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#include "pios_tim.h"
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#include "pios_tim_priv.h"
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enum pios_tim_dev_magic {
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PIOS_TIM_DEV_MAGIC = 0x87654098,
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};
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struct pios_tim_dev {
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enum pios_tim_dev_magic magic;
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const struct pios_tim_channel * channels;
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uint8_t num_channels;
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const struct pios_tim_callbacks * callbacks;
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uint32_t context;
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};
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#if 0
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static bool PIOS_TIM_validate(struct pios_tim_dev * tim_dev)
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{
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return (tim_dev->magic == PIOS_TIM_DEV_MAGIC);
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}
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#endif
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#if defined(PIOS_INCLUDE_FREERTOS) && 0
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static struct pios_tim_dev * PIOS_TIM_alloc(void)
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{
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struct pios_tim_dev * tim_dev;
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tim_dev = (struct pios_tim_dev *)malloc(sizeof(*tim_dev));
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if (!tim_dev) return(NULL);
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tim_dev->magic = PIOS_TIM_DEV_MAGIC;
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return(tim_dev);
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}
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#else
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static struct pios_tim_dev pios_tim_devs[PIOS_TIM_MAX_DEVS];
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static uint8_t pios_tim_num_devs;
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static struct pios_tim_dev * PIOS_TIM_alloc(void)
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{
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struct pios_tim_dev * tim_dev;
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if (pios_tim_num_devs >= PIOS_TIM_MAX_DEVS) {
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return (NULL);
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}
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tim_dev = &pios_tim_devs[pios_tim_num_devs++];
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tim_dev->magic = PIOS_TIM_DEV_MAGIC;
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return (tim_dev);
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}
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#endif
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int32_t PIOS_TIM_InitClock(const struct pios_tim_clock_cfg * cfg)
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{
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PIOS_DEBUG_Assert(cfg);
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/* Enable appropriate clock to timer module */
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switch((uint32_t) cfg->timer) {
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case (uint32_t)TIM1:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
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break;
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case (uint32_t)TIM2:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
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break;
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case (uint32_t)TIM3:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
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break;
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case (uint32_t)TIM4:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
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break;
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#ifdef STM32F10X_HD
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case (uint32_t)TIM5:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
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break;
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case (uint32_t)TIM6:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
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break;
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case (uint32_t)TIM7:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);
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break;
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case (uint32_t)TIM8:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
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break;
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#endif
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}
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/* Configure the dividers for this timer */
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TIM_TimeBaseInit(cfg->timer, cfg->time_base_init);
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/* Configure internal timer clocks */
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TIM_InternalClockConfig(cfg->timer);
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/* Enable timers */
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TIM_Cmd(cfg->timer, ENABLE);
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/* Enable Interrupts */
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NVIC_Init(&cfg->irq.init);
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return 0;
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}
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int32_t PIOS_TIM_InitChannels(uint32_t * tim_id, const struct pios_tim_channel * channels, uint8_t num_channels, const struct pios_tim_callbacks * callbacks, uint32_t context)
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{
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PIOS_Assert(channels);
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PIOS_Assert(num_channels);
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struct pios_tim_dev * tim_dev;
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tim_dev = (struct pios_tim_dev *) PIOS_TIM_alloc();
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if (!tim_dev) goto out_fail;
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/* Bind the configuration to the device instance */
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tim_dev->channels = channels;
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tim_dev->num_channels = num_channels;
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tim_dev->callbacks = callbacks;
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tim_dev->context = context;
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/* Configure the pins */
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for (uint8_t i = 0; i < num_channels; i++) {
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const struct pios_tim_channel * chan = &(channels[i]);
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/* Enable the peripheral clock for the GPIO */
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switch ((uint32_t)chan->pin.gpio) {
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case (uint32_t) GPIOA:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
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break;
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case (uint32_t) GPIOB:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
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break;
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case (uint32_t) GPIOC:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
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break;
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default:
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PIOS_Assert(0);
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break;
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}
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GPIO_Init(chan->pin.gpio, &chan->pin.init);
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if (chan->remap) {
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GPIO_PinRemapConfig(chan->remap, ENABLE);
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}
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}
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*tim_id = (uint32_t)tim_dev;
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return(0);
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out_fail:
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return(-1);
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}
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static void PIOS_TIM_generic_irq_handler(TIM_TypeDef * timer)
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{
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/* Iterate over all registered clients of the TIM layer to find channels on this timer */
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for (uint8_t i = 0; i < pios_tim_num_devs; i++) {
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const struct pios_tim_dev * tim_dev = &pios_tim_devs[i];
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if (!tim_dev->channels || tim_dev->num_channels == 0) {
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/* No channels to process on this client */
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continue;
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}
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/* Check for an overflow event on this timer */
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bool overflow_event;
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uint16_t overflow_count;
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if (TIM_GetITStatus(timer, TIM_IT_Update) == SET) {
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TIM_ClearITPendingBit(timer, TIM_IT_Update);
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overflow_count = timer->ARR;
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overflow_event = true;
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} else {
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overflow_count = 0;
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overflow_event = false;
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}
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for (uint8_t j = 0; j < tim_dev->num_channels; j++) {
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const struct pios_tim_channel * chan = &tim_dev->channels[j];
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if (chan->timer != timer) {
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/* channel is not on this timer */
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continue;
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}
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/* Figure out which interrupt bit we should be looking at */
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uint16_t timer_it;
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switch (chan->timer_chan) {
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case TIM_Channel_1:
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timer_it = TIM_IT_CC1;
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break;
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case TIM_Channel_2:
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timer_it = TIM_IT_CC2;
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break;
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case TIM_Channel_3:
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timer_it = TIM_IT_CC3;
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break;
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case TIM_Channel_4:
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timer_it = TIM_IT_CC4;
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break;
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default:
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PIOS_Assert(0);
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break;
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}
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bool edge_event;
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uint16_t edge_count;
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if (TIM_GetITStatus(chan->timer, timer_it) == SET) {
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TIM_ClearITPendingBit(chan->timer, timer_it);
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/* Read the current counter */
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switch(chan->timer_chan) {
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case TIM_Channel_1:
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edge_count = TIM_GetCapture1(chan->timer);
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break;
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case TIM_Channel_2:
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edge_count = TIM_GetCapture2(chan->timer);
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break;
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case TIM_Channel_3:
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edge_count = TIM_GetCapture3(chan->timer);
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break;
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case TIM_Channel_4:
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edge_count = TIM_GetCapture4(chan->timer);
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break;
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default:
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PIOS_Assert(0);
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break;
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}
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edge_event = true;
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} else {
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edge_event = false;
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edge_count = 0;
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}
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if (!tim_dev->callbacks) {
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/* No callbacks registered, we're done with this channel */
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continue;
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}
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/* Generate the appropriate callbacks */
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if (overflow_event & edge_event) {
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/*
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* When both edge and overflow happen in the same interrupt, we
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* need a heuristic to determine the order of the edge and overflow
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* events so that the callbacks happen in the right order. If we
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* get the order wrong, our pulse width calculations could be off by up
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* to ARR ticks. That could be bad.
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*
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* Heuristic: If the edge_count is < 16 ticks above zero then we assume the
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* edge happened just after the overflow.
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*/
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if (edge_count < 16) {
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/* Call the overflow callback first */
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if (tim_dev->callbacks->overflow) {
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(*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
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tim_dev->context,
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j,
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overflow_count);
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}
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/* Call the edge callback second */
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if (tim_dev->callbacks->edge) {
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(*tim_dev->callbacks->edge)((uint32_t)tim_dev,
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tim_dev->context,
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j,
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edge_count);
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}
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} else {
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/* Call the edge callback first */
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if (tim_dev->callbacks->edge) {
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(*tim_dev->callbacks->edge)((uint32_t)tim_dev,
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tim_dev->context,
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j,
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edge_count);
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}
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/* Call the overflow callback second */
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if (tim_dev->callbacks->overflow) {
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(*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
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tim_dev->context,
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j,
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overflow_count);
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}
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}
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} else if (overflow_event && tim_dev->callbacks->overflow) {
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(*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
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tim_dev->context,
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j,
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overflow_count);
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} else if (edge_event && tim_dev->callbacks->edge) {
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(*tim_dev->callbacks->edge)((uint32_t)tim_dev,
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tim_dev->context,
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j,
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edge_count);
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}
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}
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}
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}
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#if 0
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uint16_t val = 0;
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for(uint8_t i = 0; i < pios_pwm_cfg.num_channels; i++) {
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struct pios_pwm_channel channel = pios_pwm_cfg.channels[i];
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if ((channel.timer == timer) && (TIM_GetITStatus(channel.timer, channel.ccr) == SET)) {
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TIM_ClearITPendingBit(channel.timer, channel.ccr);
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switch(channel.channel) {
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case TIM_Channel_1:
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val = TIM_GetCapture1(channel.timer);
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break;
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case TIM_Channel_2:
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val = TIM_GetCapture2(channel.timer);
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break;
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case TIM_Channel_3:
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val = TIM_GetCapture3(channel.timer);
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break;
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case TIM_Channel_4:
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val = TIM_GetCapture4(channel.timer);
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break;
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}
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if (CaptureState[i] == 0) {
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RiseValue[i] = val;
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} else {
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FallValue[i] = val;
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}
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// flip state machine and capture value here
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/* Simple rise or fall state machine */
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TIM_ICInitTypeDef TIM_ICInitStructure = pios_pwm_cfg.tim_ic_init;
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if (CaptureState[i] == 0) {
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/* Switch states */
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CaptureState[i] = 1;
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/* Switch polarity of input capture */
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TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;
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TIM_ICInitStructure.TIM_Channel = channel.channel;
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TIM_ICInit(channel.timer, &TIM_ICInitStructure);
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} else {
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/* Capture computation */
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if (FallValue[i] > RiseValue[i]) {
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CaptureValue[i] = (FallValue[i] - RiseValue[i]);
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} else {
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CaptureValue[i] = ((channel.timer->ARR - RiseValue[i]) + FallValue[i]);
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}
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/* Switch states */
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CaptureState[i] = 0;
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/* Increase supervisor counter */
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CapCounter[i]++;
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/* Switch polarity of input capture */
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TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
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TIM_ICInitStructure.TIM_Channel = channel.channel;
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TIM_ICInit(channel.timer, &TIM_ICInitStructure);
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}
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}
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}
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#endif
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/* Bind Interrupt Handlers
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*
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* Map all valid TIM IRQs to the common interrupt handler
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* and give it enough context to properly demux the various timers
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*/
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void TIM1_UP_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_1_UP_irq_handler")));
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static void PIOS_TIM_1_UP_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM1);
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}
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void TIM1_CC_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_1_CC_irq_handler")));
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static void PIOS_TIM_1_CC_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM1);
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}
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void TIM2_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_2_irq_handler")));
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static void PIOS_TIM_2_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM2);
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}
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void TIM3_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_3_irq_handler")));
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static void PIOS_TIM_3_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM3);
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}
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void TIM4_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_4_irq_handler")));
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static void PIOS_TIM_4_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM4);
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}
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void TIM5_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_5_irq_handler")));
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static void PIOS_TIM_5_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM5);
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}
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void TIM6_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_6_irq_handler")));
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static void PIOS_TIM_6_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM6);
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}
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void TIM7_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_7_irq_handler")));
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static void PIOS_TIM_7_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM7);
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}
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void TIM8_UP_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_8_UP_irq_handler")));
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static void PIOS_TIM_8_UP_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM8);
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}
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void TIM8_CC_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_8_CC_irq_handler")));
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static void PIOS_TIM_8_CC_irq_handler (void)
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{
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PIOS_TIM_generic_irq_handler (TIM8);
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}
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