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70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/**
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******************************************************************************
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*
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* @file pios_helpers.h
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* @brief Header for helper functions/macro definitions
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*
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* @see The GNU Public License (GPL) Version 3
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef PIOS_HELPERS_H
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#define PIOS_HELPERS_H
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/**
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* @brief return the number of elements contained in the array x.
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* @param[in] x the array
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* @return number of elements in x.
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*
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*/
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#define NELEMENTS(x) (sizeof(x) / sizeof((x)[0]))
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/**
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* @brief Compiler barrier: Disables compiler load/store reordering across the barrier
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*
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*/
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#define COMPILER_BARRIER() asm volatile ("" ::: "memory")
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// Memory barriers:
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// Note that on single core Cortex M3 & M4, the is generally no need to use a processor memory barrier instruction such as DMB.
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// See http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf
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// However, it makes sense to use these if we want to reduce issues if we ever port to a multicore processor in the future.
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// An important exception for STM32 is when setting up the DMA engine - see the above reference for details.
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/**
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* @brief Read Acquire memory barrier
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*/
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#define READ_MEMORY_BARRIER() COMPILER_BARRIER()
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/**
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* @brief Write Release memory barrier
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*/
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#define WRITE_MEMORY_BARRIER() COMPILER_BARRIER()
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/**
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* @brief Full fence memory barrier
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*/
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#define MEMORY_BARRIER() COMPILER_BARRIER()
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// For future multicore ARM v7 or later:
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// The above three macros would be replaced with: asm volatile("dmb":::"memory")
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#endif // PIOS_HELPERS_H
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