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92 lines
3.4 KiB
C
92 lines
3.4 KiB
C
/**
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******************************************************************************
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* @addtogroup OpenPilotBL OpenPilot BootLoader
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* @{
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*
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* @file ssp_timer.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* @brief Timer functions to be used with the SSP.
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* @see The GNU Public License (GPL) Version 3
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/////////////////////////////////////////////////////////////////////////////
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// Include files
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/////////////////////////////////////////////////////////////////////////////
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#include "stm32f10x_tim.h"
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/////////////////////////////////////////////////////////////////////////////
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// Local definitions
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/////////////////////////////////////////////////////////////////////////////
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#define SSP_TIMER_TIMER_BASE TIM7
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#define SSP_TIMER_TIMER_RCC RCC_APB1Periph_TIM7
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uint32_t SSP_TIMER_Init(u32 resolution) {
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// enable timer clock
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if (SSP_TIMER_TIMER_RCC == RCC_APB2Periph_TIM1 || SSP_TIMER_TIMER_RCC
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== RCC_APB2Periph_TIM8)
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RCC_APB2PeriphClockCmd(SSP_TIMER_TIMER_RCC, ENABLE);
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else
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RCC_APB1PeriphClockCmd(SSP_TIMER_TIMER_RCC, ENABLE);
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// time base configuration
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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TIM_TimeBaseStructure.TIM_Period = 0xffff; // max period
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TIM_TimeBaseStructure.TIM_Prescaler = (72 * resolution) - 1; // <resolution> uS accuracy @ 72 MHz
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInit(SSP_TIMER_TIMER_BASE, &TIM_TimeBaseStructure);
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// enable interrupt request
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TIM_ITConfig(SSP_TIMER_TIMER_BASE, TIM_IT_Update, ENABLE);
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// start counter
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TIM_Cmd(SSP_TIMER_TIMER_BASE, ENABLE);
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return 0; // no error
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}
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/////////////////////////////////////////////////////////////////////////////
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//! Resets the SSP_TIMER
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//! \return < 0 on errors
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/////////////////////////////////////////////////////////////////////////////
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uint32_t SSP_TIMER_Reset(void) {
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// reset counter
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SSP_TIMER_TIMER_BASE->CNT = 1; // set to 1 instead of 0 to avoid new IRQ request
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TIM_ClearITPendingBit(SSP_TIMER_TIMER_BASE, TIM_IT_Update);
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return 0; // no error
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}
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/////////////////////////////////////////////////////////////////////////////
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//! Returns current value of SSP_TIMER
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//! \return 1..65535: valid SSP_TIMER value
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//! \return 0xffffffff: counter overrun
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/////////////////////////////////////////////////////////////////////////////
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uint32_t SSP_TIMER_ValueGet(void) {
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uint32_t value = SSP_TIMER_TIMER_BASE->CNT;
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if (TIM_GetITStatus(SSP_TIMER_TIMER_BASE, TIM_IT_Update) != RESET)
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SSP_TIMER_Reset();
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return value;
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}
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