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474 lines
16 KiB
C
474 lines
16 KiB
C
/**
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @addtogroup PIOS_VIDEO Code for OSD video generator
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* @brief OSD generator, Parts from CL-OSD and SUPEROSD project
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* @{
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*
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* @file pios_video.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* @brief OSD generator, Parts from CL-OSD and SUPEROSD projects
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* @see The GNU Public License (GPL) Version 3
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*
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******************************************************************************
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "pios.h"
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#ifdef PIOS_INCLUDE_VIDEO
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// Private methods
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static void configure_hsync_timers();
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static void stop_hsync_timers();
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static void reset_hsync_timers();
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static void prepare_line(uint32_t line_num);
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static void flush_spi();
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// Private variables
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extern xSemaphoreHandle osdSemaphore;
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static const struct pios_video_cfg *dev_cfg;
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// Define the buffers.
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// For 256x192 pixel mode:
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// buffer0_level/buffer0_mask becomes buffer_level; and
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// buffer1_level/buffer1_mask becomes buffer_mask;
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// For 192x128 pixel mode, allocations are as the names are written.
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// divide by 8 because two bytes to a word.
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// Must be allocated in one block, so it is in a struct.
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struct _buffers {
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uint8_t buffer0_level[GRAPHICS_HEIGHT * GRAPHICS_WIDTH];
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uint8_t buffer0_mask[GRAPHICS_HEIGHT * GRAPHICS_WIDTH];
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uint8_t buffer1_level[GRAPHICS_HEIGHT * GRAPHICS_WIDTH];
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uint8_t buffer1_mask[GRAPHICS_HEIGHT * GRAPHICS_WIDTH];
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} buffers;
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// Remove the struct definition (makes it easier to write for.)
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#define buffer0_level (buffers.buffer0_level)
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#define buffer0_mask (buffers.buffer0_mask)
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#define buffer1_level (buffers.buffer1_level)
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#define buffer1_mask (buffers.buffer1_mask)
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// We define pointers to each of these buffers.
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uint8_t *draw_buffer_level;
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uint8_t *draw_buffer_mask;
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uint8_t *disp_buffer_level;
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uint8_t *disp_buffer_mask;
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volatile uint8_t gLineType = LINE_TYPE_UNKNOWN;
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volatile uint16_t gActiveLine = 0;
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volatile uint16_t gActivePixmapLine = 0;
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volatile uint16_t line = 0;
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volatile uint16_t Vsync_update = 0;
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volatile uint16_t Hsync_update = 0;
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static int16_t m_osdLines = 0;
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/**
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* swap_buffers: Swaps the two buffers. Contents in the display
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* buffer is seen on the output and the display buffer becomes
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* the new draw buffer.
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*/
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void swap_buffers()
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{
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// While we could use XOR swap this is more reliable and
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// dependable and it's only called a few times per second.
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// Many compliers should optimise these to EXCH instructions.
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uint8_t *tmp;
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SWAP_BUFFS(tmp, disp_buffer_mask, draw_buffer_mask);
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SWAP_BUFFS(tmp, disp_buffer_level, draw_buffer_level);
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}
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bool PIOS_Hsync_ISR()
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{
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// On tenth line prepare data which will start clocking out on GRAPHICS_LINE+1
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if (Hsync_update == GRAPHICS_LINE) {
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prepare_line(0);
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gActiveLine = 1;
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}
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Hsync_update++;
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return true;
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}
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bool PIOS_Vsync_ISR()
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{
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static portBASE_TYPE xHigherPriorityTaskWoken;
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xHigherPriorityTaskWoken = pdFALSE;
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m_osdLines = gActiveLine;
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stop_hsync_timers();
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// Wait for previous word to clock out of each
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TIM_Cmd(dev_cfg->pixel_timer.timer, ENABLE);
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flush_spi();
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TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
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gActiveLine = 0;
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Hsync_update = 0;
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Vsync_update++;
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if (Vsync_update >= 2) {
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// load second image buffer
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swap_buffers();
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Vsync_update = 0;
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// trigger redraw every second field
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xHigherPriorityTaskWoken = xSemaphoreGiveFromISR(osdSemaphore, &xHigherPriorityTaskWoken);
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}
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken); // portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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return xHigherPriorityTaskWoken == pdTRUE;
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}
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uint16_t PIOS_Video_GetOSDLines(void)
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{
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return m_osdLines;
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}
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/**
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* Stops the pixel clock and ensures it ignores the rising edge. To be used after a
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* vsync until the first line is to be displayed
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*/
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static void stop_hsync_timers()
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{
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// This removes the slave mode configuration
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TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
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TIM_InternalClockConfig(dev_cfg->pixel_timer.timer);
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}
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const struct pios_tim_callbacks px_callback = {
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.overflow = NULL,
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.edge = NULL,
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};
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#ifdef PAL
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const uint32_t period = 10;
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const uint32_t dc = (10 / 2);
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#else
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const uint32_t period = 11;
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const uint32_t dc = (11 / 2);
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#endif
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/**
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* Reset the timer and configure for next call. Keeps them synced. Ideally this won't even be needed
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* since I don't think the slave mode gets lost, and this can simply be disable timer
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*/
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uint32_t failcount = 0;
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static void reset_hsync_timers()
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{
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// Stop both timers
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TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
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uint32_t tim_id;
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const struct pios_tim_channel *channels = &dev_cfg->hsync_capture;
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// BUG: This is nuts this line is needed. It simply results in allocating
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// all the memory but somehow leaving it out breaks the timer functionality.
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// I do not see how these can be related
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if (failcount == 0) {
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if (PIOS_TIM_InitChannels(&tim_id, channels, 1, &px_callback, 0) < 0) {
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failcount++;
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}
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}
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dev_cfg->pixel_timer.timer->CNT = 0xFFFF - 100; // dc;
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// Listen to Channel1 (HSYNC)
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switch (dev_cfg->hsync_capture.timer_chan) {
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case TIM_Channel_1:
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TIM_SelectInputTrigger(dev_cfg->pixel_timer.timer, TIM_TS_TI1FP1);
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break;
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case TIM_Channel_2:
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TIM_SelectInputTrigger(dev_cfg->pixel_timer.timer, TIM_TS_TI2FP2);
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break;
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default:
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PIOS_Assert(0);
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}
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TIM_SelectSlaveMode(dev_cfg->pixel_timer.timer, TIM_SlaveMode_Trigger);
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}
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static void configure_hsync_timers()
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{
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// Stop both timers
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TIM_Cmd(dev_cfg->pixel_timer.timer, DISABLE);
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// This is overkill but used for consistency. No interrupts used for pixel clock
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// but this function calls the GPIO_Remap
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uint32_t tim_id;
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const struct pios_tim_channel *channels;
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// Init the channel to output the pixel clock
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channels = &dev_cfg->pixel_timer;
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PIOS_TIM_InitChannels(&tim_id, channels, 1, &px_callback, 0);
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// Init the channel to capture the pulse
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channels = &dev_cfg->hsync_capture;
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PIOS_TIM_InitChannels(&tim_id, channels, 1, &px_callback, 0);
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// Configure the input capture channel
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TIM_ICInitTypeDef TIM_ICInitStructure;
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switch (dev_cfg->hsync_capture.timer_chan) {
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case TIM_Channel_1:
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TIM_ICInitStructure.TIM_Channel = TIM_Channel_1;
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break;
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case TIM_Channel_2:
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TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
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break;
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default:
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PIOS_Assert(0);
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}
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TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;
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// TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
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TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
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TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
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TIM_ICInitStructure.TIM_ICFilter = 0;
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TIM_ICInit(dev_cfg->pixel_timer.timer, &TIM_ICInitStructure);
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// Set up the channel to output the pixel clock
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switch (dev_cfg->pixel_timer.timer_chan) {
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case TIM_Channel_1:
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TIM_OC1Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
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TIM_OC1PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
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TIM_SetCompare1(dev_cfg->pixel_timer.timer, dc);
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break;
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case TIM_Channel_2:
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TIM_OC2Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
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TIM_OC2PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
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TIM_SetCompare2(dev_cfg->pixel_timer.timer, dc);
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break;
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case TIM_Channel_3:
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TIM_OC3Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
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TIM_OC3PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
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TIM_SetCompare3(dev_cfg->pixel_timer.timer, dc);
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break;
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case TIM_Channel_4:
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TIM_OC4Init(dev_cfg->pixel_timer.timer, &dev_cfg->tim_oc_init);
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TIM_OC4PreloadConfig(dev_cfg->pixel_timer.timer, TIM_OCPreload_Enable);
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TIM_SetCompare4(dev_cfg->pixel_timer.timer, dc);
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break;
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}
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TIM_ARRPreloadConfig(dev_cfg->pixel_timer.timer, ENABLE);
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TIM_CtrlPWMOutputs(dev_cfg->pixel_timer.timer, ENABLE);
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// This shouldn't be needed as it should come from the config struture. Something
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// is clobbering that
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TIM_PrescalerConfig(dev_cfg->pixel_timer.timer, 0, TIM_PSCReloadMode_Immediate);
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TIM_SetAutoreload(dev_cfg->pixel_timer.timer, period);
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}
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DMA_TypeDef *main_dma;
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DMA_TypeDef *mask_dma;
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DMA_Stream_TypeDef *main_stream;
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DMA_Stream_TypeDef *mask_stream;
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void PIOS_Video_Init(const struct pios_video_cfg *cfg)
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{
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dev_cfg = cfg; // store config before enabling interrupt
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configure_hsync_timers();
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/* needed for HW hack */
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const GPIO_InitTypeDef initStruct = {
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.GPIO_Pin = GPIO_Pin_12,
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.GPIO_Speed = GPIO_Speed_100MHz,
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.GPIO_Mode = GPIO_Mode_IN,
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.GPIO_OType = GPIO_OType_PP,
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.GPIO_PuPd = GPIO_PuPd_NOPULL
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};
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GPIO_Init(GPIOC, &initStruct);
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/* SPI3 - MASKBUFFER */
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GPIO_Init(cfg->mask.sclk.gpio, (GPIO_InitTypeDef *)&(cfg->mask.sclk.init));
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GPIO_Init(cfg->mask.miso.gpio, (GPIO_InitTypeDef *)&(cfg->mask.miso.init));
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/* SPI1 SLAVE FRAMEBUFFER */
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GPIO_Init(cfg->level.sclk.gpio, (GPIO_InitTypeDef *)&(cfg->level.sclk.init));
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GPIO_Init(cfg->level.miso.gpio, (GPIO_InitTypeDef *)&(cfg->level.miso.init));
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if (cfg->mask.remap) {
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GPIO_PinAFConfig(cfg->mask.sclk.gpio,
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__builtin_ctz(cfg->mask.sclk.init.GPIO_Pin),
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cfg->mask.remap);
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GPIO_PinAFConfig(cfg->mask.miso.gpio,
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__builtin_ctz(cfg->mask.miso.init.GPIO_Pin),
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cfg->mask.remap);
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}
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if (cfg->level.remap) {
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GPIO_PinAFConfig(cfg->level.sclk.gpio,
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__builtin_ctz(cfg->level.sclk.init.GPIO_Pin),
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cfg->level.remap);
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GPIO_PinAFConfig(cfg->level.miso.gpio,
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__builtin_ctz(cfg->level.miso.init.GPIO_Pin),
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cfg->level.remap);
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}
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/* Initialize the SPI block */
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SPI_Init(cfg->level.regs, (SPI_InitTypeDef *)&(cfg->level.init));
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SPI_Init(cfg->mask.regs, (SPI_InitTypeDef *)&(cfg->mask.init));
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/* Enable SPI */
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SPI_Cmd(cfg->level.regs, ENABLE);
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SPI_Cmd(cfg->mask.regs, ENABLE);
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/* Configure DMA for SPI Tx SLAVE Maskbuffer */
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DMA_Cmd(cfg->mask.dma.tx.channel, DISABLE);
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DMA_Init(cfg->mask.dma.tx.channel, (DMA_InitTypeDef *)&(cfg->mask.dma.tx.init));
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/* Configure DMA for SPI Tx SLAVE Framebuffer*/
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DMA_Cmd(cfg->level.dma.tx.channel, DISABLE);
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DMA_Init(cfg->level.dma.tx.channel, (DMA_InitTypeDef *)&(cfg->level.dma.tx.init));
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/* Trigger interrupt when for half conversions too to indicate double buffer */
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DMA_ITConfig(cfg->level.dma.tx.channel, DMA_IT_TC, ENABLE);
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/* Configure and clear buffers */
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draw_buffer_level = buffer0_level;
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draw_buffer_mask = buffer0_mask;
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disp_buffer_level = buffer1_level;
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disp_buffer_mask = buffer1_mask;
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memset(disp_buffer_mask, 0, GRAPHICS_WIDTH * GRAPHICS_HEIGHT);
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memset(disp_buffer_level, 0, GRAPHICS_WIDTH * GRAPHICS_HEIGHT);
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memset(draw_buffer_mask, 0, GRAPHICS_WIDTH * GRAPHICS_HEIGHT);
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memset(draw_buffer_level, 0, GRAPHICS_WIDTH * GRAPHICS_HEIGHT);
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/* Configure DMA interrupt */
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NVIC_Init(&cfg->level.dma.irq.init);
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(cfg->mask.regs, SPI_I2S_DMAReq_Tx, ENABLE);
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SPI_I2S_DMACmd(cfg->level.regs, SPI_I2S_DMAReq_Tx, ENABLE);
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mask_dma = DMA1;
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main_dma = DMA2;
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main_stream = cfg->level.dma.tx.channel;
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mask_stream = cfg->mask.dma.tx.channel;
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/* Configure the Video Line interrupt */
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PIOS_EXTI_Init(cfg->hsync);
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PIOS_EXTI_Init(cfg->vsync);
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// set levels to zero
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PIOS_Servo_Set(0, 0);
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PIOS_Servo_Set(1, 0);
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}
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/**
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* Prepare the system to watch for a HSYNC pulse to trigger the pixel
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* clock and clock out the next line
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*/
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static void prepare_line(uint32_t line_num)
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{
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if (line_num < GRAPHICS_HEIGHT) {
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uint32_t buf_offset = line_num * GRAPHICS_WIDTH;
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dev_cfg->pixel_timer.timer->CNT = dc;
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DMA_ClearFlag(dev_cfg->mask.dma.tx.channel, DMA_FLAG_TCIF7 | DMA_FLAG_HTIF7 | DMA_FLAG_FEIF7 | DMA_FLAG_TEIF7);
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DMA_ClearFlag(dev_cfg->level.dma.tx.channel, DMA_FLAG_FEIF5 | DMA_FLAG_TEIF5);
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// Load new line
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DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel, (uint32_t)&disp_buffer_level[buf_offset], DMA_Memory_0);
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DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel, (uint32_t)&disp_buffer_mask[buf_offset], DMA_Memory_0);
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// Enable DMA, Slave first
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DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel, BUFFER_LINE_LENGTH);
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DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel, BUFFER_LINE_LENGTH);
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SPI_Cmd(dev_cfg->level.regs, ENABLE);
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SPI_Cmd(dev_cfg->mask.regs, ENABLE);
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(dev_cfg->mask.regs, SPI_I2S_DMAReq_Tx, ENABLE);
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SPI_I2S_DMACmd(dev_cfg->level.regs, SPI_I2S_DMAReq_Tx, ENABLE);
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DMA_Cmd(dev_cfg->level.dma.tx.channel, ENABLE);
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DMA_Cmd(dev_cfg->mask.dma.tx.channel, ENABLE);
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}
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reset_hsync_timers();
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}
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void PIOS_VIDEO_DMA_Handler(void);
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void DMA1_Stream7_IRQHandler(void) __attribute__((alias("PIOS_VIDEO_DMA_Handler")));
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void DMA2_Stream5_IRQHandler(void) __attribute__((alias("PIOS_VIDEO_DMA_Handler")));
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/**
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* Check both SPI for the stop sequence before disabling them
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*/
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static void flush_spi()
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{
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bool level_empty = false;
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bool mask_empty = false;
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bool level_stopped = false;
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bool mask_stopped = false;
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// Can't flush if clock not running
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while ((dev_cfg->pixel_timer.timer->CR1 & 0x0001) && (!level_stopped | !mask_stopped)) {
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level_empty |= SPI_I2S_GetFlagStatus(dev_cfg->level.regs, SPI_I2S_FLAG_TXE) == SET;
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mask_empty |= SPI_I2S_GetFlagStatus(dev_cfg->mask.regs, SPI_I2S_FLAG_TXE) == SET;
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if (level_empty && !level_stopped) { // && SPI_I2S_GetFlagStatus(dev_cfg->level.regs ,SPI_I2S_FLAG_BSY) == RESET) {
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SPI_Cmd(dev_cfg->level.regs, DISABLE);
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level_stopped = true;
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}
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if (mask_empty && !mask_stopped) { // && SPI_I2S_GetFlagStatus(dev_cfg->mask.regs ,SPI_I2S_FLAG_BSY) == RESET) {
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SPI_Cmd(dev_cfg->mask.regs, DISABLE);
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mask_stopped = true;
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}
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}
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/*
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uint32_t i = 0;
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while(SPI_I2S_GetFlagStatus(dev_cfg->level.regs ,SPI_I2S_FLAG_TXE) == RESET && i < 30000) i++;
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while(SPI_I2S_GetFlagStatus(dev_cfg->mask.regs ,SPI_I2S_FLAG_TXE) == RESET && i < 30000) i++;
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while(SPI_I2S_GetFlagStatus(dev_cfg->level.regs ,SPI_I2S_FLAG_BSY) == SET && i < 30000) i++;
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while(SPI_I2S_GetFlagStatus(dev_cfg->mask.regs ,SPI_I2S_FLAG_BSY) == SET && i < 30000) i++;*/
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SPI_Cmd(dev_cfg->mask.regs, DISABLE);
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SPI_Cmd(dev_cfg->level.regs, DISABLE);
|
|
}
|
|
|
|
/**
|
|
* @brief Interrupt for half and full buffer transfer
|
|
*/
|
|
void PIOS_VIDEO_DMA_Handler(void)
|
|
{
|
|
// Handle flags from stream channel
|
|
if (DMA_GetFlagStatus(dev_cfg->level.dma.tx.channel, DMA_FLAG_TCIF5)) { // whole double buffer filled
|
|
DMA_ClearFlag(dev_cfg->level.dma.tx.channel, DMA_FLAG_TCIF5);
|
|
if (gActiveLine < GRAPHICS_HEIGHT) {
|
|
flush_spi();
|
|
stop_hsync_timers();
|
|
|
|
dev_cfg->pixel_timer.timer->CNT = dc;
|
|
|
|
prepare_line(gActiveLine);
|
|
} else if (gActiveLine >= GRAPHICS_HEIGHT) {
|
|
// last line completed
|
|
flush_spi();
|
|
stop_hsync_timers();
|
|
|
|
// STOP DMA, master first
|
|
DMA_Cmd(dev_cfg->mask.dma.tx.channel, DISABLE);
|
|
DMA_Cmd(dev_cfg->level.dma.tx.channel, DISABLE);
|
|
}
|
|
gActiveLine++;
|
|
} else if (DMA_GetFlagStatus(dev_cfg->level.dma.tx.channel, DMA_FLAG_HTIF5)) {
|
|
DMA_ClearFlag(dev_cfg->level.dma.tx.channel, DMA_FLAG_HTIF5);
|
|
} else {}
|
|
}
|
|
|
|
#endif /* PIOS_INCLUDE_VIDEO */
|