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https://bitbucket.org/librepilot/librepilot.git
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29237f97ae
transactions should already be completed. Also reset the callback so in the case of noise on the IRQ line it will not keep firing interrupts. I suspect we should probably disable interrupts in this handler to prevent refiring.
653 lines
20 KiB
C
653 lines
20 KiB
C
/**
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @addtogroup PIOS_SPI SPI Functions
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* @brief PIOS interface to read and write from SPI ports
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* @{
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*
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* @file pios_spi.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
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* @brief Hardware Abstraction Layer for SPI ports of STM32
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* @see The GNU Public License (GPL) Version 3
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* @notes
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*
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* Note that additional chip select lines can be easily added by using
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* the remaining free GPIOs of the core module. Shared SPI ports should be
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* arbitrated with (FreeRTOS based) Mutexes to avoid collisions!
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* @todo Clocking is wrong (interface is badly defined, should be speed not prescaler magic numbers)
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* @todo DMA doesn't work. Fix it.
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*/
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#include <pios.h>
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#if defined(PIOS_INCLUDE_SPI)
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#include <pios_spi_priv.h>
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#define SPI_MAX_BLOCK_PIO 128
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static bool PIOS_SPI_validate(struct pios_spi_dev * com_dev)
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{
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/* Should check device magic here */
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return(true);
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}
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#if defined(PIOS_INCLUDE_FREERTOS)
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static struct pios_spi_dev * PIOS_SPI_alloc(void)
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{
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return (malloc(sizeof(struct pios_spi_dev)));
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}
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#else
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static struct pios_spi_dev pios_spi_devs[PIOS_SPI_MAX_DEVS];
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static uint8_t pios_spi_num_devs;
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static struct pios_spi_dev * PIOS_SPI_alloc(void)
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{
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if (pios_spi_num_devs >= PIOS_SPI_MAX_DEVS) {
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return (NULL);
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}
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return (&pios_spi_devs[pios_spi_num_devs++]);
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}
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#endif
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/**
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* Initialises SPI pins
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* \param[in] mode currently only mode 0 supported
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* \return < 0 if initialisation failed
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*/
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int32_t PIOS_SPI_Init(uint32_t * spi_id, const struct pios_spi_cfg * cfg)
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{
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uint32_t init_ssel = 0;
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PIOS_Assert(spi_id);
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PIOS_Assert(cfg);
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struct pios_spi_dev * spi_dev;
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spi_dev = (struct pios_spi_dev *) PIOS_SPI_alloc();
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if (!spi_dev) goto out_fail;
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/* Bind the configuration to the device instance */
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spi_dev->cfg = cfg;
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#if defined(PIOS_INCLUDE_FREERTOS)
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vSemaphoreCreateBinary(spi_dev->busy);
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xSemaphoreGive(spi_dev->busy);
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#endif
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/* Disable callback function */
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spi_dev->callback = NULL;
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/* Set rx/tx dummy bytes to a known value */
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spi_dev->rx_dummy_byte = 0xFF;
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spi_dev->tx_dummy_byte = 0xFF;
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switch (spi_dev->cfg->init.SPI_NSS) {
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case SPI_NSS_Soft:
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if (spi_dev->cfg->init.SPI_Mode == SPI_Mode_Master) {
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/* We're a master in soft NSS mode, make sure we see NSS high at all times. */
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Set);
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/* Init as many slave selects as the config advertises. */
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init_ssel = spi_dev->cfg->slave_count;
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} else {
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/* We're a slave in soft NSS mode, make sure we see NSS low at all times. */
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Reset);
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}
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break;
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case SPI_NSS_Hard:
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/* only legal for single-slave config */
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PIOS_Assert(spi_dev->cfg->slave_count == 1);
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init_ssel = 1;
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/* FIXME: Should this also call SPI_SSOutputCmd()? */
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break;
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default:
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PIOS_Assert(0);
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}
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/* Initialize the GPIO pins */
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/* note __builtin_ctz() due to the difference between GPIO_PinX and GPIO_PinSourceX */
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if (spi_dev->cfg->remap) {
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GPIO_PinAFConfig(spi_dev->cfg->sclk.gpio,
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__builtin_ctz(spi_dev->cfg->sclk.init.GPIO_Pin),
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spi_dev->cfg->remap);
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GPIO_PinAFConfig(spi_dev->cfg->mosi.gpio,
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__builtin_ctz(spi_dev->cfg->mosi.init.GPIO_Pin),
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spi_dev->cfg->remap);
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GPIO_PinAFConfig(spi_dev->cfg->miso.gpio,
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__builtin_ctz(spi_dev->cfg->miso.init.GPIO_Pin),
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spi_dev->cfg->remap);
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for (uint32_t i = 0; i < init_ssel; i++) {
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GPIO_PinAFConfig(spi_dev->cfg->ssel[i].gpio,
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__builtin_ctz(spi_dev->cfg->ssel[i].init.GPIO_Pin),
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spi_dev->cfg->remap);
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}
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}
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GPIO_Init(spi_dev->cfg->sclk.gpio, (GPIO_InitTypeDef*)&(spi_dev->cfg->sclk.init));
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GPIO_Init(spi_dev->cfg->mosi.gpio, (GPIO_InitTypeDef*)&(spi_dev->cfg->mosi.init));
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GPIO_Init(spi_dev->cfg->miso.gpio, (GPIO_InitTypeDef*)&(spi_dev->cfg->miso.init));
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for (uint32_t i = 0; i < init_ssel; i++) {
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/* Since we're driving the SSEL pin in software, ensure that the slave is deselected */
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/* XXX multi-slave support - maybe have another SPI_NSS_ mode? */
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GPIO_SetBits(spi_dev->cfg->ssel[i].gpio, spi_dev->cfg->ssel[i].init.GPIO_Pin);
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GPIO_Init(spi_dev->cfg->ssel[i].gpio, (GPIO_InitTypeDef*)&(spi_dev->cfg->ssel[i].init));
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}
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/* Configure DMA for SPI Rx */
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DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Init(spi_dev->cfg->dma.rx.channel, (DMA_InitTypeDef*)&(spi_dev->cfg->dma.rx.init));
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/* Configure DMA for SPI Tx */
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DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
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DMA_Init(spi_dev->cfg->dma.tx.channel, (DMA_InitTypeDef*)&(spi_dev->cfg->dma.tx.init));
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/* Initialize the SPI block */
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SPI_Init(spi_dev->cfg->regs, (SPI_InitTypeDef*)&(spi_dev->cfg->init));
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/* Configure CRC calculation */
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if (spi_dev->cfg->use_crc) {
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SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
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} else {
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SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
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}
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/* Enable SPI */
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SPI_Cmd(spi_dev->cfg->regs, ENABLE);
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(spi_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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/* Must store this before enabling interrupt */
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*spi_id = (uint32_t)spi_dev;
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/* Configure DMA interrupt */
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NVIC_Init((NVIC_InitTypeDef*)&(spi_dev->cfg->dma.irq.init));
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DMA_ITConfig(spi_dev->cfg->dma.tx.channel, spi_dev->cfg->dma.irq.flags, ENABLE); /* XXX is this correct? */
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return(0);
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out_fail:
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return(-1);
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}
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/**
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* (Re-)initialises SPI peripheral clock rate
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*
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* \param[in] spi SPI number (0 or 1)
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* \param[in] spi_prescaler configures the SPI speed
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* \return 0 if no error
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* \return -1 if disabled SPI port selected
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* \return -3 if invalid spi_prescaler selected
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*/
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int32_t PIOS_SPI_SetClockSpeed(uint32_t spi_id, SPIPrescalerTypeDef spi_prescaler)
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{
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struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(spi_dev);
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PIOS_Assert(valid)
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SPI_InitTypeDef SPI_InitStructure;
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if (spi_prescaler >= 8) {
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/* Invalid prescaler selected */
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return -3;
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}
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/* Start with a copy of the default configuration for the peripheral */
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SPI_InitStructure = spi_dev->cfg->init;
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/* Adjust the prescaler for the peripheral's clock */
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/* XXX is this correct? */
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SPI_InitStructure.SPI_BaudRatePrescaler = ((uint16_t) spi_prescaler & 7) << 3;
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/* Write back the new configuration */
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SPI_Init(spi_dev->cfg->regs, &SPI_InitStructure);
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/* XXX what gets selected by this? */
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PIOS_SPI_TransferByte(spi_id, 0xFF);
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return 0;
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}
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/**
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* Claim the SPI bus semaphore. Calling the SPI functions does not require this
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* \param[in] spi SPI number (0 or 1)
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* \return 0 if no error
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* \return -1 if timeout before claiming semaphore
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*/
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int32_t PIOS_SPI_ClaimBus(uint32_t spi_id)
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{
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#if defined(PIOS_INCLUDE_FREERTOS)
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struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(spi_dev);
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PIOS_Assert(valid)
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if (xSemaphoreTake(spi_dev->busy, 0xffff) != pdTRUE)
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return -1;
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#endif
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return 0;
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}
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/**
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* Claim the SPI bus semaphore from an ISR. Has no timeout.
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* \param[in] spi SPI number (0 or 1)
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* \return 0 if no error
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* \return -1 if timeout before claiming semaphore
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*/
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int32_t PIOS_SPI_ClaimBusISR(uint32_t spi_id)
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{
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#if defined(PIOS_INCLUDE_FREERTOS)
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struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(spi_dev);
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PIOS_Assert(valid)
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if (xQueueGenericReceive(( xQueueHandle ) spi_dev->busy, NULL, 0x0000 , pdFALSE ) != pdTRUE)
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return -1;
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#endif
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return 0;
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}
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/**
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* Release the SPI bus semaphore. Calling the SPI functions does not require this
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* \param[in] spi SPI number (0 or 1)
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* \return 0 if no error
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*/
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int32_t PIOS_SPI_ReleaseBus(uint32_t spi_id)
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{
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#if defined(PIOS_INCLUDE_FREERTOS)
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struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(spi_dev);
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PIOS_Assert(valid)
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xSemaphoreGive(spi_dev->busy);
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#endif
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return 0;
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}
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/**
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* Controls the RC (Register Clock alias Chip Select) pin of a SPI port
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* \param[in] spi SPI number (0 or 1)
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* \param[in] pin_value 0 or 1
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* \return 0 if no error
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*/
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int32_t PIOS_SPI_RC_PinSet(uint32_t spi_id, uint32_t slave_id, uint8_t pin_value)
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{
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struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(spi_dev);
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PIOS_Assert(valid)
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PIOS_Assert(slave_id <= spi_dev->cfg->slave_count)
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/* XXX multi-slave support? */
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if (pin_value) {
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GPIO_SetBits(spi_dev->cfg->ssel[slave_id].gpio, spi_dev->cfg->ssel[slave_id].init.GPIO_Pin);
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} else {
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GPIO_ResetBits(spi_dev->cfg->ssel[slave_id].gpio, spi_dev->cfg->ssel[slave_id].init.GPIO_Pin);
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}
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return 0;
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}
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/**
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* Transfers a byte to SPI output and reads back the return value from SPI input
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* \param[in] spi SPI number (0 or 1)
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* \param[in] b the byte which should be transfered
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*/
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int32_t PIOS_SPI_TransferByte(uint32_t spi_id, uint8_t b)
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{
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struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(spi_dev);
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PIOS_Assert(valid)
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// uint8_t dummy;
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uint8_t rx_byte;
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/*
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* Procedure taken from STM32F10xxx Reference Manual section 23.3.5
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*/
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/* Make sure the RXNE flag is cleared by reading the DR register */
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/*dummy =*/(void)spi_dev->cfg->regs->DR;
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/* Start the transfer */
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spi_dev->cfg->regs->DR = b;
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/* Wait until there is a byte to read */
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while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_RXNE)) ;
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/* Read the rx'd byte */
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rx_byte = spi_dev->cfg->regs->DR;
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/* Wait until the TXE goes high */
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while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_TXE)) ;
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/* Wait for SPI transfer to have fully completed */
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while (spi_dev->cfg->regs->SR & SPI_I2S_FLAG_BSY) ;
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/* Return received byte */
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return rx_byte;
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}
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/**
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* Transfers a block of bytes via DMA.
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* \param[in] spi SPI number (0 or 1)
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* \param[in] send_buffer pointer to buffer which should be sent.<BR>
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* If NULL, 0xff (all-one) will be sent.
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* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
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* If NULL, received bytes will be discarded.
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* \param[in] len number of bytes which should be transfered
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* \param[in] callback pointer to callback function which will be executed
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* from DMA channel interrupt once the transfer is finished.
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* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
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* block until the transfer is finished.
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* \return >= 0 if no error during transfer
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* \return -1 if disabled SPI port selected
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* \return -3 if function has been called during an ongoing DMA transfer
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*/
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static int32_t SPI_DMA_TransferBlock(uint32_t spi_id, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
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{
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struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
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bool valid = PIOS_SPI_validate(spi_dev);
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PIOS_Assert(valid)
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DMA_InitTypeDef dma_init;
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/* Exit if ongoing transfer */
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if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) {
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return -3;
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}
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/* Disable the DMA channels */
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DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
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while(DMA_GetCmdStatus(spi_dev->cfg->dma.rx.channel) == ENABLE);
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while(DMA_GetCmdStatus(spi_dev->cfg->dma.tx.channel) == ENABLE);
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/* Disable the SPI peripheral */
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SPI_Cmd(spi_dev->cfg->regs, DISABLE);
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/* Set callback function */
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spi_dev->callback = callback;
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/*
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* Configure Rx channel
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*/
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/* Start with the default configuration for this peripheral */
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dma_init = spi_dev->cfg->dma.rx.init;
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if (receive_buffer != NULL) {
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/* Enable memory addr. increment - bytes written into receive buffer */
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dma_init.DMA_Memory0BaseAddr = (uint32_t) receive_buffer;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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/* Disable memory addr. increment - bytes written into dummy buffer */
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spi_dev->rx_dummy_byte = 0xFF;
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dma_init.DMA_Memory0BaseAddr = (uint32_t) &spi_dev->rx_dummy_byte;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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if (spi_dev->cfg->use_crc) {
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/* Make sure the CRC error flag is cleared before we start */
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SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
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}
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dma_init.DMA_BufferSize = len;
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DMA_Init(spi_dev->cfg->dma.rx.channel, &(dma_init));
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/*
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* Configure Tx channel
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*/
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/* Start with the default configuration for this peripheral */
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dma_init = spi_dev->cfg->dma.tx.init;
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if (send_buffer != NULL) {
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/* Enable memory addr. increment - bytes written into receive buffer */
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dma_init.DMA_Memory0BaseAddr = (uint32_t) send_buffer;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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/* Disable memory addr. increment - bytes written into dummy buffer */
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spi_dev->tx_dummy_byte = 0xFF;
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dma_init.DMA_Memory0BaseAddr = (uint32_t) &spi_dev->tx_dummy_byte;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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if (spi_dev->cfg->use_crc) {
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/* The last byte of the payload will be replaced with the CRC8 */
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dma_init.DMA_BufferSize = len - 1;
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} else {
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dma_init.DMA_BufferSize = len;
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}
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DMA_Init(spi_dev->cfg->dma.tx.channel, &(dma_init));
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/* Enable DMA interrupt if callback function active */
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DMA_ITConfig(spi_dev->cfg->dma.rx.channel, DMA_IT_TC, (callback != NULL) ? ENABLE : DISABLE);
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/* Flush out the CRC registers */
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SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
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(void)SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
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SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
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/* Make sure to flush out the receive buffer */
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(void)SPI_I2S_ReceiveData(spi_dev->cfg->regs);
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if (spi_dev->cfg->use_crc) {
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/* Need a 0->1 transition to reset the CRC logic */
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SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
|
|
}
|
|
|
|
/* Start DMA transfers */
|
|
DMA_Cmd(spi_dev->cfg->dma.rx.channel, ENABLE);
|
|
DMA_Cmd(spi_dev->cfg->dma.tx.channel, ENABLE);
|
|
|
|
/* Reenable the SPI device */
|
|
SPI_Cmd(spi_dev->cfg->regs, ENABLE);
|
|
|
|
if (callback) {
|
|
/* User has requested a callback, don't wait for the transfer to complete. */
|
|
return 0;
|
|
}
|
|
|
|
/* Wait until all bytes have been transmitted/received */
|
|
while (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel));
|
|
|
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
|
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE)));
|
|
|
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
|
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY));
|
|
|
|
/* Check the CRC on the transfer if enabled. */
|
|
if (spi_dev->cfg->use_crc) {
|
|
/* Check the SPI CRC error flag */
|
|
if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
|
|
return -4;
|
|
}
|
|
}
|
|
|
|
/* No error */
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Transfers a block of bytes via PIO.
|
|
*
|
|
* \param[in] spi_id SPI device handle
|
|
* \param[in] send_buffer pointer to buffer which should be sent.<BR>
|
|
* If NULL, 0xff (all-one) will be sent.
|
|
* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
|
|
* If NULL, received bytes will be discarded.
|
|
* \param[in] len number of bytes which should be transfered
|
|
* \return >= 0 if no error during transfer
|
|
* \return -1 if disabled SPI port selected
|
|
* \return -3 if function has been called during an ongoing DMA transfer
|
|
*/
|
|
static int32_t SPI_PIO_TransferBlock(uint32_t spi_id, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len)
|
|
{
|
|
struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
|
|
uint8_t b;
|
|
|
|
bool valid = PIOS_SPI_validate(spi_dev);
|
|
PIOS_Assert(valid)
|
|
|
|
/* Exit if ongoing transfer */
|
|
if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) {
|
|
return -3;
|
|
}
|
|
|
|
/* Make sure the RXNE flag is cleared by reading the DR register */
|
|
b = spi_dev->cfg->regs->DR;
|
|
|
|
while (len--) {
|
|
/* get the byte to send */
|
|
b = send_buffer ? *(send_buffer++) : 0xff;
|
|
|
|
/* Start the transfer */
|
|
spi_dev->cfg->regs->DR = b;
|
|
|
|
/* Wait until there is a byte to read */
|
|
while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_RXNE)) ;
|
|
|
|
/* Read the rx'd byte */
|
|
b = spi_dev->cfg->regs->DR;
|
|
|
|
/* save the received byte */
|
|
if (receive_buffer)
|
|
*(receive_buffer++) = b;
|
|
|
|
/* Wait until the TXE goes high */
|
|
while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_TXE)) ;
|
|
}
|
|
|
|
/* Wait for SPI transfer to have fully completed */
|
|
while (spi_dev->cfg->regs->SR & SPI_I2S_FLAG_BSY) ;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/**
|
|
* Transfers a block of bytes via PIO or DMA.
|
|
* \param[in] spi_id SPI device handle
|
|
* \param[in] send_buffer pointer to buffer which should be sent.<BR>
|
|
* If NULL, 0xff (all-one) will be sent.
|
|
* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
|
|
* If NULL, received bytes will be discarded.
|
|
* \param[in] len number of bytes which should be transfered
|
|
* \param[in] callback pointer to callback function which will be executed
|
|
* from DMA channel interrupt once the transfer is finished.
|
|
* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
|
|
* block until the transfer is finished.
|
|
* \return >= 0 if no error during transfer
|
|
* \return -1 if disabled SPI port selected
|
|
* \return -3 if function has been called during an ongoing DMA transfer
|
|
*/
|
|
int32_t PIOS_SPI_TransferBlock(uint32_t spi_id, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
|
|
{
|
|
if (callback || len > SPI_MAX_BLOCK_PIO) {
|
|
return SPI_DMA_TransferBlock(spi_id, send_buffer, receive_buffer, len, callback);
|
|
}
|
|
return SPI_PIO_TransferBlock(spi_id, send_buffer, receive_buffer, len);
|
|
}
|
|
|
|
/**
|
|
* Check if a transfer is in progress
|
|
* \param[in] spi SPI number (0 or 1)
|
|
* \return >= 0 if no transfer is in progress
|
|
* \return -1 if disabled SPI port selected
|
|
* \return -2 if unsupported SPI port selected
|
|
* \return -3 if function has been called during an ongoing DMA transfer
|
|
*/
|
|
int32_t PIOS_SPI_Busy(uint32_t spi_id)
|
|
{
|
|
struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
|
|
|
|
bool valid = PIOS_SPI_validate(spi_dev);
|
|
PIOS_Assert(valid)
|
|
|
|
/* DMA buffer has data or SPI transmit register not empty or SPI is busy*/
|
|
if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel) ||
|
|
!SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE) ||
|
|
SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY))
|
|
{
|
|
return -3;
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|
|
void PIOS_SPI_SetPrescalar(uint32_t spi_id, uint32_t prescaler)
|
|
{
|
|
struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
|
|
|
|
bool valid = PIOS_SPI_validate(spi_dev);
|
|
PIOS_Assert(valid);
|
|
PIOS_Assert(IS_SPI_BAUDRATE_PRESCALER(prescaler));
|
|
|
|
spi_dev->cfg->regs->CR1 = (spi_dev->cfg->regs->CR1 & ~0x0038) | prescaler;
|
|
}
|
|
|
|
void PIOS_SPI_IRQ_Handler(uint32_t spi_id)
|
|
{
|
|
struct pios_spi_dev * spi_dev = (struct pios_spi_dev *)spi_id;
|
|
|
|
bool valid = PIOS_SPI_validate(spi_dev);
|
|
PIOS_Assert(valid)
|
|
|
|
// FIXME XXX Only RX channel or better clear flags for both channels?
|
|
DMA_ClearFlag(spi_dev->cfg->dma.rx.channel, spi_dev->cfg->dma.irq.flags);
|
|
|
|
if(spi_dev->cfg->init.SPI_Mode == SPI_Mode_Master) {
|
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
|
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
|
|
|
|
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
|
|
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
|
|
}
|
|
|
|
if (spi_dev->callback != NULL) {
|
|
bool crc_ok = true;
|
|
uint8_t crc_val;
|
|
|
|
if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
|
|
crc_ok = false;
|
|
SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
|
|
}
|
|
crc_val = SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
|
|
spi_dev->callback(crc_ok, crc_val);
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
* @}
|
|
*/
|