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b7771e3ec7
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@2 ebee16cc-31ac-478f-84a7-5cbb03baadba
133 lines
5.1 KiB
C
133 lines
5.1 KiB
C
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
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* File Name : usb_conf.h
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* Author : MCD Application Team
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* Version : V3.1.0
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* Date : 10/30/2009
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* Description : Mass Storage Demo configuration header
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __USB_CONF_H
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#define __USB_CONF_H
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/*-------------------------------------------------------------*/
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/* EP_NUM */
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/* defines how many endpoints are used by the device */
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/*-------------------------------------------------------------*/
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#define EP_NUM (3)
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#ifndef STM32F10X_CL
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/*-------------------------------------------------------------*/
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/* -------------- Buffer Description Table -----------------*/
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/*-------------------------------------------------------------*/
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/* buffer table base address */
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#define BTABLE_ADDRESS (0x00)
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/* EP0 */
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/* rx/tx buffer base address */
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#define ENDP0_RXADDR (0x18)
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#define ENDP0_TXADDR (0x58)
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/* EP1 */
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/* tx buffer base address */
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#define ENDP1_TXADDR (0x98)
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/* EP2 */
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/* Rx buffer base address */
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#define ENDP2_RXADDR (0xD8)
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/* ISTR events */
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/* IMR_MSK */
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/* mask defining which events has to be handled */
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/* by the device application software */
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#define IMR_MSK (CNTR_CTRM | CNTR_RESETM)
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#endif /* STM32F10X_CL */
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/* CTR service routines */
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/* associated to defined endpoints */
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//#define EP1_IN_Callback NOP_Process
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#define EP2_IN_Callback NOP_Process
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#define EP3_IN_Callback NOP_Process
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#define EP4_IN_Callback NOP_Process
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#define EP5_IN_Callback NOP_Process
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#define EP6_IN_Callback NOP_Process
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#define EP7_IN_Callback NOP_Process
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#define EP1_OUT_Callback NOP_Process
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//#define EP2_OUT_Callback NOP_Process
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#define EP3_OUT_Callback NOP_Process
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#define EP4_OUT_Callback NOP_Process
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#define EP5_OUT_Callback NOP_Process
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#define EP6_OUT_Callback NOP_Process
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#define EP7_OUT_Callback NOP_Process
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#ifdef STM32F10X_CL
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/* OTGD-FS-DEVICE IP interrupts Enable definitions */
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/* Uncomment the define to enable the selected interrupt */
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//#define INTR_MODEMISMATCH
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#define INTR_SOFINTR
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#define INTR_RXSTSQLVL /* Mandatory */
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//#define INTR_NPTXFEMPTY
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//#define INTR_GINNAKEFF
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//#define INTR_GOUTNAKEFF
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//#define INTR_ERLYSUSPEND
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#define INTR_USBSUSPEND /* Mandatory */
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#define INTR_USBRESET /* Mandatory */
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#define INTR_ENUMDONE /* Mandatory */
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//#define INTR_ISOOUTDROP
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#define INTR_EOPFRAME
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//#define INTR_EPMISMATCH
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#define INTR_INEPINTR /* Mandatory */
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#define INTR_OUTEPINTR /* Mandatory */
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//#define INTR_INCOMPLISOIN
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//#define INTR_INCOMPLISOOUT
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#define INTR_WKUPINTR /* Mandatory */
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/* OTGD-FS-DEVICE IP interrupts subroutines */
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/* Comment the define to enable the selected interrupt subroutine and replace it
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by user code */
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#define INTR_MODEMISMATCH_Callback NOP_Process
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#define INTR_SOFINTR_Callback NOP_Process
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#define INTR_RXSTSQLVL_Callback NOP_Process
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#define INTR_NPTXFEMPTY_Callback NOP_Process
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#define INTR_NPTXFEMPTY_Callback NOP_Process
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#define INTR_GINNAKEFF_Callback NOP_Process
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#define INTR_GOUTNAKEFF_Callback NOP_Process
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#define INTR_ERLYSUSPEND_Callback NOP_Process
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#define INTR_USBSUSPEND_Callback NOP_Process
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#define INTR_USBRESET_Callback NOP_Process
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#define INTR_ENUMDONE_Callback NOP_Process
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#define INTR_ISOOUTDROP_Callback NOP_Process
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#define INTR_EOPFRAME_Callback NOP_Process
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#define INTR_EPMISMATCH_Callback NOP_Process
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#define INTR_INEPINTR_Callback NOP_Process
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#define INTR_OUTEPINTR_Callback NOP_Process
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#define INTR_INCOMPLISOIN_Callback NOP_Process
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#define INTR_INCOMPLISOOUT_Callback NOP_Process
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#define INTR_WKUPINTR_Callback NOP_Process
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/* Isochronous data update */
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#define INTR_RXSTSQLVL_ISODU_Callback NOP_Process
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/* Isochronous transfer parameters */
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/* Size of a single Isochronous buffer (size of a single transfer) */
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#define ISOC_BUFFER_SZE 1
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/* Number of sub-buffers (number of single buffers/transfers), should be even */
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#define NUM_SUB_BUFFERS 2
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#endif /* STM32F10X_CL */
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#endif /* __USB_CONF_H */
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/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
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