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b7e9c2ee2a
Removes hard-coding of JTAG interface config in the <board>_program make macros. This allows the use of STLINKv2 for F4 boards while continuing to use the FOSS JTAG revB on F1 boards.
32 lines
1.0 KiB
Makefile
32 lines
1.0 KiB
Makefile
BOARD_TYPE := 0x03
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BOARD_REVISION := 0x01
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BOOTLOADER_VERSION := 0x02
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HW_TYPE := 0x01
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MCU := cortex-m3
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CHIP := STM32F103CBT
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BOARD := STM32103CB_PIPXTREME
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MODEL := MD
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MODEL_SUFFIX := _PX
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OPENOCD_CONFIG := stm32f1x.cfg
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OPENOCD_JTAG_CONFIG := foss-jtag.revb.cfg
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OPENOCD_CONFIG := stm32f1x.cfg
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OPENOCD_JTAG_CONFIG := foss-jtag.revb.cfg
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OPENOCD_CONFIG := stm32f1x.cfg
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OPENOCD_JTAG_CONFIG := foss-jtag.revb.cfg
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OPENOCD_CONFIG := stm32f1x.cfg
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# Note: These must match the values in link_$(BOARD)_memory.ld
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BL_BANK_BASE := 0x08000000 # Start of bootloader flash
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BL_BANK_SIZE := 0x00003000 # Should include BD_INFO region
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FW_BANK_BASE := 0x08003000 # Start of firmware flash
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FW_BANK_SIZE := 0x0001CC00 # Should include FW_DESC_SIZE
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EE_BANK_BASE := 0x0801FC00 # EEPROM storage area
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EE_BANK_SIZE := 0x00000400 # Size of EEPROM storage area
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FW_DESC_SIZE := 0x00000064
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