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https://bitbucket.org/librepilot/librepilot.git
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a2d8544931
to make the flight code compile again. Needs careful review, particularly all the fixes for the signed vs unsigned comparisons. +review OPReview-459
381 lines
12 KiB
C
381 lines
12 KiB
C
/**
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @addtogroup PIOS_OVERO OVERO Functions
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* @brief PIOS interface to read and write to overo
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* @{
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*
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* @file pios_overo.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
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* @brief Hardware Abstraction Layer for Overo communications
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* @see The GNU Public License (GPL) Version 3
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* @notes
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <pios.h>
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#ifdef PIOS_INCLUDE_OVERO
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/**
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* Configures the SPI device to use a double buffered DMA for transferring
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* data. At the end of each transfer (NSS goes high) it makes sure to reset
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* the DMA counter to the beginning of each packet and swap to the next
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* buffer
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*/
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#ifdef PIOS_INCLUDE_SPI
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#include <pios_overo_priv.h>
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#define PACKET_SIZE 1024
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/* Provide a COM driver */
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static void PIOS_OVERO_RegisterRxCallback(uint32_t overo_id, pios_com_callback rx_in_cb, uint32_t context);
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static void PIOS_OVERO_RegisterTxCallback(uint32_t overo_id, pios_com_callback tx_out_cb, uint32_t context);
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static void PIOS_OVERO_TxStart(uint32_t overo_id, uint16_t tx_bytes_avail);
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static void PIOS_OVERO_RxStart(uint32_t overo_id, uint16_t rx_bytes_avail);
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const struct pios_com_driver pios_overo_com_driver = {
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.set_baud = NULL,
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.tx_start = PIOS_OVERO_TxStart,
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.rx_start = PIOS_OVERO_RxStart,
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.bind_tx_cb = PIOS_OVERO_RegisterTxCallback,
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.bind_rx_cb = PIOS_OVERO_RegisterRxCallback,
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};
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//! Data types
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enum pios_overo_dev_magic {
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PIOS_OVERO_DEV_MAGIC = 0x85A3834A,
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};
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struct pios_overo_dev {
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enum pios_overo_dev_magic magic;
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const struct pios_overo_cfg * cfg;
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int8_t writing_buffer;
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uint32_t writing_offset;
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uint32_t packets;
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uint8_t tx_buffer[2][PACKET_SIZE];
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uint8_t rx_buffer[2][PACKET_SIZE];
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pios_com_callback rx_in_cb;
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uint32_t rx_in_context;
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pios_com_callback tx_out_cb;
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uint32_t tx_out_context;
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};
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#if defined(PIOS_INCLUDE_FREERTOS)
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//! Private methods
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static void PIOS_OVERO_WriteData(struct pios_overo_dev *overo_dev);
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static bool PIOS_OVERO_validate(struct pios_overo_dev * overo_dev);
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static struct pios_overo_dev * PIOS_OVERO_alloc(void);
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static bool PIOS_OVERO_validate(struct pios_overo_dev * overo_dev)
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{
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return (overo_dev->magic == PIOS_OVERO_DEV_MAGIC);
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}
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static struct pios_overo_dev * PIOS_OVERO_alloc(void)
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{
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struct pios_overo_dev * overo_dev;
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overo_dev = (struct pios_overo_dev *)pvPortMalloc(sizeof(*overo_dev));
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if (!overo_dev) return(NULL);
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overo_dev->rx_in_cb = 0;
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overo_dev->rx_in_context = 0;
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overo_dev->tx_out_cb = 0;
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overo_dev->tx_out_context = 0;
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overo_dev->packets = 0;
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overo_dev->magic = PIOS_OVERO_DEV_MAGIC;
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return(overo_dev);
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}
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/**
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* Take data from the PIOS_COM buffer and transfer it to the currently inactive DMA
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* circular buffer
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*/
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static void PIOS_OVERO_WriteData(struct pios_overo_dev *overo_dev)
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{
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// TODO: How do we protect against the DMA buffer swapping midway through adding data
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// to this buffer. If we were writing at the beginning it could cause a weird race.
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if (overo_dev->tx_out_cb) {
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int32_t max_bytes = PACKET_SIZE - overo_dev->writing_offset;
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if (max_bytes > 0) {
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uint16_t bytes_added;
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bool tx_need_yield = false;
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uint8_t *writing_pointer = &overo_dev->tx_buffer[overo_dev->writing_buffer][overo_dev->writing_offset];
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bytes_added = (overo_dev->tx_out_cb)(overo_dev->tx_out_context, writing_pointer, max_bytes, NULL, &tx_need_yield);
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#if defined(OVERO_USES_BLOCKING_WRITE)
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if (tx_need_yield) {
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vPortYieldFromISR();
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}
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#endif
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overo_dev->writing_offset += bytes_added;
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}
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}
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}
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/**
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* Called at the end of each DMA transaction. Refresh the flag indicating which
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* DMA buffer to write new data from the PIOS_COM fifo into the buffer
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*/
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void PIOS_OVERO_DMA_irq_handler(uint32_t overo_id)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *) overo_id;
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if(!PIOS_OVERO_validate(overo_dev))
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return;
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DMA_ClearFlag(overo_dev->cfg->dma.tx.channel, overo_dev->cfg->dma.irq.flags);
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overo_dev->writing_buffer = 1 - DMA_GetCurrentMemoryTarget(overo_dev->cfg->dma.tx.channel);
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overo_dev->writing_offset = 0;
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/* bool rx_need_yield;
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// Get data from the Rx buffer and add to the fifo
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(void) (overo_dev->rx_in_cb)(overo_dev->rx_in_context,
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&overo_dev->rx_buffer[overo_dev->writing_buffer][0],
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PACKET_SIZE, NULL, &rx_need_yield);
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if(rx_need_yield) {
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vPortYieldFromISR();
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}
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// Fill the buffer with known value to prevent rereading these bytes
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memset(&overo_dev->rx_buffer[overo_dev->writing_buffer][0], 0xFF, PACKET_SIZE);
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*/
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// Fill the buffer with known value to prevent resending any bytes
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memset(&overo_dev->tx_buffer[overo_dev->writing_buffer][0], 0xFF, PACKET_SIZE);
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// Load any pending bytes from TX fifo
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PIOS_OVERO_WriteData(overo_dev);
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overo_dev->packets++;
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}
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/**
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* Debugging information to check how it is runnign
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*/
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int32_t PIOS_OVERO_GetPacketCount(uint32_t overo_id)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *) overo_id;
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PIOS_Assert(PIOS_OVERO_validate(overo_dev));
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return overo_dev->packets;
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}
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/**
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* Debugging information to check how it is runnign
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*/
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int32_t PIOS_OVERO_GetWrittenBytes(uint32_t overo_id)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *) overo_id;
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PIOS_Assert(PIOS_OVERO_validate(overo_dev));
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return overo_dev->writing_offset;
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}
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/**
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* Initialise a single Overo device
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*/
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int32_t PIOS_OVERO_Init(uint32_t * overo_id, const struct pios_overo_cfg * cfg)
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{
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PIOS_DEBUG_Assert(overo_id);
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PIOS_DEBUG_Assert(cfg);
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struct pios_overo_dev *overo_dev;
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overo_dev = (struct pios_overo_dev *) PIOS_OVERO_alloc();
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if (!overo_dev) goto out_fail;
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/* Bind the configuration to the device instance */
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overo_dev->cfg = cfg;
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overo_dev->writing_buffer = 1; // First writes to second buffer
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/* Put buffers to a known state */
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memset(&overo_dev->tx_buffer[0][0], 0xFF, PACKET_SIZE);
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memset(&overo_dev->tx_buffer[1][0], 0xFF, PACKET_SIZE);
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memset(&overo_dev->rx_buffer[0][0], 0xFF, PACKET_SIZE);
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memset(&overo_dev->rx_buffer[1][0], 0xFF, PACKET_SIZE);
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/*
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* Enable the SPI device
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*
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* 1. Enable the SPI port
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* 2. Enable DMA with circular buffered DMA (validate config)
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* 3. Enable the DMA Tx IRQ
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*/
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//PIOS_Assert(overo_dev->cfg->dma.tx-> == CIRCULAR);
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//PIOS_Assert(overo_dev->cfg->dma.rx-> == CIRCULAR);
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/* only legal for single-slave config */
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PIOS_Assert(overo_dev->cfg->slave_count == 1);
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SPI_SSOutputCmd(overo_dev->cfg->regs, DISABLE);
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/* Initialize the GPIO pins */
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/* note __builtin_ctz() due to the difference between GPIO_PinX and GPIO_PinSourceX */
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GPIO_PinAFConfig(overo_dev->cfg->sclk.gpio,
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__builtin_ctz(overo_dev->cfg->sclk.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->mosi.gpio,
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__builtin_ctz(overo_dev->cfg->mosi.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->miso.gpio,
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__builtin_ctz(overo_dev->cfg->miso.init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_PinAFConfig(overo_dev->cfg->ssel[0].gpio,
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__builtin_ctz(overo_dev->cfg->ssel[0].init.GPIO_Pin),
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overo_dev->cfg->remap);
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GPIO_Init(overo_dev->cfg->sclk.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->sclk.init));
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GPIO_Init(overo_dev->cfg->mosi.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->mosi.init));
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GPIO_Init(overo_dev->cfg->miso.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->miso.init));
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/* Configure circular buffer targets. Configure 0 to be initially active */
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DMA_InitTypeDef dma_init;
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DMA_DeInit(overo_dev->cfg->dma.rx.channel);
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dma_init = overo_dev->cfg->dma.rx.init;
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dma_init.DMA_Memory0BaseAddr = (uint32_t) overo_dev->rx_buffer[0];
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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dma_init.DMA_BufferSize = PACKET_SIZE;
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DMA_Init(overo_dev->cfg->dma.rx.channel, &dma_init);
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DMA_DoubleBufferModeConfig(overo_dev->cfg->dma.rx.channel, (uint32_t) overo_dev->rx_buffer[1], DMA_Memory_0);
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DMA_DoubleBufferModeCmd(overo_dev->cfg->dma.rx.channel, ENABLE);
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DMA_DeInit(overo_dev->cfg->dma.tx.channel);
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dma_init = overo_dev->cfg->dma.tx.init;
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dma_init.DMA_Memory0BaseAddr = (uint32_t) overo_dev->tx_buffer[0];
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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dma_init.DMA_BufferSize = PACKET_SIZE;
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DMA_Init(overo_dev->cfg->dma.tx.channel, &dma_init);
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DMA_DoubleBufferModeConfig(overo_dev->cfg->dma.tx.channel, (uint32_t) overo_dev->tx_buffer[1], DMA_Memory_0);
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DMA_DoubleBufferModeCmd(overo_dev->cfg->dma.tx.channel, ENABLE);
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/* Set the packet size */
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DMA_SetCurrDataCounter(overo_dev->cfg->dma.rx.channel, PACKET_SIZE);
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DMA_SetCurrDataCounter(overo_dev->cfg->dma.tx.channel, PACKET_SIZE);
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/* Initialize the SPI block */
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SPI_DeInit(overo_dev->cfg->regs);
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SPI_Init(overo_dev->cfg->regs, (SPI_InitTypeDef*)&(overo_dev->cfg->init));
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SPI_CalculateCRC(overo_dev->cfg->regs, DISABLE);
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/* Enable SPI */
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SPI_Cmd(overo_dev->cfg->regs, ENABLE);
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(overo_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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/* Configure DMA interrupt */
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NVIC_Init((NVIC_InitTypeDef*)&(overo_dev->cfg->dma.irq.init));
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DMA_ITConfig(overo_dev->cfg->dma.tx.channel, DMA_IT_TC, ENABLE);
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/* Enable the DMA channels */
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DMA_Cmd(overo_dev->cfg->dma.tx.channel, ENABLE);
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DMA_Cmd(overo_dev->cfg->dma.rx.channel, ENABLE);
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*overo_id = (uint32_t) overo_dev;
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return(0);
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out_fail:
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return(-1);
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}
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static void PIOS_OVERO_RxStart(uint32_t overo_id, __attribute__((unused)) uint16_t rx_bytes_avail)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid);
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// DMA RX enable (enable IRQ) ?
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}
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static void PIOS_OVERO_TxStart(uint32_t overo_id, __attribute__((unused)) uint16_t tx_bytes_avail)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid);
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// DMA TX enable (enable IRQ) ?
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// Load any pending bytes from TX fifo
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//PIOS_OVERO_WriteData(overo_dev);
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}
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static void PIOS_OVERO_RegisterRxCallback(uint32_t overo_id, pios_com_callback rx_in_cb, uint32_t context)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid);
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/*
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* Order is important in these assignments since ISR uses _cb
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* field to determine if it's ok to dereference _cb and _context
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*/
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overo_dev->rx_in_context = context;
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overo_dev->rx_in_cb = rx_in_cb;
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}
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static void PIOS_OVERO_RegisterTxCallback(uint32_t overo_id, pios_com_callback tx_out_cb, uint32_t context)
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{
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struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
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bool valid = PIOS_OVERO_validate(overo_dev);
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PIOS_Assert(valid);
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/*
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* Order is important in these assignments since ISR uses _cb
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* field to determine if it's ok to dereference _cb and _context
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*/
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overo_dev->tx_out_context = context;
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overo_dev->tx_out_cb = tx_out_cb;
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}
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#else
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static void PIOS_OVERO_RegisterTxCallback(uint32_t overo_id, pios_com_callback tx_out_cb, uint32_t context) {};
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static void PIOS_OVERO_RegisterRxCallback(uint32_t overo_id, pios_com_callback rx_in_cb, uint32_t context) {};
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static void PIOS_OVERO_TxStart(uint32_t overo_id, uint16_t tx_bytes_avail) {};
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static void PIOS_OVERO_RxStart(uint32_t overo_id, uint16_t rx_bytes_avail) {};
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#endif /* PIOS_INCLUDE_FREERTOS */
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#endif /* PIOS_INCLUDE_SPI */
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#endif /* PIOS_INCLUDE_OVERO */
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/**
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* @}
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* @}
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*/
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