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https://github.com/doitsujin/dxvk.git
synced 2025-01-18 02:52:10 +01:00
[dxvk] Defer host barriers until the end of the current command buffer
This commit is contained in:
parent
72de8a1dc1
commit
044e2e9dff
@ -12,7 +12,6 @@ namespace dxvk {
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| VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
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| VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
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| VK_ACCESS_TRANSFER_READ_BIT
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| VK_ACCESS_TRANSFER_READ_BIT
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| VK_ACCESS_HOST_READ_BIT
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| VK_ACCESS_MEMORY_READ_BIT
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| VK_ACCESS_MEMORY_READ_BIT
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT;
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT;
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@ -21,11 +20,36 @@ namespace dxvk {
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| VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_TRANSFER_WRITE_BIT
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| VK_ACCESS_TRANSFER_WRITE_BIT
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| VK_ACCESS_HOST_WRITE_BIT
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| VK_ACCESS_MEMORY_WRITE_BIT
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| VK_ACCESS_MEMORY_WRITE_BIT
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| VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
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| VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT;
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT;
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constexpr static VkAccessFlags AccessDeviceMask
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= AccessWriteMask | AccessReadMask;
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constexpr static VkAccessFlags AccessHostMask
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= VK_ACCESS_HOST_READ_BIT
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| VK_ACCESS_HOST_WRITE_BIT;
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constexpr static VkPipelineStageFlags StageDeviceMask
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= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
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| VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
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| VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
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| VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
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| VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
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| VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
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| VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
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| VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
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| VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
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| VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
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| VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
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| VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
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| VK_PIPELINE_STAGE_TRANSFER_BIT
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| VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
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| VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
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| VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
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| VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT;
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DxvkBarrierSet:: DxvkBarrierSet(DxvkCmdBuffer cmdBuffer)
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DxvkBarrierSet:: DxvkBarrierSet(DxvkCmdBuffer cmdBuffer)
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: m_cmdBuffer(cmdBuffer) {
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: m_cmdBuffer(cmdBuffer) {
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@ -45,12 +69,18 @@ namespace dxvk {
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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m_allBarrierSrcStages |= srcStages;
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m_allBarrierSrcStages |= srcStages;
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m_memBarrier.srcStageMask |= srcStages;
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m_memBarrier.srcStageMask |= srcStages & StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages;
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m_memBarrier.dstStageMask |= dstStages & StageDeviceMask;
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if (access.test(DxvkAccess::Write))
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if (access.test(DxvkAccess::Write)) {
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m_memBarrier.dstAccessMask |= dstAccess;
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m_memBarrier.dstAccessMask |= dstAccess & AccessDeviceMask;
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if (dstAccess & AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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}
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}
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}
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}
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@ -63,12 +93,18 @@ namespace dxvk {
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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m_allBarrierSrcStages |= srcStages;
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m_allBarrierSrcStages |= srcStages;
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m_memBarrier.srcStageMask |= srcStages;
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m_memBarrier.srcStageMask |= srcStages & StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages;
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m_memBarrier.dstStageMask |= dstStages & StageDeviceMask;
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if (access.test(DxvkAccess::Write))
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if (access.test(DxvkAccess::Write)) {
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m_memBarrier.dstAccessMask |= dstAccess;
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m_memBarrier.dstAccessMask |= dstAccess & AccessDeviceMask;
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if (dstAccess & AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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}
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}
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m_bufSlices.insert(bufSlice.handle,
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m_bufSlices.insert(bufSlice.handle,
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DxvkBarrierBufferSlice(bufSlice.offset, bufSlice.length, access));
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DxvkBarrierBufferSlice(bufSlice.offset, bufSlice.length, access));
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@ -86,21 +122,27 @@ namespace dxvk {
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VkAccessFlags dstAccess) {
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VkAccessFlags dstAccess) {
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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m_allBarrierSrcStages |= srcStages;
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m_allBarrierSrcStages |= srcStages & StageDeviceMask;
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if (srcLayout == dstLayout) {
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if (srcLayout == dstLayout) {
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m_memBarrier.srcStageMask |= srcStages;
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m_memBarrier.srcStageMask |= srcStages & StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages;
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m_memBarrier.dstStageMask |= dstStages & StageDeviceMask;
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if (access.test(DxvkAccess::Write))
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if (access.test(DxvkAccess::Write)) {
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m_memBarrier.dstAccessMask |= dstAccess;
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m_memBarrier.dstAccessMask |= dstAccess;
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if (dstAccess & AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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}
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}
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} else {
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} else {
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VkImageMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2 };
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VkImageMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2 };
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barrier.srcStageMask = srcStages;
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barrier.srcStageMask = srcStages & StageDeviceMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.dstStageMask = dstStages;
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barrier.dstStageMask = dstStages & StageDeviceMask;
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barrier.dstAccessMask = dstAccess;
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barrier.dstAccessMask = dstAccess & AccessDeviceMask;
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barrier.oldLayout = srcLayout;
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barrier.oldLayout = srcLayout;
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barrier.newLayout = dstLayout;
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barrier.newLayout = dstLayout;
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barrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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barrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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@ -110,6 +152,11 @@ namespace dxvk {
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barrier.subresourceRange.aspectMask = image->formatInfo()->aspectMask;
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barrier.subresourceRange.aspectMask = image->formatInfo()->aspectMask;
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m_imgBarriers.push_back(barrier);
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m_imgBarriers.push_back(barrier);
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if (dstAccess & AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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}
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access.set(DxvkAccess::Write);
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access.set(DxvkAccess::Write);
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}
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}
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@ -132,7 +179,7 @@ namespace dxvk {
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m_allBarrierSrcStages |= srcStages;
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m_allBarrierSrcStages |= srcStages;
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VkBufferMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2 };
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VkBufferMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2 };
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barrier.srcStageMask = srcStages;
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barrier.srcStageMask = srcStages & StageDeviceMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
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barrier.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
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barrier.dstAccessMask = 0;
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barrier.dstAccessMask = 0;
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@ -149,6 +196,11 @@ namespace dxvk {
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barrier.dstAccessMask = dstAccess;
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barrier.dstAccessMask = dstAccess;
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acquire.m_bufBarriers.push_back(barrier);
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acquire.m_bufBarriers.push_back(barrier);
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if (dstAccess & AccessHostMask) {
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acquire.m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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acquire.m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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}
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DxvkAccessFlags access(DxvkAccess::Read, DxvkAccess::Write);
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DxvkAccessFlags access(DxvkAccess::Read, DxvkAccess::Write);
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release.m_bufSlices.insert(bufSlice.handle,
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release.m_bufSlices.insert(bufSlice.handle,
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DxvkBarrierBufferSlice(bufSlice.offset, bufSlice.length, access));
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DxvkBarrierBufferSlice(bufSlice.offset, bufSlice.length, access));
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@ -174,7 +226,7 @@ namespace dxvk {
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m_allBarrierSrcStages |= srcStages;
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m_allBarrierSrcStages |= srcStages;
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VkImageMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2 };
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VkImageMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2 };
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barrier.srcStageMask = srcStages;
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barrier.srcStageMask = srcStages & StageDeviceMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
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barrier.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
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barrier.dstAccessMask = 0;
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barrier.dstAccessMask = 0;
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@ -196,6 +248,11 @@ namespace dxvk {
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barrier.dstAccessMask = dstAccess;
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barrier.dstAccessMask = dstAccess;
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acquire.m_imgBarriers.push_back(barrier);
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acquire.m_imgBarriers.push_back(barrier);
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if (dstAccess & AccessHostMask) {
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acquire.m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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acquire.m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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}
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DxvkAccessFlags access(DxvkAccess::Read, DxvkAccess::Write);
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DxvkAccessFlags access(DxvkAccess::Read, DxvkAccess::Write);
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release.m_imgSlices.insert(image->handle(),
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release.m_imgSlices.insert(image->handle(),
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DxvkBarrierImageSlice(subresources, access));
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DxvkBarrierImageSlice(subresources, access));
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@ -236,6 +293,22 @@ namespace dxvk {
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}
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}
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void DxvkBarrierSet::finalize(const Rc<DxvkCommandList>& commandList) {
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// Emit host barrier if necessary
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if (m_hostBarrierSrcStages) {
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m_memBarrier.srcStageMask |= m_hostBarrierSrcStages;
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m_memBarrier.srcAccessMask |= VK_ACCESS_MEMORY_WRITE_BIT;
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m_memBarrier.dstStageMask |= VK_PIPELINE_STAGE_HOST_BIT;
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m_memBarrier.dstAccessMask |= m_hostBarrierDstAccess;
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m_hostBarrierSrcStages = 0;
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m_hostBarrierDstAccess = 0;
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}
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this->recordCommands(commandList);
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}
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void DxvkBarrierSet::recordCommands(const Rc<DxvkCommandList>& commandList) {
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void DxvkBarrierSet::recordCommands(const Rc<DxvkCommandList>& commandList) {
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VkDependencyInfo depInfo = { VK_STRUCTURE_TYPE_DEPENDENCY_INFO };
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VkDependencyInfo depInfo = { VK_STRUCTURE_TYPE_DEPENDENCY_INFO };
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@ -270,7 +343,7 @@ namespace dxvk {
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m_memBarrier.srcAccessMask = 0;
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m_memBarrier.srcAccessMask = 0;
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m_memBarrier.dstStageMask = 0;
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m_memBarrier.dstStageMask = 0;
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m_memBarrier.dstAccessMask = 0;
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m_memBarrier.dstAccessMask = 0;
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m_bufBarriers.resize(0);
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m_bufBarriers.resize(0);
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m_imgBarriers.resize(0);
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m_imgBarriers.resize(0);
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@ -576,6 +576,9 @@ namespace dxvk {
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return m_allBarrierSrcStages;
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return m_allBarrierSrcStages;
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}
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}
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void finalize(
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const Rc<DxvkCommandList>& commandList);
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void recordCommands(
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void recordCommands(
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const Rc<DxvkCommandList>& commandList);
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const Rc<DxvkCommandList>& commandList);
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@ -603,6 +606,9 @@ namespace dxvk {
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DxvkCmdBuffer m_cmdBuffer;
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DxvkCmdBuffer m_cmdBuffer;
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VkPipelineStageFlags2 m_hostBarrierSrcStages = 0;
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VkAccessFlags2 m_hostBarrierDstAccess = 0;
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VkPipelineStageFlags2 m_allBarrierSrcStages = 0;
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VkPipelineStageFlags2 m_allBarrierSrcStages = 0;
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VkMemoryBarrier2 m_memBarrier = { VK_STRUCTURE_TYPE_MEMORY_BARRIER_2 };
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VkMemoryBarrier2 m_memBarrier = { VK_STRUCTURE_TYPE_MEMORY_BARRIER_2 };
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@ -6226,9 +6226,9 @@ namespace dxvk {
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this->spillRenderPass(true);
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this->spillRenderPass(true);
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this->flushSharedImages();
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this->flushSharedImages();
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m_sdmaBarriers.recordCommands(m_cmd);
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m_sdmaBarriers.finalize(m_cmd);
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m_initBarriers.recordCommands(m_cmd);
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m_initBarriers.finalize(m_cmd);
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m_execBarriers.recordCommands(m_cmd);
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m_execBarriers.finalize(m_cmd);
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}
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}
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