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[dxbc] Implemented 64-bit compare instructions

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This commit is contained in:
Philip Rebohle 2018-06-07 15:21:30 +02:00
parent a89eb15546
commit 10170a89ab
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2 changed files with 38 additions and 8 deletions
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22
src/dxbc/dxbc_compiler.cpp
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@ -1630,13 +1630,23 @@ namespace dxvk {
// (dst0) The destination register // (dst0) The destination register
// (src0) The first vector to compare // (src0) The first vector to compare
// (src1) The second vector to compare // (src1) The second vector to compare
uint32_t componentCount = ins.dst[0].mask.popCount();
// For 64-bit operations, we'll return a 32-bit
// vector, so we have to adjust the read mask
DxbcRegMask srcMask = ins.dst[0].mask;
if (isDoubleType(ins.src[0].dataType)) {
srcMask = DxbcRegMask(
componentCount > 0, componentCount > 0,
componentCount > 1, componentCount > 1);
}
const std::array<DxbcRegisterValue, 2> src = { const std::array<DxbcRegisterValue, 2> src = {
emitRegisterLoad(ins.src[0], ins.dst[0].mask), emitRegisterLoad(ins.src[0], srcMask),
emitRegisterLoad(ins.src[1], ins.dst[0].mask), emitRegisterLoad(ins.src[1], srcMask),
}; };
const uint32_t componentCount = ins.dst[0].mask.popCount();
// Condition, which is a boolean vector used // Condition, which is a boolean vector used
// to select between the ~0u and 0u vectors. // to select between the ~0u and 0u vectors.
uint32_t condition = 0; uint32_t condition = 0;
@ -1647,21 +1657,25 @@ namespace dxvk {
switch (ins.op) { switch (ins.op) {
case DxbcOpcode::Eq: case DxbcOpcode::Eq:
case DxbcOpcode::DEq:
condition = m_module.opFOrdEqual( condition = m_module.opFOrdEqual(
conditionType, src.at(0).id, src.at(1).id); conditionType, src.at(0).id, src.at(1).id);
break; break;
case DxbcOpcode::Ge: case DxbcOpcode::Ge:
case DxbcOpcode::DGe:
condition = m_module.opFOrdGreaterThanEqual( condition = m_module.opFOrdGreaterThanEqual(
conditionType, src.at(0).id, src.at(1).id); conditionType, src.at(0).id, src.at(1).id);
break; break;
case DxbcOpcode::Lt: case DxbcOpcode::Lt:
case DxbcOpcode::DLt:
condition = m_module.opFOrdLessThan( condition = m_module.opFOrdLessThan(
conditionType, src.at(0).id, src.at(1).id); conditionType, src.at(0).id, src.at(1).id);
break; break;
case DxbcOpcode::Ne: case DxbcOpcode::Ne:
case DxbcOpcode::DNe:
condition = m_module.opFOrdNotEqual( condition = m_module.opFOrdNotEqual(
conditionType, src.at(0).id, src.at(1).id); conditionType, src.at(0).id, src.at(1).id);
break; break;

24
src/dxbc/dxbc_defs.cpp
View File

@ -982,13 +982,29 @@ namespace dxvk {
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 }, { DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
} }, } },
/* DEq */ /* DEq */
{ }, { 3, DxbcInstClass::VectorCmp, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
} },
/* DGe */ /* DGe */
{ }, { 3, DxbcInstClass::VectorCmp, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
} },
/* DLt */ /* DLt */
{ }, { 3, DxbcInstClass::VectorCmp, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
} },
/* DNe */ /* DNe */
{ }, { 3, DxbcInstClass::VectorCmp, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float64 },
} },
/* DMov */ /* DMov */
{ 2, DxbcInstClass::VectorAlu, { { 2, DxbcInstClass::VectorAlu, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Float64 }, { DxbcOperandKind::DstReg, DxbcScalarType::Float64 },